arm64: Update the ID_AA64MMFR1_EL1 fields

Sponsored by:	Arm Ltd
Differential Revision:	https://reviews.freebsd.org/D40891

sys/arm64/arm64/identcpu.c

@@ -1051,6 +1051,41 @@ static const struct mrs_field id_aa64mmfr0_fields[] = {
 
 
 /* ID_AA64MMFR1_EL1 */
+static const struct mrs_field_value id_aa64mmfr1_cmovw[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, CMOVW, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr1_tidcp1[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, TIDCP1, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr1_ntlbpa[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, nTLBPA, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr1_afp[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, AFP, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr1_hcx[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, HCX, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr1_ets[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, ETS, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
+static const struct mrs_field_value id_aa64mmfr1_twed[] = {
+	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, TWED, NONE, IMPL),
+	MRS_FIELD_VALUE_END,
+};
+
 static const struct mrs_field_value id_aa64mmfr1_xnx[] = {
 	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, XNX, NONE, IMPL),
 	MRS_FIELD_VALUE_END,
@@ -1064,6 +1099,7 @@ static const struct mrs_field_value id_aa64mmfr1_specsei[] = {
 static const struct mrs_field_value id_aa64mmfr1_pan[] = {
 	MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, PAN, NONE, IMPL),
 	MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_ATS1E1, "PAN+ATS1E1"),
+	MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_EPAN, "EPAN"),
 	MRS_FIELD_VALUE_END,
 };
 
@@ -1098,6 +1134,13 @@ static const struct mrs_field_value id_aa64mmfr1_hafdbs[] = {
 };
 
 static const struct mrs_field id_aa64mmfr1_fields[] = {
+	MRS_FIELD(ID_AA64MMFR1, CMOVW, false, MRS_EXACT, id_aa64mmfr1_cmovw),
+	MRS_FIELD(ID_AA64MMFR1, TIDCP1, false, MRS_EXACT, id_aa64mmfr1_tidcp1),
+	MRS_FIELD(ID_AA64MMFR1, nTLBPA, false, MRS_EXACT, id_aa64mmfr1_ntlbpa),
+	MRS_FIELD(ID_AA64MMFR1, AFP, false, MRS_EXACT, id_aa64mmfr1_afp),
+	MRS_FIELD(ID_AA64MMFR1, HCX, false, MRS_EXACT, id_aa64mmfr1_hcx),
+	MRS_FIELD(ID_AA64MMFR1, ETS, false, MRS_EXACT, id_aa64mmfr1_ets),
+	MRS_FIELD(ID_AA64MMFR1, TWED, false, MRS_EXACT, id_aa64mmfr1_twed),
 	MRS_FIELD(ID_AA64MMFR1, XNX, false, MRS_EXACT, id_aa64mmfr1_xnx),
 	MRS_FIELD(ID_AA64MMFR1, SpecSEI, false, MRS_EXACT,
 	    id_aa64mmfr1_specsei),

sys/arm64/include/armreg.h

@@ -933,6 +933,7 @@
 #define	 ID_AA64MMFR1_PAN_NONE		(UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
 #define	 ID_AA64MMFR1_PAN_IMPL		(UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
 #define	 ID_AA64MMFR1_PAN_ATS1E1	(UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
+#define	 ID_AA64MMFR1_PAN_EPAN		(UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
 #define	ID_AA64MMFR1_SpecSEI_SHIFT	24
 #define	ID_AA64MMFR1_SpecSEI_MASK	(UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
 #define	ID_AA64MMFR1_SpecSEI_VAL(x)	((x) & ID_AA64MMFR1_SpecSEI_MASK)
@@ -943,6 +944,41 @@
 #define	ID_AA64MMFR1_XNX_VAL(x)		((x) & ID_AA64MMFR1_XNX_MASK)
 #define	 ID_AA64MMFR1_XNX_NONE		(UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
 #define	 ID_AA64MMFR1_XNX_IMPL		(UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
+#define	ID_AA64MMFR1_TWED_SHIFT		32
+#define	ID_AA64MMFR1_TWED_MASK		(UL(0xf) << ID_AA64MMFR1_TWED_SHIFT)
+#define	ID_AA64MMFR1_TWED_VAL(x)	((x) & ID_AA64MMFR1_TWED_MASK)
+#define	 ID_AA64MMFR1_TWED_NONE		(UL(0x0) << ID_AA64MMFR1_TWED_SHIFT)
+#define	 ID_AA64MMFR1_TWED_IMPL		(UL(0x1) << ID_AA64MMFR1_TWED_SHIFT)
+#define	ID_AA64MMFR1_ETS_SHIFT		36
+#define	ID_AA64MMFR1_ETS_MASK		(UL(0xf) << ID_AA64MMFR1_ETS_SHIFT)
+#define	ID_AA64MMFR1_ETS_VAL(x)		((x) & ID_AA64MMFR1_ETS_MASK)
+#define	 ID_AA64MMFR1_ETS_NONE		(UL(0x0) << ID_AA64MMFR1_ETS_SHIFT)
+#define	 ID_AA64MMFR1_ETS_IMPL		(UL(0x1) << ID_AA64MMFR1_ETS_SHIFT)
+#define	ID_AA64MMFR1_HCX_SHIFT		40
+#define	ID_AA64MMFR1_HCX_MASK		(UL(0xf) << ID_AA64MMFR1_HCX_SHIFT)
+#define	ID_AA64MMFR1_HCX_VAL(x)		((x) & ID_AA64MMFR1_HCX_MASK)
+#define	 ID_AA64MMFR1_HCX_NONE		(UL(0x0) << ID_AA64MMFR1_HCX_SHIFT)
+#define	 ID_AA64MMFR1_HCX_IMPL		(UL(0x1) << ID_AA64MMFR1_HCX_SHIFT)
+#define	ID_AA64MMFR1_AFP_SHIFT		44
+#define	ID_AA64MMFR1_AFP_MASK		(UL(0xf) << ID_AA64MMFR1_AFP_SHIFT)
+#define	ID_AA64MMFR1_AFP_VAL(x)		((x) & ID_AA64MMFR1_AFP_MASK)
+#define	 ID_AA64MMFR1_AFP_NONE		(UL(0x0) << ID_AA64MMFR1_AFP_SHIFT)
+#define	 ID_AA64MMFR1_AFP_IMPL		(UL(0x1) << ID_AA64MMFR1_AFP_SHIFT)
+#define	ID_AA64MMFR1_nTLBPA_SHIFT	48
+#define	ID_AA64MMFR1_nTLBPA_MASK	(UL(0xf) << ID_AA64MMFR1_nTLBPA_SHIFT)
+#define	ID_AA64MMFR1_nTLBPA_VAL(x)	((x) & ID_AA64MMFR1_nTLBPA_MASK)
+#define	 ID_AA64MMFR1_nTLBPA_NONE	(UL(0x0) << ID_AA64MMFR1_nTLBPA_SHIFT)
+#define	 ID_AA64MMFR1_nTLBPA_IMPL	(UL(0x1) << ID_AA64MMFR1_nTLBPA_SHIFT)
+#define	ID_AA64MMFR1_TIDCP1_SHIFT	52
+#define	ID_AA64MMFR1_TIDCP1_MASK	(UL(0xf) << ID_AA64MMFR1_TIDCP1_SHIFT)
+#define	ID_AA64MMFR1_TIDCP1_VAL(x)	((x) & ID_AA64MMFR1_TIDCP1_MASK)
+#define	 ID_AA64MMFR1_TIDCP1_NONE	(UL(0x0) << ID_AA64MMFR1_TIDCP1_SHIFT)
+#define	 ID_AA64MMFR1_TIDCP1_IMPL	(UL(0x1) << ID_AA64MMFR1_TIDCP1_SHIFT)
+#define	ID_AA64MMFR1_CMOVW_SHIFT	56
+#define	ID_AA64MMFR1_CMOVW_MASK		(UL(0xf) << ID_AA64MMFR1_CMOVW_SHIFT)
+#define	ID_AA64MMFR1_CMOVW_VAL(x)	((x) & ID_AA64MMFR1_CMOVW_MASK)
+#define	 ID_AA64MMFR1_CMOVW_NONE	(UL(0x0) << ID_AA64MMFR1_CMOVW_SHIFT)
+#define	 ID_AA64MMFR1_CMOVW_IMPL	(UL(0x1) << ID_AA64MMFR1_CMOVW_SHIFT)
 
 /* ID_AA64MMFR2_EL1 */
 #define	ID_AA64MMFR2_EL1		MRS_REG(ID_AA64MMFR2_EL1)