arm64: Update the ID_AA64MMFR0_EL1 fields
While here move to decimal for the _op and _CR definitions to be used by a future macro to define the register when the assembler doesn't know about it. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D40890
This commit is contained in:
Andrew Turner
@@ -935,6 +935,17 @@ static const struct mrs_field id_aa64isar2_fields[] = {
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/* ID_AA64MMFR0_EL1 */
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static const struct mrs_field_value id_aa64mmfr0_ecv[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ECV, NONE, IMPL),
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MRS_FIELD_VALUE(ID_AA64MMFR0_ECV_CNTHCTL, "ECV+CNTHCTL"),
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MRS_FIELD_VALUE_END,
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};
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static const struct mrs_field_value id_aa64mmfr0_fgt[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, FGT, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static const struct mrs_field_value id_aa64mmfr0_exs[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL),
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MRS_FIELD_VALUE_END,
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@@ -944,6 +955,7 @@ static const struct mrs_field_value id_aa64mmfr0_tgran4_2[] = {
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""),
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"),
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"),
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_LPA2, "S2 TGran4+LPA2"),
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MRS_FIELD_VALUE_END,
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};
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@@ -958,11 +970,13 @@ static const struct mrs_field_value id_aa64mmfr0_tgran16_2[] = {
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""),
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"),
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"),
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_LPA2, "S2 TGran16+LPA2"),
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MRS_FIELD_VALUE_END,
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};
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static const struct mrs_field_value id_aa64mmfr0_tgran4[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4,NONE, IMPL),
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL),
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_LPA2, "TGran4+LPA2"),
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MRS_FIELD_VALUE_END,
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};
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@@ -973,6 +987,7 @@ static const struct mrs_field_value id_aa64mmfr0_tgran64[] = {
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static const struct mrs_field_value id_aa64mmfr0_tgran16[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL),
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MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_LPA2, "TGran16+LPA2"),
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MRS_FIELD_VALUE_END,
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};
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@@ -1009,6 +1024,8 @@ static const struct mrs_field_value id_aa64mmfr0_parange[] = {
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};
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static const struct mrs_field id_aa64mmfr0_fields[] = {
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MRS_FIELD(ID_AA64MMFR0, ECV, false, MRS_EXACT, id_aa64mmfr0_ecv),
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MRS_FIELD(ID_AA64MMFR0, FGT, false, MRS_EXACT, id_aa64mmfr0_fgt),
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MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_EXACT, id_aa64mmfr0_exs),
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MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_EXACT,
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id_aa64mmfr0_tgran4_2),
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+25
-10
@@ -804,11 +804,11 @@
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/* ID_AA64MMFR0_EL1 */
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#define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1)
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#define ID_AA64MMFR0_EL1_op0 0x3
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#define ID_AA64MMFR0_EL1_op1 0x0
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#define ID_AA64MMFR0_EL1_CRn 0x0
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#define ID_AA64MMFR0_EL1_CRm 0x7
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#define ID_AA64MMFR0_EL1_op2 0x0
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#define ID_AA64MMFR0_EL1_op0 3
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#define ID_AA64MMFR0_EL1_op1 0
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#define ID_AA64MMFR0_EL1_CRn 0
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#define ID_AA64MMFR0_EL1_CRm 7
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#define ID_AA64MMFR0_EL1_op2 0
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#define ID_AA64MMFR0_PARange_SHIFT 0
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#define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
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#define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK)
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@@ -844,6 +844,7 @@
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#define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK)
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#define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
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#define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
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#define ID_AA64MMFR0_TGran16_LPA2 (UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT)
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#define ID_AA64MMFR0_TGran64_SHIFT 24
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#define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
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#define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK)
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@@ -853,6 +854,7 @@
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#define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
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#define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK)
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#define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
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#define ID_AA64MMFR0_TGran4_LPA2 (UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT)
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#define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
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#define ID_AA64MMFR0_TGran16_2_SHIFT 32
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#define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
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@@ -860,6 +862,7 @@
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#define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
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#define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
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#define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
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#define ID_AA64MMFR0_TGran16_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT)
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#define ID_AA64MMFR0_TGran64_2_SHIFT 36
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#define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
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#define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK)
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@@ -872,19 +875,31 @@
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#define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
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#define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
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#define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
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#define ID_AA64MMFR0_TGran4_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT)
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#define ID_AA64MMFR0_ExS_SHIFT 44
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#define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
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#define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK)
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#define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
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#define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
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#define ID_AA64MMFR0_FGT_SHIFT 56
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#define ID_AA64MMFR0_FGT_MASK (UL(0xf) << ID_AA64MMFR0_FGT_SHIFT)
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#define ID_AA64MMFR0_FGT_VAL(x) ((x) & ID_AA64MMFR0_FGT_MASK)
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#define ID_AA64MMFR0_FGT_NONE (UL(0x0) << ID_AA64MMFR0_FGT_SHIFT)
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#define ID_AA64MMFR0_FGT_IMPL (UL(0x1) << ID_AA64MMFR0_FGT_SHIFT)
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#define ID_AA64MMFR0_ECV_SHIFT 60
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#define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT)
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#define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK)
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#define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT)
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#define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT)
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#define ID_AA64MMFR0_ECV_CNTHCTL (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT)
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/* ID_AA64MMFR1_EL1 */
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#define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1)
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#define ID_AA64MMFR1_EL1_op0 0x3
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#define ID_AA64MMFR1_EL1_op1 0x0
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#define ID_AA64MMFR1_EL1_CRn 0x0
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#define ID_AA64MMFR1_EL1_CRm 0x7
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#define ID_AA64MMFR1_EL1_op2 0x1
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#define ID_AA64MMFR1_EL1_op0 3
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#define ID_AA64MMFR1_EL1_op1 0
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#define ID_AA64MMFR1_EL1_CRn 0
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#define ID_AA64MMFR1_EL1_CRm 7
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#define ID_AA64MMFR1_EL1_op2 1
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#define ID_AA64MMFR1_HAFDBS_SHIFT 0
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#define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
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#define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
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