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Import device-tree files from Linux 6.17

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This commit is contained in:
Emmanuel Vadot
2025-11-22 12:29:08 +01:00
parent b8aada787c
commit d50fbf3559
1212 changed files with 67407 additions and 8013 deletions
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Bindings/arm/amlogic.yaml
+1
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@@ -135,6 +135,7 @@ properties:
- minix,neo-u9h
- nexbox,a1
- tronsmart,vega-s96
- ugoos,am3
- videostrong,gxm-kiii-pro
- wetek,core2
- const: amlogic,s912
Bindings/arm/arm,trace-buffer-extension.yaml
+5 -5
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@@ -41,10 +41,10 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
...
Bindings/arm/aspeed/aspeed.yaml
+2
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@@ -87,6 +87,7 @@ properties:
- facebook,greatlakes-bmc
- facebook,harma-bmc
- facebook,minerva-cmc
- facebook,santabarbara-bmc
- facebook,yosemite4-bmc
- ibm,blueridge-bmc
- ibm,everest-bmc
@@ -98,6 +99,7 @@ properties:
- inventec,starscream-bmc
- inventec,transformer-bmc
- jabil,rbp-bmc
- nvidia,gb200nvl-bmc
- qcom,dc-scm-v1-bmc
- quanta,s6q-bmc
- ufispace,ncplite-bmc
Bindings/arm/axiado.yaml
+23
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@@ -0,0 +1,23 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/axiado.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axiado Platforms
maintainers:
- Harshit Shah <hshah@axiado.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: AX3000 based boards
items:
- enum:
- axiado,ax3000-evk # Axiado AX3000 Evaluation Board
- const: axiado,ax3000 # Axiado AX3000 SoC
additionalProperties: true
Bindings/arm/cix.yaml
+26
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@@ -0,0 +1,26 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CIX platforms
maintainers:
- Peter Chen <peter.chen@cixtech.com>
- Fugang Duan <fugang.duan@cixtech.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Radxa Orion O6
items:
- const: radxa,orion-o6
- const: cix,sky1
additionalProperties: true
...
Bindings/arm/cpus.yaml
+1
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@@ -200,6 +200,7 @@ properties:
- qcom,kryo385
- qcom,kryo465
- qcom,kryo468
- qcom,kryo470
- qcom,kryo485
- qcom,kryo560
- qcom,kryo570
Bindings/arm/fsl.yaml
+18
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@@ -89,6 +89,7 @@ properties:
- description: i.MX28 based Boards
items:
- enum:
- amarula,imx28-rmm
- armadeus,imx28-apf28 # APF28 SoM
- bluegiga,apx4devkit # Bluegiga APx4 SoM on dev board
- crystalfontz,cfa10036 # Crystalfontz CFA-10036 SoM
@@ -769,6 +770,15 @@ properties:
- const: dh,imx6ull-dhcor-som
- const: fsl,imx6ull
- description: i.MX6ULL Engicam MicroGEA SoM based boards
items:
- enum:
- engicam,microgea-imx6ull-bmm # i.MX6ULL Engicam MicroGEA BMM Board
- engicam,microgea-imx6ull-gtw # i.MX6ULL Engicam MicroGEA GTW Board
- engicam,microgea-imx6ull-rmm # i.MX6ULL Engicam MicroGEA RMM Board
- const: engicam,microgea-imx6ull # i.MX6ULL Engicam MicroGEA SoM
- const: fsl,imx6ull
- description: i.MX6ULL PHYTEC phyBOARD-Segin
items:
- enum:
@@ -1095,6 +1105,7 @@ properties:
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
- gocontroll,moduline-display # GOcontroll Moduline Display controller
- skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
@@ -1395,6 +1406,13 @@ properties:
- fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
- const: fsl,imx95
- description: PHYTEC i.MX 95 FPSC based Boards
items:
- enum:
- phytec,imx95-libra-rdk-fpsc # Libra-i.MX 95 FPSC
- const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC
- const: fsl,imx95
- description: i.MXRT1050 based Boards
items:
- enum:
Bindings/arm/mediatek.yaml
+9 -3
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@@ -27,6 +27,11 @@ properties:
- enum:
- mediatek,mt2712-evb
- const: mediatek,mt2712
- items:
- enum:
- jty,d101
- lenovo,a369i
- const: mediatek,mt6572
- items:
- enum:
- mediatek,mt6580-evbp1
@@ -302,6 +307,10 @@ properties:
- const: google,steelix-sku196608
- const: google,steelix
- const: mediatek,mt8186
- description: Google Squirtle (Acer Chromebook Spin 311 (R724T)
items:
- const: google,squirtle
- const: mediatek,mt8186
- description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
items:
- const: google,starmie-sku0
@@ -350,9 +359,6 @@ properties:
- const: mediatek,mt8186
- description: Google Voltorb (Acer Chromebook 311 C723/C732T)
items:
- enum:
- google,voltorb-sku589824
- google,voltorb-sku589825
- const: google,voltorb
- const: mediatek,mt8186
- items:
Bindings/arm/mrvl/mrvl.yaml
+5
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@@ -35,6 +35,11 @@ properties:
- enum:
- dell,wyse-ariel
- const: marvell,mmp3
- description: PXA1908 based boards
items:
- enum:
- samsung,coreprimevelte
- const: marvell,pxa1908
additionalProperties: true
Bindings/arm/qcom.yaml
+6
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@@ -209,6 +209,7 @@ properties:
- samsung,hlte
- sony,xperia-amami
- sony,xperia-honami
- sony,xperia-togari
- const: qcom,msm8974
- items:
@@ -230,6 +231,11 @@ properties:
- const: qcom,msm8974pro
- const: qcom,msm8974
- items:
- enum:
- longcheer,l9360
- const: qcom,msm8976
- items:
- enum:
- acer,a1-724
Bindings/arm/rockchip.yaml
+28
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@@ -258,6 +258,11 @@ properties:
- const: firefly,rk3566-roc-pc
- const: rockchip,rk3566
- description: Firefly Station M3
items:
- const: firefly,rk3588s-roc-pc
- const: rockchip,rk3588s
- description: Firefly Station P2
items:
- const: firefly,rk3568-roc-pc
@@ -295,6 +300,12 @@ properties:
- friendlyarm,nanopi-r4s-enterprise
- const: rockchip,rk3399
- description: FriendlyElec NanoPi M5 series boards
items:
- enum:
- friendlyarm,nanopi-m5
- const: rockchip,rk3576
- description: FriendlyElec NanoPi R5 series boards
items:
- enum:
@@ -715,6 +726,13 @@ properties:
- const: lckfb,tspi-rk3566
- const: rockchip,rk3566
- description: Luckfox Core3576 Module based boards
items:
- enum:
- luckfox,omni3576
- const: luckfox,core3576
- const: rockchip,rk3576
- description: Lunzn FastRhino R66S / R68S
items:
- enum:
@@ -961,6 +979,11 @@ properties:
- const: radxa,rock-s0
- const: rockchip,rk3308
- description: Radxa ROCK 5T
items:
- const: radxa,rock-5t
- const: rockchip,rk3588
- description: Radxa ZERO 3W/3E
items:
- enum:
@@ -1109,6 +1132,11 @@ properties:
- const: rockchip,rk3588-toybrick-x0
- const: rockchip,rk3588
- description: Sakura Pi RK3308B
items:
- const: sakurapi,rk3308-sakurapi-rk3308b
- const: rockchip,rk3308
- description: Sinovoip RK3308 Banana Pi P2 Pro
items:
- const: sinovoip,rk3308-bpi-p2pro
Bindings/arm/rockchip/pmu.yaml
+2
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@@ -25,6 +25,7 @@ select:
- rockchip,rk3288-pmu
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3528-pmu
- rockchip,rk3562-pmu
- rockchip,rk3568-pmu
- rockchip,rk3576-pmu
@@ -44,6 +45,7 @@ properties:
- rockchip,rk3288-pmu
- rockchip,rk3368-pmu
- rockchip,rk3399-pmu
- rockchip,rk3528-pmu
- rockchip,rk3562-pmu
- rockchip,rk3568-pmu
- rockchip,rk3576-pmu
Bindings/arm/samsung/samsung-boards.yaml
+6
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@@ -45,6 +45,12 @@ properties:
- const: samsung,aries
- const: samsung,s5pv210
- description: Exynos2200 based boards
items:
- enum:
- samsung,g0s # Samsung Galaxy S22+ (SM-S906B)
- const: samsung,exynos2200
- description: Exynos3250 based boards
items:
- enum:
Bindings/arm/stm32/st,mlahb.yaml
+10 -10
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@@ -55,17 +55,17 @@ unevaluatedProperties: false
examples:
- |
ahb {
compatible = "st,mlahb", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma-ranges = <0x00000000 0x38000000 0x10000>,
<0x10000000 0x10000000 0x60000>,
<0x30000000 0x30000000 0x60000>;
compatible = "st,mlahb", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma-ranges = <0x00000000 0x38000000 0x10000>,
<0x10000000 0x10000000 0x60000>,
<0x30000000 0x30000000 0x60000>;
m4_rproc: m4@10000000 {
reg = <0x10000000 0x40000>;
};
m4_rproc: m4@10000000 {
reg = <0x10000000 0x40000>;
};
};
...
Bindings/arm/stm32/stm32.yaml
+1
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@@ -121,6 +121,7 @@ properties:
- st,stm32mp157a-dk1-scmi
- st,stm32mp157c-dk2
- st,stm32mp157c-dk2-scmi
- st,stm32mp157f-dk2
- const: st,stm32mp157
- items:
Bindings/arm/sunxi.yaml
+14 -22
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@@ -341,15 +341,11 @@ properties:
- const: allwinner,i12-tvbox
- const: allwinner,sun7i-a20
- description: ICnova A20 ADB4006
- description: ICnova A20
items:
- const: incircuit,icnova-a20-adb4006
- const: incircuit,icnova-a20
- const: allwinner,sun7i-a20
- description: ICNova A20 SWAC
items:
- const: incircuit,icnova-a20-swac
- enum:
- incircuit,icnova-a20-adb4006
- incircuit,icnova-a20-swac
- const: incircuit,icnova-a20
- const: allwinner,sun7i-a20
@@ -760,21 +756,12 @@ properties:
- const: pine64,pinebook
- const: allwinner,sun50i-a64
- description: Pine64 PinePhone Developer Batch (1.0)
- description: Pine64 PinePhone
items:
- const: pine64,pinephone-1.0
- const: pine64,pinephone
- const: allwinner,sun50i-a64
- description: Pine64 PinePhone Braveheart (1.1)
items:
- const: pine64,pinephone-1.1
- const: pine64,pinephone
- const: allwinner,sun50i-a64
- description: Pine64 PinePhone (1.2)
items:
- const: pine64,pinephone-1.2
- enum:
- pine64,pinephone-1.0 # Developer Batch (1.0)
- pine64,pinephone-1.1 # Braveheart (1.1)
- pine64,pinephone-1.2
- const: pine64,pinephone
- const: allwinner,sun50i-a64
@@ -996,6 +983,11 @@ properties:
- const: xunlong,orangepi-3
- const: allwinner,sun50i-h6
- description: Xunlong OrangePi 4A
items:
- const: xunlong,orangepi-4a
- const: allwinner,sun55i-t527
- description: Xunlong OrangePi Lite
items:
- const: xunlong,orangepi-lite
Bindings/arm/tegra.yaml
+13
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@@ -52,6 +52,10 @@ properties:
- nvidia,cardhu-a04
- const: nvidia,cardhu
- const: nvidia,tegra30
- description: ASUS Portable AiO P1801-T
items:
- const: asus,p1801-t
- const: nvidia,tegra30
- description: ASUS Transformers Device family
items:
- enum:
@@ -61,6 +65,10 @@ properties:
- asus,tf300tl
- asus,tf700t
- const: nvidia,tegra30
- description: Asus VivoTab RT
items:
- const: asus,tf600t
- const: nvidia,tegra30
- description: LG Optimus 4X P880
items:
- const: lg,p880
@@ -242,5 +250,10 @@ properties:
- const: nvidia,p3768-0000+p3767-0005
- const: nvidia,p3767-0005
- const: nvidia,tegra234
- description: NVIDIA P3971-0089+P3834-0008 Engineering Reference Platform
items:
- const: nvidia,p3971-0089+p3834-0008
- const: nvidia,p3834-0008
- const: nvidia,tegra264
additionalProperties: true
Bindings/arm/tegra/nvidia,tegra186-pmc.yaml
+1
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@@ -16,6 +16,7 @@ properties:
- nvidia,tegra186-pmc
- nvidia,tegra194-pmc
- nvidia,tegra234-pmc
- nvidia,tegra264-pmc
reg:
minItems: 4
Bindings/arm/ti/k3.yaml
+6
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@@ -25,6 +25,12 @@ properties:
- ti,am62a7-sk
- const: ti,am62a7
- description: K3 AM62D2 SoC and Boards
items:
- enum:
- ti,am62d2-evm
- const: ti,am62d2
- description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra
items:
- const: phytec,am62a7-phyboard-lyra-rdk
Bindings/arm/ti/omap.yaml
+1
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@@ -107,6 +107,7 @@ properties:
- compulab,cm-t335
- moxa,uc-8100-me-t
- novatech,am335x-lxm
- seeed,am335x-bone-green-eco
- ti,am335x-bone
- ti,am335x-evm
- ti,am3359-icev2
Bindings/bus/fsl,imx8mp-aipstz.yaml
+104
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@@ -0,0 +1,104 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/fsl,imx8mp-aipstz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Secure AHB to IP Slave bus (AIPSTZ) bridge
description:
The secure AIPS bridge (AIPSTZ) acts as a bridge for AHB masters issuing
transactions to IP Slave peripherals. Additionally, this module offers access
control configurations meant to restrict which peripherals a master can
access.
maintainers:
- Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
properties:
compatible:
const: fsl,imx8mp-aipstz
reg:
maxItems: 1
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
"#access-controller-cells":
const: 3
description:
First cell - consumer ID
Second cell - consumer type (master or peripheral)
Third cell - configuration value
ranges: true
# borrowed from simple-bus.yaml, no additional requirements for children
patternProperties:
"@(0|[1-9a-f][0-9a-f]*)$":
type: object
additionalProperties: true
properties:
reg:
items:
minItems: 2
maxItems: 4
minItems: 1
maxItems: 1024
ranges:
oneOf:
- items:
minItems: 3
maxItems: 7
minItems: 1
maxItems: 1024
- $ref: /schemas/types.yaml#/definitions/flag
anyOf:
- required:
- reg
- required:
- ranges
required:
- compatible
- reg
- power-domains
- "#address-cells"
- "#size-cells"
- "#access-controller-cells"
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus@30df0000 {
compatible = "fsl,imx8mp-aipstz";
reg = <0x30df0000 0x10000>;
ranges = <0x30c00000 0x30c00000 0x400000>;
power-domains = <&pgc_audio>;
#address-cells = <1>;
#size-cells = <1>;
#access-controller-cells = <3>;
dma-controller@30e00000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30e00000 0x10000>;
#dma-cells = <3>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
<&clk IMX8MP_CLK_AUDIO_ROOT>;
clock-names = "ipg", "ahb";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
};
Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
+5 -2
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@@ -103,11 +103,14 @@ examples:
clock-names = "msi", "ahb";
power-domains = <&pd IMX_SC_R_DC_0>;
syscon@56221000 {
compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
bus@56221000 {
compatible = "simple-pm-bus", "syscon";
reg = <0x56221000 0x1000>;
clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
clock-names = "ipg";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pxl2dpi {
compatible = "fsl,imx8qxp-pxl2dpi";
Bindings/clock/alphascale,asm9260-clock-controller.yaml
+49
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@@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/alphascale,asm9260-clock-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Alphascale Clock Controller
maintainers:
- Oleksij Rempel <linux@rempel-privat.de>
description: |
The ACC (Alphascale Clock Controller) is responsible for choosing proper
clock source, setting dividers and clock gates.
Simple one-cell clock specifier format is used, where the only cell is used
as an index of the clock inside the provider.
It is encouraged to use dt-binding for clock index definitions. SoC specific
dt-binding should be included to the device tree descriptor. For example
Alphascale ASM9260:
#include <dt-bindings/clock/alphascale,asm9260.h>
This binding contains two types of clock providers:
_AHB_ - AHB gate;
_SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
All clock specific details can be found in the SoC documentation.
properties:
compatible:
const: alphascale,asm9260-clock-controller
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
Bindings/clock/apm,xgene-device-clock.yaml
+80
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@@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene SoC device clocks
maintainers:
- Khuong Dinh <khuong@os.amperecomputing.com>
properties:
compatible:
const: apm,xgene-device-clock
reg:
minItems: 1
maxItems: 2
reg-names:
items:
- enum: [ csr-reg, div-reg ]
- const: div-reg
minItems: 1
clocks:
maxItems: 1
"#clock-cells":
const: 1
clock-output-names:
maxItems: 1
clock-names:
maxItems: 1
csr-offset:
description: Offset to the CSR reset register
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
csr-mask:
description: CSR reset mask bit
$ref: /schemas/types.yaml#/definitions/uint32
default: 0xf
enable-offset:
description: Offset to the enable register
$ref: /schemas/types.yaml#/definitions/uint32
default: 8
enable-mask:
description: CSR enable mask bit
$ref: /schemas/types.yaml#/definitions/uint32
default: 0xf
divider-offset:
description: Offset to the divider register
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
divider-width:
description: Width of the divider register
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
divider-shift:
description: Bit shift of the divider register
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
required:
- compatible
- reg
- clocks
- '#clock-cells'
- clock-output-names
additionalProperties: false
Bindings/clock/apm,xgene-socpll-clock.yaml
+50
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@@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/apm,xgene-socpll-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene SoC PLL, PCPPLL, and PMD clocks
maintainers:
- Khuong Dinh <khuong@os.amperecomputing.com>
properties:
compatible:
items:
- enum:
- apm,xgene-pcppll-clock
- apm,xgene-pcppll-v2-clock
- apm,xgene-pmd-clock
- apm,xgene-socpll-clock
- apm,xgene-socpll-v2-clock
reg:
maxItems: 1
reg-names:
items:
- enum: [ csr-reg, div-reg ]
- const: div-reg
minItems: 1
clocks:
maxItems: 1
clock-names:
enum: [ pcppll, socpll ]
"#clock-cells":
const: 1
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- clock-output-names
additionalProperties: false
Bindings/clock/axis,artpec6-clkctrl.yaml
+55
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@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/axis,artpec6-clkctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axis ARTPEC-6 clock controller
maintainers:
- Lars Persson <lars.persson@axis.com>
properties:
compatible:
const: axis,artpec6-clkctrl
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
minItems: 1
items:
- description: external 50 MHz oscillator.
- description: optional audio reference clock.
- description: fractional audio clock divider 0.
- description: fractional audio clock divider 1.
clock-names:
minItems: 1
items:
- const: sys_refclk
- const: i2s_refclk
- const: frac_clk0
- const: frac_clk1
required:
- compatible
- reg
- "#clock-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
clock-controller@f8000000 {
compatible = "axis,artpec6-clkctrl";
reg = <0xf8000000 0x48>;
#clock-cells = <1>;
clocks = <&ext_clk>;
clock-names = "sys_refclk";
};
Bindings/clock/brcm,bcm2835-cprman.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,bcm2835-cprman.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM2835 CPRMAN clocks
maintainers:
- Stefan Wahren <wahrenst@gmx.net>
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
description:
The CPRMAN clock controller generates clocks in the audio power domain of the
BCM2835. There is a level of PLLs deriving from an external oscillator, a
level of PLL dividers that produce channels off of the few PLLs, and a level
of mostly-generic clock generators sourcing from the PLL channels. Most other
hardware components source from the clock generators, but a few (like the ARM
or HDMI) will source from the PLL dividers directly.
properties:
compatible:
enum:
- brcm,bcm2711-cprman
- brcm,bcm2835-cprman
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 1
items:
- description: External oscillator clock.
- description: DSI0 byte clock.
- description: DSI0 DDR2 clock.
- description: DSI0 DDR clock.
- description: DSI1 byte clock.
- description: DSI1 DDR2 clock.
- description: DSI1 DDR clock.
additionalProperties: false
required:
- compatible
- '#clock-cells'
- reg
- clocks
examples:
- |
clock-controller@7e101000 {
compatible = "brcm,bcm2835-cprman";
reg = <0x7e101000 0x2000>;
#clock-cells = <1>;
clocks = <&clk_osc>;
};
Bindings/clock/brcm,bcm53573-ilp.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,bcm53573-ilp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM53573 ILP clock
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
description: >
ILP clock (sometimes referred as "slow clock") on Broadcom BCM53573 devices
using Cortex-A7 CPU.
ILP's rate has to be calculated on runtime and it depends on ALP clock which
has to be referenced.
This clock is part of PMU (Power Management Unit), a Broadcom device handling
power-related aspects. Its node must be sub-node of the PMU device.
properties:
compatible:
items:
- const: brcm,bcm53573-ilp
clocks:
maxItems: 1
'#clock-cells':
const: 0
clock-output-names:
items:
- const: ilp
additionalProperties: false
examples:
- |
ilp {
compatible = "brcm,bcm53573-ilp";
clocks = <&alp>;
#clock-cells = <0>;
clock-output-names = "ilp";
};
Bindings/clock/brcm,bcm63xx-clocks.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,bcm63xx-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS based BCM63XX SoCs Gated Clock Controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
properties:
compatible:
enum:
- brcm,bcm3368-clocks
- brcm,bcm6318-clocks
- brcm,bcm6318-ubus-clocks
- brcm,bcm6328-clocks
- brcm,bcm6358-clocks
- brcm,bcm6362-clocks
- brcm,bcm6368-clocks
- brcm,bcm63268-clocks
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@10000004 {
compatible = "brcm,bcm6328-clocks";
reg = <0x10000004 0x4>;
#clock-cells = <1>;
};
Bindings/clock/cirrus,ep7209-clk.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/cirrus,ep7209-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic CLPS711X Clock Controller
maintainers:
- Alexander Shiyan <shc_work@mail.ru>
description:
See include/dt-bindings/clock/clps711x-clock.h for the full list of CLPS711X
clock IDs.
properties:
compatible:
items:
- const: cirrus,ep7312-clk
- const: cirrus,ep7209-clk
reg:
maxItems: 1
startup-frequency:
description: Factory set CPU startup frequency in HZ.
$ref: /schemas/types.yaml#/definitions/uint32
"#clock-cells":
const: 1
required:
- compatible
- reg
- startup-frequency
- "#clock-cells"
additionalProperties: false
examples:
- |
clock-controller@80000000 {
compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
reg = <0x80000000 0xc000>;
#clock-cells = <1>;
startup-frequency = <73728000>;
};
Bindings/clock/img,pistachio-clk.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/img,pistachio-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Imagination Technologies Pistachio SoC clock controllers
maintainers:
- Andrew Bresticker <abrestic@chromium.org>
description: |
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
general control, and top general control) which are instantiated individually
from the device-tree.
Core clock controller:
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
co-processor), audio, and several peripherals.
Peripheral clock controller:
The peripheral clock controller generates clocks for the DDR, ROM, and other
peripherals. The peripheral system clock ("periph_sys") generated by the core
clock controller is the input clock to the peripheral clock controller.
Peripheral general control:
The peripheral general control block generates system interface clocks and
resets for various peripherals. It also contains miscellaneous peripheral
control registers.
Top-level general control:
The top-level general control block contains miscellaneous control registers
and gates for the external clocks "audio_clk_in" and "enet_clk_in".
properties:
compatible:
items:
- enum:
- img,pistachio-clk
- img,pistachio-clk-periph
- img,pistachio-cr-periph
- img,pistachio-cr-top
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: img,pistachio-clk
then:
properties:
clocks:
items:
- description: External 52Mhz oscillator
- description: Alternate audio reference clock
- description: Alternate ethernet PHY clock
clock-names:
items:
- const: xtal
- const: audio_refclk_ext_gate
- const: ext_enet_in_gate
- if:
properties:
compatible:
contains:
const: img,pistachio-clk-periph
then:
properties:
clocks:
items:
- description: Peripheral system clock
clock-names:
items:
- const: periph_sys_core
- if:
properties:
compatible:
contains:
const: img,pistachio-cr-periph
then:
properties:
clocks:
items:
- description: System interface clock
clock-names:
items:
- const: sys
- if:
properties:
compatible:
contains:
const: img,pistachio-cr-top
then:
properties:
clocks:
items:
- description: External audio reference clock
- description: External ethernet PHY clock
clock-names:
items:
- const: audio_clk_in
- const: enet_clk_in
additionalProperties: false
Bindings/clock/lsi,axm5516-clks.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2025 LSI
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/lsi,axm5516-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LSI AXM5516 Clock Controller
maintainers:
- Anders Berg <anders.berg@lsi.com>
description:
See <dt-bindings/clock/lsi,axxia-clock.h> for the list of supported clock IDs.
properties:
compatible:
const: lsi,axm5516-clks
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <1>;
clock-controller@2010020000 {
compatible = "lsi,axm5516-clks";
#clock-cells = <1>;
reg = <0x20 0x10020000 0x20000>;
};
};
Bindings/clock/lsi,nspire-cx-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/lsi,nspire-cx-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI-NSPIRE Clocks
maintainers:
- Daniel Tang <dt.tangr@gmail.com>
properties:
compatible:
enum:
- lsi,nspire-cx-ahb-divider
- lsi,nspire-classic-ahb-divider
- lsi,nspire-cx-clock
- lsi,nspire-classic-clock
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 0
additionalProperties: false
required:
- compatible
- reg
Bindings/clock/marvell,armada-370-corediv-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/marvell,armada-370-corediv-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MVEBU Core Divider Clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
oneOf:
- enum:
- marvell,armada-370-corediv-clock
- marvell,armada-375-corediv-clock
- marvell,armada-380-corediv-clock
- marvell,mv98dx3236-corediv-clock
- items:
- const: marvell,armada-390-corediv-clock
- const: marvell,armada-380-corediv-clock
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- "#clock-cells"
- clocks
additionalProperties: false
examples:
- |
clock-controller@18740 {
compatible = "marvell,armada-370-corediv-clock";
reg = <0x18740 0xc>;
#clock-cells = <1>;
clocks = <&pll>;
};
Bindings/clock/marvell,armada-3700-periph-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,armada-3700-periph-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 37xx SoCs Peripheral Clocks
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell Armada 37xx SoCs provide peripheral clocks which are used as clock
source for the peripheral of the SoC.
There are two different blocks associated to north bridge and south bridge.
The following is a list of provided IDs for Armada 3700 North bridge clocks:
ID Clock name Description
-----------------------------------
0 mmc MMC controller
1 sata_host Sata Host
2 sec_at Security AT
3 sac_dap Security DAP
4 tsecm Security Engine
5 setm_tmx Serial Embedded Trace Module
6 avs Adaptive Voltage Scaling
7 sqf SPI
8 pwm PWM
9 i2c_2 I2C 2
10 i2c_1 I2C 1
11 ddr_phy DDR PHY
12 ddr_fclk DDR F clock
13 trace Trace
14 counter Counter
15 eip97 EIP 97
16 cpu CPU
The following is a list of provided IDs for Armada 3700 South bridge clocks:
ID Clock name Description
-----------------------------------
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
1 gbe-core parent clock for Gigabit Ethernet core
2 gbe-125 125 MHz parent clock for Gigabit Ethernet
3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
7 gbe1-core Gigabit Ethernet core port 1
8 gbe0-core Gigabit Ethernet core port 0
9 gbe-bm Gigabit Ethernet Buffer Manager
10 sdio SDIO
11 usb32-sub2-sys USB 2 clock
12 usb32-ss-sys USB 3 clock
13 pcie PCIe controller
properties:
compatible:
oneOf:
- const: marvell,armada-3700-periph-clock-sb
- items:
- const: marvell,armada-3700-periph-clock-nb
- const: syscon
reg:
maxItems: 1
clocks:
items:
- description: TBG-A P clock and specifier
- description: TBG-B P clock and specifier
- description: TBG-A S clock and specifier
- description: TBG-B S clock and specifier
- description: Xtal clock and specifier
'#clock-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@13000{
compatible = "marvell,armada-3700-periph-clock-sb";
reg = <0x13000 0x1000>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};
Bindings/clock/marvell,armada-3700-tbg-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,armada-3700-tbg-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 3700 Time Base Generator Clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell Armada 37xx SoCs provide Time Base Generator clocks which are used as
parent clocks for the peripheral clocks.
The TBG clock consumer should specify the desired clock by having the clock ID
in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 3700:
0 = TBG A P
1 = TBG B P
2 = TBG A S
3 = TBG B S
properties:
compatible:
const: marvell,armada-3700-tbg-clock
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x1000>;
clocks = <&xtalclk>;
#clock-cells = <1>;
};
Bindings/clock/marvell,armada-xp-cpu-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
---
$schema: http://devicetree.org/meta-schemas/core.yaml#
$id: http://devicetree.org/schemas/clock/marvell,armada-xp-cpu-clock.yaml#
title: Marvell EBU CPU Clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
enum:
- marvell,armada-xp-cpu-clock
- marvell,mv98dx3236-cpu-clock
reg:
items:
- description: Clock complex registers
- description: PMU DFS registers
'#clock-cells':
const: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
- clocks
additionalProperties: false
examples:
- |
clock-controller@d0018700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
reg = <0xd0018700 0xa0>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
};
Bindings/clock/marvell,berlin2-clk.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,berlin2-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Berlin Clock Controller
maintainers:
- Jisheng Zhang <jszhang@kernel.org>
description:
Clock related registers are spread among the chip control registers. Berlin
clock node should be a sub-node of the chip controller node. Marvell Berlin2
(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some minor
differences in features and register layout.
properties:
compatible:
enum:
- marvell,berlin2-clk
- marvell,berlin2q-clk
'#clock-cells':
const: 1
clocks:
maxItems: 1
clock-names:
items:
- enum:
- refclk
- video_ext0
required:
- compatible
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
clock-controller {
compatible = "marvell,berlin2q-clk";
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
Bindings/clock/marvell,dove-divider-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/marvell,dove-divider-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Dove PLL Divider Clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
high speed clocks for a number of peripherals. These dividers are part of the
PMU, and thus this node should be a child of the PMU node.
The following clocks are provided:
ID Clock
-------------
0 AXI bus clock
1 GPU clock
2 VMeta clock
3 LCD clock
properties:
compatible:
const: marvell,dove-divider-clock
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@64 {
compatible = "marvell,dove-divider-clock";
reg = <0x0064 0x8>;
#clock-cells = <1>;
};
Bindings/clock/marvell,mvebu-core-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,mvebu-core-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MVEBU SoC core clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell MVEBU SoCs usually allow to determine core clock frequencies by
reading the Sample-At-Reset (SAR) register. The core clock consumer should
specify the desired clock by having the clock ID in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 370/XP:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = nbclk (L2 Cache clock)
3 = hclk (DRAM control clock)
4 = dramclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 375:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 380/385:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 39x:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = nbclk (Coherent Fabric clock)
3 = hclk (SDRAM Controller Internal Clock)
4 = dclk (SDRAM Interface Clock)
5 = refclk (Reference Clock)
The following is a list of provided IDs and clock names on 98dx3236:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = ddrclk (DDR clock)
3 = mpll (MPLL Clock)
The following is a list of provided IDs and clock names on Kirkwood and Dove:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
2 = l2clk (L2 Cache clock derived from CPU0 clock)
3 = ddrclk (DDR controller clock derived from CPU0 clock)
The following is a list of provided IDs and clock names on Orion5x:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
2 = ddrclk (DDR controller clock derived from CPU0 clock)
properties:
compatible:
enum:
- marvell,armada-370-core-clock
- marvell,armada-375-core-clock
- marvell,armada-380-core-clock
- marvell,armada-390-core-clock
- marvell,armada-xp-core-clock
- marvell,dove-core-clock
- marvell,kirkwood-core-clock
- marvell,mv88f5181-core-clock
- marvell,mv88f5182-core-clock
- marvell,mv88f5281-core-clock
- marvell,mv88f6180-core-clock
- marvell,mv88f6183-core-clock
- marvell,mv98dx1135-core-clock
- marvell,mv98dx3236-core-clock
reg:
maxItems: 1
'#clock-cells':
const: 1
clock-output-names:
description: Overwrite default clock output names.
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
Bindings/clock/marvell-armada-370-gating-clock.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
---
$id: http://devicetree.org/schemas/clock/marvell-armada-370-gating-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell EBU SoC gating-clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some peripheral
clocks to be gated to save some power. The clock ID is directly mapped to the
corresponding clock gating control bit in HW to ease manual clock lookup in
datasheet.
The following is a list of provided IDs for Armada 370:
ID Clock Peripheral
-----------------------------------
0 Audio AC97 Cntrl
1 pex0_en PCIe 0 Clock out
2 pex1_en PCIe 1 Clock out
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
9 pex1 PCIe Cntrl 1
15 sata0 SATA Host 0
17 sdio SDHCI Host
23 crypto CESA (crypto engine)
25 tdm Time Division Mplx
28 ddr DDR Cntrl
30 sata1 SATA Host 0
The following is a list of provided IDs for Armada 375:
ID Clock Peripheral
-----------------------------------
2 mu Management Unit
3 pp Packet Processor
4 ptp PTP
5 pex0 PCIe 0 Clock out
6 pex1 PCIe 1 Clock out
8 audio Audio Cntrl
11 nd_clk Nand Flash Cntrl
14 sata0_link SATA 0 Link
15 sata0_core SATA 0 Core
16 usb3 USB3 Host
17 sdio SDHCI Host
18 usb USB Host
19 gop Gigabit Ethernet MAC
20 sata1_link SATA 1 Link
21 sata1_core SATA 1 Core
22 xor0 XOR DMA 0
23 xor1 XOR DMA 0
24 copro Coprocessor
25 tdm Time Division Mplx
28 crypto0_enc Cryptographic Unit Port 0 Encryption
29 crypto0_core Cryptographic Unit Port 0 Core
30 crypto1_enc Cryptographic Unit Port 1 Encryption
31 crypto1_core Cryptographic Unit Port 1 Core
The following is a list of provided IDs for Armada 380/385:
ID Clock Peripheral
-----------------------------------
0 audio Audio
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex1 PCIe 1
6 pex2 PCIe 2
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
11 usb3d USB3 Device
13 bm Buffer Management
14 crypto0z Cryptographic 0 Z
15 sata0 SATA 0
16 crypto1z Cryptographic 1 Z
17 sdio SDIO
18 usb2 USB 2
21 crypto1 Cryptographic 1
22 xor0 XOR 0
23 crypto0 Cryptographic 0
25 tdm Time Division Multiplexing
28 xor1 XOR 1
30 sata1 SATA 1
The following is a list of provided IDs for Armada 39x:
ID Clock Peripheral
-----------------------------------
5 pex1 PCIe 1
6 pex2 PCIe 2
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
15 sata0 SATA 0
17 sdio SDIO
22 xor0 XOR 0
28 xor1 XOR 1
The following is a list of provided IDs for Armada XP:
ID Clock Peripheral
-----------------------------------
0 audio Audio Cntrl
1 ge3 Gigabit Ethernet 3
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
6 pex1 PCIe Cntrl 1
7 pex2 PCIe Cntrl 2
8 pex3 PCIe Cntrl 3
13 bp
14 sata0lnk
15 sata0 SATA Host 0
16 lcd LCD Cntrl
17 sdio SDHCI Host
18 usb0 USB Host 0
19 usb1 USB Host 1
20 usb2 USB Host 2
22 xor0 XOR DMA 0
23 crypto CESA engine
25 tdm Time Division Mplx
28 xor1 XOR DMA 1
29 sata1lnk
30 sata1 SATA Host 1
The following is a list of provided IDs for 98dx3236:
ID Clock Peripheral
-----------------------------------
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
17 sdio SDHCI Host
18 usb0 USB Host 0
22 xor0 XOR DMA 0
The following is a list of provided IDs for Dove:
ID Clock Peripheral
-----------------------------------
0 usb0 USB Host 0
1 usb1 USB Host 1
2 ge Gigabit Ethernet
3 sata SATA Host
4 pex0 PCIe Cntrl 0
5 pex1 PCIe Cntrl 1
8 sdio0 SDHCI Host 0
9 sdio1 SDHCI Host 1
10 nand NAND Cntrl
11 camera Camera Cntrl
12 i2s0 I2S Cntrl 0
13 i2s1 I2S Cntrl 1
15 crypto CESA engine
21 ac97 AC97 Cntrl
22 pdma Peripheral DMA
23 xor0 XOR DMA 0
24 xor1 XOR DMA 1
30 gephy Gigabit Ethernet PHY
Note: gephy(30) is implemented as a parent clock of ge(2)
The following is a list of provided IDs for Kirkwood:
ID Clock Peripheral
-----------------------------------
0 ge0 Gigabit Ethernet 0
2 pex0 PCIe Cntrl 0
3 usb0 USB Host 0
4 sdio SDIO Cntrl
5 tsu Transp. Stream Unit
6 dunit SDRAM Cntrl
7 runit Runit
8 xor0 XOR DMA 0
9 audio I2S Cntrl 0
14 sata0 SATA Host 0
15 sata1 SATA Host 1
16 xor1 XOR DMA 1
17 crypto CESA engine
18 pex1 PCIe Cntrl 1
19 ge1 Gigabit Ethernet 1
20 tdm Time Division Mplx
properties:
compatible:
enum:
- marvell,armada-370-gating-clock
- marvell,armada-375-gating-clock
- marvell,armada-380-gating-clock
- marvell,armada-390-gating-clock
- marvell,armada-xp-gating-clock
- marvell,mv98dx3236-gating-clock
- marvell,dove-gating-clock
- marvell,kirkwood-gating-clock
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@d0038 {
compatible = "marvell,dove-gating-clock";
reg = <0xd0038 0x4>;
/* default parent clock is tclk */
clocks = <&core_clk 0>;
#clock-cells = <1>;
};
Bindings/clock/maxim,max9485.yaml
+82
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/maxim,max9485.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim MAX9485 Programmable Audio Clock Generator
maintainers:
- Daniel Mack <daniel@zonque.org>
description: >
Maxim MAX9485 Programmable Audio Clock Generator exposes 4 clocks in total:
- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
frequencies
- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
requests.
properties:
compatible:
const: maxim,max9485
reg:
maxItems: 1
clocks:
description: Input clock. Must provide 27 MHz
maxItems: 1
clock-names:
items:
- const: xclk
'#clock-cells':
const: 1
reset-gpios:
description: >
GPIO descriptor connected to the #RESET input pin
vdd-supply:
description: A regulator node for Vdd
clock-output-names:
description: Name of output clocks, as defined in common clock bindings
items:
- const: mclkout
- const: clkout
- const: clkout1
- const: clkout2
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
clock-controller@63 {
compatible = "maxim,max9485";
reg = <0x63>;
#clock-cells = <1>;
clock-names = "xclk";
clocks = <&xo_27mhz>;
reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
vdd-supply = <&reg_3v3>;
};
};
Bindings/clock/mediatek,mtmips-sysc.yaml
+16 -12
View File
@@ -26,18 +26,22 @@ description: |
properties:
compatible:
items:
- enum:
- ralink,mt7620-sysc
- ralink,mt7628-sysc
- ralink,mt7688-sysc
- ralink,rt2880-sysc
- ralink,rt3050-sysc
- ralink,rt3052-sysc
- ralink,rt3352-sysc
- ralink,rt3883-sysc
- ralink,rt5350-sysc
- const: syscon
oneOf:
- items:
- enum:
- ralink,mt7620-sysc
- ralink,mt7688-sysc
- ralink,rt2880-sysc
- ralink,rt3050-sysc
- ralink,rt3052-sysc
- ralink,rt3352-sysc
- ralink,rt3883-sysc
- ralink,rt5350-sysc
- const: syscon
- items:
- const: ralink,mt7628-sysc
- const: ralink,mt7688-sysc
- const: syscon
reg:
maxItems: 1
Bindings/clock/microchip,pic32mzda-clk.yaml
+45
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@@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,pic32mzda-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PIC32MZDA Clock Controller
maintainers:
- Purna Chandra Mandal <purna.mandal@microchip.com>
description:
Microchip clock controller consists of a few oscillators, PLL, multiplexer
and divider modules.
properties:
compatible:
const: microchip,pic32mzda-clk
reg:
maxItems: 1
'#clock-cells':
const: 1
microchip,pic32mzda-sosc:
description: Presence of secondary oscillator.
type: boolean
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
clock-controller@1f801200 {
compatible = "microchip,pic32mzda-clk";
reg = <0x1f801200 0x200>;
#clock-cells = <1>;
/* optional */
microchip,pic32mzda-sosc;
};
Bindings/clock/moxa,moxart-clock.yaml
+38
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@@ -0,0 +1,38 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/moxa,moxart-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MOXA ART Clock Controllers
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description:
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading
registers holding multiplier and divisor information.
properties:
compatible:
enum:
- moxa,moxart-apb-clock
- moxa,moxart-pll-clock
"#clock-cells":
const: 0
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names: true
additionalProperties: false
required:
- compatible
- "#clock-cells"
- reg
Bindings/clock/nuvoton,npcm750-clk.yaml
+66
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@@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nuvoton,npcm750-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton NPCM7XX Clock Controller
maintainers:
- Tali Perry <tali.perry1@gmail.com>
description: >
Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
generates and supplies clocks to all modules within the BMC.
External clocks:
There are six fixed clocks that are generated outside the BMC. All clocks are of
a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
clk_sysbypck are inputs to the clock controller.
clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
network. They are set on the device tree, but not used by the clock module. The
network devices use them directly.
All available clocks are defined as preprocessor macros in:
dt-bindings/clock/nuvoton,npcm7xx-clock.h
and can be reused as DT sources.
properties:
compatible:
const: nuvoton,npcm750-clk
reg:
maxItems: 1
'#clock-cells':
const: 1
clock-names:
items:
- const: refclk
- const: sysbypck
- const: mcbypck
clocks:
items:
- description: refclk
- description: sysbypck
- description: mcbypck
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@f0801000 {
compatible = "nuvoton,npcm750-clk";
#clock-cells = <1>;
reg = <0xf0801000 0x1000>;
clock-names = "refclk", "sysbypck", "mcbypck";
clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
};
Bindings/clock/nxp,imx95-blk-ctl.yaml
+2
View File
@@ -13,6 +13,8 @@ properties:
compatible:
items:
- enum:
- nxp,imx94-display-csr
- nxp,imx94-lvds-csr
- nxp,imx95-camera-csr
- nxp,imx95-display-csr
- nxp,imx95-hsio-blk-ctl
Bindings/clock/nxp,lpc1850-ccu.yaml
+104
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@@ -0,0 +1,104 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nxp,lpc1850-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC1850 Clock Control Unit (CCU)
description:
Each CGU base clock has several clock branches which can be turned on
or off independently by the Clock Control Units CCU1 or CCU2. The
branch clocks are distributed between CCU1 and CCU2.
Above text taken from NXP LPC1850 User Manual
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: nxp,lpc1850-ccu
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 1
maxItems: 8
clock-names:
minItems: 1
maxItems: 8
items:
enum:
- base_usb0_clk
- base_periph_clk
- base_usb1_clk
- base_cpu_clk
- base_spifi_clk
- base_spi_clk
- base_apb1_clk
- base_apb3_clk
- base_adchs_clk
- base_sdio_clk
- base_ssp0_clk
- base_ssp1_clk
- base_uart0_clk
- base_uart1_clk
- base_uart2_clk
- base_uart3_clk
- base_audio_clk
description:
Which branch clocks that are available on the CCU depends on the
specific LPC part. Check the user manual for your specific part.
A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/lpc18xx-cgu.h>
clock-controller@40051000 {
compatible = "nxp,lpc1850-ccu";
reg = <0x40051000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
clock-names = "base_apb3_clk", "base_apb1_clk",
"base_spifi_clk", "base_cpu_clk",
"base_periph_clk", "base_usb0_clk",
"base_usb1_clk", "base_spi_clk";
};
- |
#include <dt-bindings/clock/lpc18xx-cgu.h>
clock-controller@40052000 {
compatible = "nxp,lpc1850-ccu";
reg = <0x40052000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
clock-names = "base_audio_clk", "base_uart3_clk",
"base_uart2_clk", "base_uart1_clk",
"base_uart0_clk", "base_ssp1_clk",
"base_ssp0_clk", "base_sdio_clk";
};
Bindings/clock/nxp,lpc1850-cgu.yaml
+99
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@@ -0,0 +1,99 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nxp,lpc1850-cgu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC1850 Clock Generation Unit (CGU)
description: >
The CGU generates multiple independent clocks for the core and the
peripheral blocks of the LPC18xx. Each independent clock is called
a base clock and itself is one of the inputs to the two Clock
Control Units (CCUs) which control the branch clocks to the
individual peripherals.
The CGU selects the inputs to the clock generators from multiple
clock sources, controls the clock generation, and routes the outputs
of the clock generators through the clock source bus to the output
stages. Each output stage provides an independent clock source and
corresponds to one of the base clocks for the LPC18xx.
Above text taken from NXP LPC1850 User Manual.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: nxp,lpc1850-cgu
reg:
maxItems: 1
'#clock-cells':
const: 1
description: |
Which base clocks that are available on the CGU depends on the
specific LPC part. Base clocks are numbered from 0 to 27.
Number: Name: Description:
0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
1 BASE_USB0_CLK Base clock for USB0
2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
SPI, and SGPIO
3 BASE_USB1_CLK Base clock for USB1
4 BASE_CPU_CLK System base clock for ARM Cortex-M core
and APB peripheral blocks #0 and #2
5 BASE_SPIFI_CLK Base clock for SPIFI
6 BASE_SPI_CLK Base clock for SPI
7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
9 BASE_APB1_CLK Base clock for APB peripheral block # 1
10 BASE_APB3_CLK Base clock for APB peripheral block # 3
11 BASE_LCD_CLK Base clock for LCD
12 BASE_ADCHS_CLK Base clock for ADCHS
13 BASE_SDIO_CLK Base clock for SD/MMC
14 BASE_SSP0_CLK Base clock for SSP0
15 BASE_SSP1_CLK Base clock for SSP1
16 BASE_UART0_CLK Base clock for UART0
17 BASE_UART1_CLK Base clock for UART1
18 BASE_UART2_CLK Base clock for UART2
19 BASE_UART3_CLK Base clock for UART3
20 BASE_OUT_CLK Base clock for CLKOUT pin
24-21 - Reserved
25 BASE_AUDIO_CLK Base clock for audio system (I2S)
26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
BASE_ADCHS_CLK is only available on LPC4370.
clocks:
maxItems: 5
clock-indices:
minItems: 1
maxItems: 28
clock-output-names:
minItems: 1
maxItems: 28
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@40050000 {
compatible = "nxp,lpc1850-cgu";
reg = <0x40050000 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
};
Bindings/clock/qca,ath79-pll.yaml
+70
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@@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qca,ath79-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros ATH79 PLL controller
maintainers:
- Alban Bedel <albeu@free.fr>
- Antony Pavlov <antonynpavlov@gmail.com>
description: >
The PLL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
properties:
compatible:
oneOf:
- items:
- const: qca,ar9132-pll
- const: qca,ar9130-pll
- items:
- enum:
- qca,ar7100-pll
- qca,ar7240-pll
- qca,ar9130-pll
- qca,ar9330-pll
- qca,ar9340-pll
- qca,qca9530-pll
- qca,qca9550-pll
- qca,qca9560-pll
reg:
maxItems: 1
clock-names:
items:
- const: ref
clocks:
maxItems: 1
'#clock-cells':
const: 1
clock-output-names:
items:
- const: cpu
- const: ddr
- const: ahb
required:
- compatible
- reg
- clock-names
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@18050000 {
compatible = "qca,ar9132-pll", "qca,ar9130-pll";
reg = <0x18050000 0x20>;
clock-names = "ref";
clocks = <&extosc>;
#clock-cells = <1>;
clock-output-names = "cpu", "ddr", "ahb";
};
Bindings/clock/qcom,camcc-sm8250.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8250.
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
See also: include/dt-bindings/clock/qcom,camcc-sm8250.h
allOf:
- $ref: qcom,gcc.yaml#
Bindings/clock/qcom,dispcc-sm6125.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks and power domains
on SM6125.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
See also: include/dt-bindings/clock/qcom,dispcc-sm6125.h
properties:
compatible:
Bindings/clock/qcom,dispcc-sm6350.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM6350.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
See also: include/dt-bindings/clock/qcom,dispcc-sm6350.h
properties:
compatible:
Bindings/clock/qcom,gcc-ipq4019.yaml
+1 -1
View File
@@ -15,7 +15,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ4019.
See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h
See also: include/dt-bindings/clock/qcom,gcc-ipq4019.h
allOf:
- $ref: qcom,gcc.yaml#
Bindings/clock/qcom,gcc-ipq8074.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8074.
See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
See also: include/dt-bindings/clock/qcom,gcc-ipq8074.h
allOf:
- $ref: qcom,gcc.yaml#
Bindings/clock/qcom,gcc-msm8976.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8976.
See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h
See also: include/dt-bindings/clock/qcom,gcc-msm8976.h
properties:
compatible:
Bindings/clock/qcom,gcc-msm8994.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8994 and MSM8992.
See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h
See also: include/dt-bindings/clock/qcom,gcc-msm8994.h
properties:
compatible:
Bindings/clock/qcom,gcc-msm8996.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module which provides the clocks, resets and
power domains on MSM8996.
See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h
See also: include/dt-bindings/clock/qcom,gcc-msm8996.h
properties:
compatible:
Bindings/clock/qcom,gcc-msm8998.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8998.
See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h
See also: include/dt-bindings/clock/qcom,gcc-msm8998.h
properties:
compatible:
Bindings/clock/qcom,gcc-qcm2290.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on QCM2290.
See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h
See also: include/dt-bindings/clock/qcom,gcc-qcm2290.h
properties:
compatible:
Bindings/clock/qcom,gcc-qcs404.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on QCS404.
See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h
See also: include/dt-bindings/clock/qcom,gcc-qcs404.h
properties:
compatible:
Bindings/clock/qcom,gcc-sc7180.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SC7180.
See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h
See also: include/dt-bindings/clock/qcom,gcc-sc7180.h
properties:
compatible:
Bindings/clock/qcom,gcc-sc7280.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SC7280.
See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
See also: include/dt-bindings/clock/qcom,gcc-sc7280.h
properties:
compatible:
Bindings/clock/qcom,gcc-sc8180x.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SC8180x.
See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h
See also: include/dt-bindings/clock/qcom,gcc-sc8180x.h
properties:
compatible:
Bindings/clock/qcom,gcc-sc8280xp.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and
power domains on SC8280xp.
See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
See also: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
properties:
compatible:
Bindings/clock/qcom,gcc-sdm845.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDM670 and SDM845
See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
See also: include/dt-bindings/clock/qcom,gcc-sdm845.h
properties:
compatible:
Bindings/clock/qcom,gcc-sdx55.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and
power domains on SDX55
See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h
See also: include/dt-bindings/clock/qcom,gcc-sdx55.h
properties:
compatible:
Bindings/clock/qcom,gcc-sdx65.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDX65
See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
See also: include/dt-bindings/clock/qcom,gcc-sdx65.h
properties:
compatible:
Bindings/clock/qcom,gcc-sm6115.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM4250/6115.
See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h
See also: include/dt-bindings/clock/qcom,gcc-sm6115.h
properties:
compatible:
Bindings/clock/qcom,gcc-sm6125.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6125.
See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h
See also: include/dt-bindings/clock/qcom,gcc-sm6125.h
properties:
compatible:
Bindings/clock/qcom,gcc-sm6350.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6350.
See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h
See also: include/dt-bindings/clock/qcom,gcc-sm6350.h
properties:
compatible:
Bindings/clock/qcom,gcc-sm8150.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8150.
See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h
See also: include/dt-bindings/clock/qcom,gcc-sm8150.h
properties:
compatible:
Bindings/clock/qcom,gcc-sm8250.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8250.
See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h
See also: include/dt-bindings/clock/qcom,gcc-sm8250.h
properties:
compatible:
Bindings/clock/qcom,gcc-sm8350.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8350.
See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
See also: include/dt-bindings/clock/qcom,gcc-sm8350.h
properties:
compatible:
Bindings/clock/qcom,gcc-sm8450.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8450
See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
See also: include/dt-bindings/clock/qcom,gcc-sm8450.h
properties:
compatible:
Bindings/clock/qcom,ipq9574-cmn-pll.yaml
+2
View File
@@ -24,6 +24,8 @@ description:
properties:
compatible:
enum:
- qcom,ipq5018-cmn-pll
- qcom,ipq5424-cmn-pll
- qcom,ipq9574-cmn-pll
reg:
Bindings/clock/qcom,krait-cc.yaml
+43
View File
@@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Krait Clock Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
properties:
compatible:
enum:
- qcom,krait-cc-v1
- qcom,krait-cc-v2
'#clock-cells':
const: 1
clocks:
items:
- description: Parent clock phandle for hfpll0
- description: Parent clock phandle for hfpll1
- description: Parent clock phandle for acpu0_aux
- description: Parent clock phandle for acpu1_aux
- description: Parent clock phandle for qsb
clock-names:
items:
- const: hfpll0
- const: hfpll1
- const: acpu0_aux
- const: acpu1_aux
- const: qsb
required:
- compatible
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
Bindings/clock/qcom,milos-camcc.yaml
+51
View File
@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-camcc.h
properties:
compatible:
const: qcom,milos-camcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: Camera AHB clock from GCC
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
clock-controller@adb0000 {
compatible = "qcom,milos-camcc";
reg = <0x0adb0000 0x40000>;
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,milos-dispcc.yaml
+63
View File
@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-dispcc.h
properties:
compatible:
const: qcom,milos-dispcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: Display's AHB clock
- description: GPLL0 source from GCC
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
clock-controller@af00000 {
compatible = "qcom,milos-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,milos-gcc.yaml
+62
View File
@@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-gcc.h
properties:
compatible:
const: qcom,milos-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,milos-gcc";
reg = <0x00100000 0x1f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,milos-videocc.yaml
+53
View File
@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-videocc.h
properties:
compatible:
const: qcom,milos-videocc
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- description: Video AHB clock from GCC
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
clock-controller@aaf0000 {
compatible = "qcom,milos-videocc";
reg = <0x0aaf0000 0x10000>;
clocks = <&bi_tcxo_div2>,
<&bi_tcxo_ao_div2>,
<&sleep_clk>,
<&gcc GCC_VIDEO_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,mmcc.yaml
+3 -21
View File
@@ -38,36 +38,16 @@ properties:
minItems: 7
maxItems: 13
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding
vdd-gfx-supply:
description:
Regulator supply for the GPU_GX GDSC
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
@@ -351,6 +331,8 @@ allOf:
- const: dp_link_2x_clk_divsel_five
- const: dp_vco_divided_clk_src_mux
unevaluatedProperties: false
examples:
# Example for MMCC for MSM8960:
- |
Bindings/clock/qcom,msm8998-gpucc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on MSM8998.
See also:: include/dt-bindings/clock/qcom,gpucc-msm8998.h
See also: include/dt-bindings/clock/qcom,gpucc-msm8998.h
properties:
compatible:
Bindings/clock/qcom,qcm2290-dispcc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on qcm2290.
See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
See also: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
properties:
compatible:
Bindings/clock/qcom,qcs615-dispcc.yaml
+55
View File
@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on QCS615
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on QCS615.
See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h
properties:
compatible:
const: qcom,qcs615-dispcc
clocks:
items:
- description: Board XO source
- description: GPLL0 clock source from GCC
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Pixel clock from DSI PHY1
- description: Display port PLL link clock
- description: Display port PLL VCO DIV clock
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
clock-controller@af00000 {
compatible = "qcom,qcs615-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dp_phy 0>,
<&mdss_dp_vco 0>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,qcs615-gpucc.yaml
+49
View File
@@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on QCS615
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm graphics clock control module provides clocks, resets and power
domains on QCS615 Qualcomm SoCs.
See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h
properties:
compatible:
const: qcom,qcs615-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 GPUCC div branch source
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0x5090000 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GPLL0>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,qcs615-videocc.yaml
+47
View File
@@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on QCS615
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm video clock control module provides clocks, resets and power
domains on QCS615 Qualcomm SoCs.
See also: include/dt-bindings/clock/qcom,qcs615-videocc.h
properties:
compatible:
const: qcom,qcs615-videocc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
clock-controller@ab00000 {
compatible = "qcom,qcs615-videocc";
reg = <0xab00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,qdu1000-ecpricc.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
module which supports the clocks, resets on QDU1000 and QRU1000
See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
See also: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
properties:
compatible:
Bindings/clock/qcom,qdu1000-gcc.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on QDU1000 and QRU1000
See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h
See also: include/dt-bindings/clock/qcom,qdu1000-gcc.h
properties:
compatible:
Bindings/clock/qcom,rpmhcc.yaml
+1
View File
@@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- qcom,milos-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
Bindings/clock/qcom,sa8775p-camcc.yaml
+15
View File
@@ -17,12 +17,14 @@ description: |
See also:
include/dt-bindings/clock/qcom,qcs8300-camcc.h
include/dt-bindings/clock/qcom,sa8775p-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
properties:
compatible:
enum:
- qcom,qcs8300-camcc
- qcom,sa8775p-camcc
- qcom,sc8280xp-camcc
clocks:
items:
@@ -35,6 +37,11 @@ properties:
maxItems: 1
description: MMCX power domain
required-opps:
description:
OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- clocks
@@ -43,6 +50,14 @@ required:
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
contains:
const: qcom,sc8280xp-camcc
then:
required:
- required-opps
unevaluatedProperties: false
Bindings/clock/qcom,sa8775p-gcc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and
power domains on sa8775p.
See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h
See also: include/dt-bindings/clock/qcom,sa8775p-gcc.h
properties:
compatible:
Bindings/clock/qcom,sc7180-camcc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SC7180.
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
See also: include/dt-bindings/clock/qcom,camcc-sc7180.h
allOf:
- $ref: qcom,gcc.yaml#
Bindings/clock/qcom,sc7180-dispcc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SC7180.
See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h
See also: include/dt-bindings/clock/qcom,dispcc-sc7180.h
properties:
compatible:
Bindings/clock/qcom,sc7180-lpasscorecc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm LPASS core clock control module provides the clocks and power
domains on SC7180.
See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
See also: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
properties:
compatible:
Bindings/clock/qcom,sc7280-camcc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SC7280.
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
See also: include/dt-bindings/clock/qcom,camcc-sc7280.h
allOf:
- $ref: qcom,gcc.yaml#
Bindings/clock/qcom,sc7280-dispcc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SC7280.
See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
See also: include/dt-bindings/clock/qcom,dispcc-sc7280.h
properties:
compatible:
Bindings/clock/qcom,sc7280-lpasscc.yaml
+1 -1
View File
@@ -13,7 +13,7 @@ description: |
Qualcomm LPASS core clock control module provides the clocks and power
domains on SC7280.
See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h
See also: include/dt-bindings/clock/qcom,lpass-sc7280.h
properties:
compatible:
Bindings/clock/qcom,sc8180x-camcc.yaml
+67
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc8180x-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SC8180X
maintainers:
- Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SC8180X.
See also: include/dt-bindings/clock/qcom,sc8180x-camcc.h
properties:
compatible:
const: qcom,sc8180x-camcc
clocks:
items:
- description: Camera AHB clock from GCC
- description: Board XO source
- description: Sleep clock source
power-domains:
maxItems: 1
description:
A phandle and PM domain specifier for the MMCX power domain.
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
required:
- compatible
- clocks
- power-domains
- required-opps
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@ad00000 {
compatible = "qcom,sc8180x-camcc";
reg = <0x0ad00000 0x20000>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
power-domains = <&rpmhpd SC8180X_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,sdm845-camcc.yaml
+1 -1
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@@ -13,7 +13,7 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SDM845.
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
See also: include/dt-bindings/clock/qcom,camcc-sm845.h
allOf:
- $ref: qcom,gcc.yaml#

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