Revert odd change, setting limit registers before base.

I don't know what errata is mentioned there, I was unable to find it, but
setting limit before the base simply does not work at all.  According to
specification attempt to set limit out of the present window range resets
it to zero, effectively disabling it.  And that is what I see in practice.

Fixing this properly disables access for remote side to our memory until
respective xlat is negotiated and set.  As I see, Linux does the same.

sys/dev/ntb/ntb_hw/ntb_hw.c

@@ -1699,26 +1699,22 @@ xeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr,
 			bar_addr = 0;
 	}
 
-	/*
-	 * Set limit registers first to avoid an errata where setting the base
-	 * registers locks the limit registers.
-	 */
 	if (!bar_is_64bit(ntb, idx)) {
-		ntb_reg_write(4, lmt_reg, bar_addr);
-		reg_val = ntb_reg_read(4, lmt_reg);
-		(void)reg_val;
-
 		ntb_reg_write(4, base_reg, bar_addr);
 		reg_val = ntb_reg_read(4, base_reg);
 		(void)reg_val;
-	} else {
-		ntb_reg_write(8, lmt_reg, bar_addr);
-		reg_val = ntb_reg_read(8, lmt_reg);
-		(void)reg_val;
 
+		ntb_reg_write(4, lmt_reg, bar_addr);
+		reg_val = ntb_reg_read(4, lmt_reg);
+		(void)reg_val;
+	} else {
 		ntb_reg_write(8, base_reg, bar_addr);
 		reg_val = ntb_reg_read(8, base_reg);
 		(void)reg_val;
+
+		ntb_reg_write(8, lmt_reg, bar_addr);
+		reg_val = ntb_reg_read(8, lmt_reg);
+		(void)reg_val;
 	}
 }