cxgbetool(8): Updates for T7
* Registers dump * SGE context * TCB info MFC after: 3 days Sponsored by: Chelsio Communications
This commit is contained in:
Navdeep Parhar
@@ -6,6 +6,7 @@ SRCS+= tcb_common.c
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SRCS+= tcbinfot4.c tcbshowt4.c
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SRCS+= tcbinfot5.c tcbshowt5.c
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SRCS+= tcbinfot6.c tcbshowt6.c
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SRCS+= tcbinfot7.c tcbshowt7.c
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CFLAGS+= -I${SRCTOP}/sys/dev/cxgbe -I${SRCTOP}/sys -I.
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LIBADD= pcap
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WARNS?= 2
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@@ -1,6 +1,5 @@
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/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* All rights reserved.
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* Copyright (c) 2011, 2025 Chelsio Communications.
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* Written by: Navdeep Parhar <np@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -92,6 +91,7 @@ struct field_desc {
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#include "reg_defs_t4.c"
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#include "reg_defs_t5.c"
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#include "reg_defs_t6.c"
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#include "reg_defs_t7.c"
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#include "reg_defs_t4vf.c"
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static void
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@@ -436,6 +436,48 @@ dump_regs_t6(int argc, const char *argv[], const uint32_t *regs)
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}
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#undef T6_MODREGS
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#define T7_MODREGS(name) { #name, t7_##name##_regs }
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static int
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dump_regs_t7(int argc, const char *argv[], const uint32_t *regs)
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{
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static struct mod_regs t7_mod[] = {
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T7_MODREGS(sge),
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{ "pci", t7_pcie_regs },
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T7_MODREGS(dbg),
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{ "mc0", t7_mc_t70_regs },
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T7_MODREGS(ma),
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{ "edc0", t7_edc_t60_regs },
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{ "edc1", t7_edc_t61_regs },
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T7_MODREGS(cim),
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T7_MODREGS(tp),
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{ "ulprx", t7_ulp_rx_regs },
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{ "ulptx", t7_ulp_tx_regs },
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{ "pmrx", t7_pm_rx_regs },
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{ "pmtx", t7_pm_tx_regs },
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T7_MODREGS(mps),
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{ "cplsw", t7_cpl_switch_regs },
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T7_MODREGS(smb),
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{ "i2c", t7_i2cm_regs },
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T7_MODREGS(mi),
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T7_MODREGS(uart),
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T7_MODREGS(pmu),
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T7_MODREGS(sf),
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T7_MODREGS(pl),
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T7_MODREGS(le),
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T7_MODREGS(ncsi),
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{ "mac", t7_mac_t7_regs },
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{ "hma", t7_hma_t6_regs },
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{ "crypto0", t7_crypto_0_regs },
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{ "crypto1", t7_crypto_1_regs },
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{ "cryptokey", t7_crypto_key_regs },
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T7_MODREGS(arm),
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T7_MODREGS(gcache),
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};
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return dump_regs_table(argc, argv, regs, t7_mod, nitems(t7_mod));
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}
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#undef T7_MODREGS
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static int
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dump_regs_t4vf(int argc, const char *argv[], const uint32_t *regs)
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{
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@@ -478,6 +520,20 @@ dump_regs_t6vf(int argc, const char *argv[], const uint32_t *regs)
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return dump_regs_table(argc, argv, regs, t6vf_mod, nitems(t6vf_mod));
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}
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static int
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dump_regs_t7vf(int argc, const char *argv[], const uint32_t *regs)
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{
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static struct mod_regs t7vf_mod[] = {
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{ "sge", t5vf_sge_regs },
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{ "mps", t4vf_mps_regs },
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{ "pl", t7vf_pl_regs },
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{ "mbdata", t4vf_mbdata_regs },
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{ "cim", t4vf_cim_regs },
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};
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return dump_regs_table(argc, argv, regs, t7vf_mod, nitems(t7vf_mod));
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}
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static int
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dump_regs(int argc, const char *argv[])
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{
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@@ -515,6 +571,11 @@ dump_regs(int argc, const char *argv[])
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rc = dump_regs_t6vf(argc, argv, regs.data);
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else
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rc = dump_regs_t6(argc, argv, regs.data);
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} else if (vers == 7) {
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if (revision == 0x3f)
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rc = dump_regs_t7vf(argc, argv, regs.data);
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else
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rc = dump_regs_t7(argc, argv, regs.data);
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} else {
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warnx("%s (type %d, rev %d) is not a known card.",
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g.nexus, vers, revision);
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@@ -1492,7 +1553,180 @@ show_struct(const uint32_t *words, int nwords, const struct field_desc *fd)
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#define FIELD1(name, start) FIELD(name, start, start)
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static void
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show_t5t6_ctxt(const struct t4_sge_context *p, int vers)
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show_t7_ctxt(const struct t4_sge_ctxt *p)
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{
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static struct field_desc egress_t7[] = {
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FIELD("uPToken_4k:", 197, 198),
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FIELD("WrLength_5:", 196, 196),
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FIELD("CpuId:", 193, 195),
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FIELD("PCIeDataChannel_1:", 192, 192),
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FIELD("DCA_ST:", 181, 191),
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FIELD("StatusPgNS:", 180, 180),
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FIELD("StatusPgRO:", 179, 179),
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FIELD("FetchNS:", 178, 178),
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FIELD("FetchRO:", 177, 177),
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FIELD("Valid:", 176, 176),
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FIELD("ReschedulePending_1:", 175, 175),
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FIELD("PCIeDataChannel:", 174, 174),
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FIELD("StatusPgTPHintEn:", 173, 173),
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FIELD("StatusPgTPHint:", 171, 172),
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FIELD("FetchTPHintEn:", 170, 170),
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FIELD("FetchTPHint:", 168, 169),
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FIELD("FCThreshOverride:", 167, 167),
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{ "WRLength:", 162, 166, 9, 0, 1 },
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FIELD("WRLengthKnown:", 161, 161),
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FIELD("ReschedulePending:", 160, 160),
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FIELD("TimerIx:", 157, 159),
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FIELD("FetchBurstMin:", 156, 156),
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FIELD("FLMPacking:", 155, 155),
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FIELD("FetchBurstMax:", 153, 154),
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FIELD("uPToken:", 133, 152),
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FIELD("uPTokenEn:", 132, 132),
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FIELD("UserModeIO:", 131, 131),
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FIELD("uPFLCredits:", 123, 130),
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FIELD("uPFLCreditEn:", 122, 122),
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FIELD("FID:", 111, 121),
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FIELD("HostFCMode:", 109, 110),
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FIELD("HostFCOwner:", 108, 108),
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{ "CIDXFlushThresh:", 105, 107, 0, 0, 1 },
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FIELD("CIDX:", 89, 104),
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FIELD("PIDX:", 73, 88),
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{ "BaseAddress:", 18, 72, 9, 1 },
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FIELD("QueueSize:", 2, 17),
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FIELD("QueueType:", 1, 1),
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FIELD("FetchSizeMode:", 0, 0),
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{ NULL }
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};
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static struct field_desc fl_t7[] = {
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FIELD("FLMcontextID_4k:", 197, 198),
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FIELD("CpuId:", 193, 195),
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FIELD("PCIeDataChannel_1:", 192, 192),
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FIELD("DCA_ST:", 181, 191),
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FIELD("StatusPgNS:", 180, 180),
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FIELD("StatusPgRO:", 179, 179),
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FIELD("FetchNS:", 178, 178),
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FIELD("FetchRO:", 177, 177),
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FIELD("Valid:", 176, 176),
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FIELD("PCIeDataChannel:", 174, 175),
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FIELD("StatusPgTPHintEn:", 173, 173),
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FIELD("StatusPgTPHint:", 171, 172),
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FIELD("FetchTPHintEn:", 170, 170),
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FIELD("FetchTPHint:", 168, 169),
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FIELD("FCThreshOverride:", 167, 167),
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FIELD("ReschedulePending:", 160, 160),
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FIELD("OnChipQueue:", 159, 159),
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FIELD("FetchSizeMode:", 158, 158),
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{ "FetchBurstMin:", 156, 157, 4, 0, 1 },
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FIELD("FLMPacking:", 155, 155),
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FIELD("FetchBurstMax:", 153, 154),
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FIELD("FLMcongMode:", 152, 152),
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FIELD("MaxuPFLCredits:", 144, 151),
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FIELD("FLMcontextID:", 133, 143),
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FIELD("uPTokenEn:", 132, 132),
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FIELD("UserModeIO:", 131, 131),
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FIELD("uPFLCredits:", 123, 130),
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FIELD("uPFLCreditEn:", 122, 122),
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FIELD("FID:", 111, 121),
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FIELD("HostFCMode:", 109, 110),
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FIELD("HostFCOwner:", 108, 108),
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{ "CIDXFlushThresh:", 105, 107, 0, 0, 1 },
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FIELD("CIDX:", 89, 104),
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FIELD("PIDX:", 73, 88),
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{ "BaseAddress:", 18, 72, 9, 1 },
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FIELD("QueueSize:", 2, 17),
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FIELD("QueueType:", 1, 1),
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FIELD("CachePriority:", 0, 0),
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{ NULL }
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};
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static struct field_desc ingress_t7[] = {
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FIELD("Fid:", 171, 182),
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FIELD("InterruptIDX4K:", 170, 170),
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FIELD("CoalEn:", 169, 169),
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FIELD("CoalAbort:", 168, 168),
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FIELD("CoalCntr:", 161, 167),
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FIELD("CoalCompTimerStatus:", 160, 160),
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FIELD("CoalCompCntrStatus:", 159, 159),
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FIELD("SP_NS:", 158, 158),
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FIELD("SP_RO:", 157, 157),
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FIELD("SP_TPHintEn:", 156, 156),
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FIELD("SP_TPHint:", 154, 155),
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FIELD("DCA_ST:", 143, 153),
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FIELD("ISCSICoalescing:", 142, 142),
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FIELD("Queue_Valid:", 141, 141),
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FIELD("TimerPending:", 140, 140),
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FIELD("DropRSS:", 139, 139),
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FIELD("PCIeChannel:", 137, 138),
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FIELD("SEInterruptArmed:", 136, 136),
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FIELD("CongestionMgtEnable:", 135, 135),
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FIELD("NoSnoop:", 134, 134),
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FIELD("RelaxedOrdering:", 133, 133),
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FIELD("GTSmode:", 132, 132),
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FIELD("TPHintEn:", 131, 131),
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FIELD("TPHint:", 129, 130),
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FIELD("UpdateScheduling:", 128, 128),
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FIELD("UpdateDelivery:", 126, 127),
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FIELD("InterruptSent:", 125, 125),
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FIELD("InterruptIDX:", 114, 124),
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FIELD("InterruptDestination:", 113, 113),
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FIELD("InterruptArmed:", 112, 112),
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FIELD("RxIntCounter:", 106, 111),
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FIELD("RxIntCounterThreshold:", 104, 105),
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FIELD("Generation:", 103, 103),
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{ "BaseAddress:", 48, 102, 9, 1 },
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FIELD("PIDX:", 32, 47),
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FIELD("CIDX:", 16, 31),
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{ "QueueSize:", 4, 15, 4, 0 },
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{ "QueueEntrySize:", 2, 3, 4, 0, 1 },
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FIELD("QueueEntryOverride:", 1, 1),
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FIELD("CachePriority:", 0, 0),
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{ NULL }
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};
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static struct field_desc flm_t7[] = {
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FIELD("MidCongEn:", 154, 154),
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FIELD("FlPtr:", 90, 153),
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FIELD("Valid:", 89, 89),
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FIELD("SplitLenMode:", 87, 88),
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FIELD("TPHintEn:", 86, 86),
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FIELD("TPHint:", 84, 85),
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FIELD("NoSnoop:", 83, 83),
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FIELD("RelaxedOrdering:", 82, 82),
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FIELD("DCA_ST:", 71, 81),
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FIELD("EQid:", 54, 70),
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FIELD("SplitEn:", 52, 53),
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FIELD("PadEn:", 51, 51),
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FIELD("PackEn:", 50, 50),
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FIELD("Cache_Lock :", 49, 49),
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FIELD("CongDrop:", 48, 48),
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FIELD("Inflifght:", 47, 47),
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FIELD("CongEn:", 46, 46),
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FIELD("CongMode:", 45, 45),
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FIELD("PackOffset:", 20, 39),
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FIELD("CIDX:", 8, 15),
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FIELD("PIDX:", 0, 7),
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{ NULL }
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};
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static struct field_desc conm_t7[] = {
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FIELD("CngMPSEnable:", 37, 37),
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FIELD("CngTPMode:", 35, 36),
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FIELD("CngDBPHdr:", 34, 34),
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FIELD("CngDBPData:", 33, 33),
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FIELD("CngIMSG:", 32, 32),
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{ "CngChMap:", 0, 31, 0, 1, 0 },
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{ NULL }
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};
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if (p->mem_id == SGE_CONTEXT_EGRESS)
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show_struct(p->data, 7, (p->data[0] & 2) ? fl_t7 : egress_t7);
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else if (p->mem_id == SGE_CONTEXT_FLM)
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show_struct(p->data, 5, flm_t7);
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else if (p->mem_id == SGE_CONTEXT_INGRESS)
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show_struct(p->data, 6, ingress_t7);
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else if (p->mem_id == SGE_CONTEXT_CNM)
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show_struct(p->data, 2, conm_t7);
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}
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static void
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show_t5t6_ctxt(const struct t4_sge_ctxt *p, int vers)
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{
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static struct field_desc egress_t5[] = {
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FIELD("DCA_ST:", 181, 191),
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@@ -1743,7 +1977,7 @@ show_t5t6_ctxt(const struct t4_sge_context *p, int vers)
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}
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static void
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show_t4_ctxt(const struct t4_sge_context *p)
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show_t4_ctxt(const struct t4_sge_ctxt *p)
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{
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static struct field_desc egress_t4[] = {
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FIELD1("StatusPgNS:", 180),
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@@ -1887,7 +2121,7 @@ get_sge_context(int argc, const char *argv[])
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int rc;
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char *p;
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long cid;
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struct t4_sge_context cntxt = {0};
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struct t4_sge_ctxt cntxt = {0};
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if (argc != 2) {
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warnx("sge_context: incorrect number of arguments.");
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@@ -1915,14 +2149,21 @@ get_sge_context(int argc, const char *argv[])
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}
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cntxt.cid = cid;
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rc = doit(CHELSIO_T4_GET_SGE_CONTEXT, &cntxt);
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rc = doit(CHELSIO_T4_GET_SGE_CTXT, &cntxt);
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if (rc != 0)
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return (rc);
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if (g.chip_id == 4)
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switch (g.chip_id) {
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case 4:
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show_t4_ctxt(&cntxt);
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else
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break;
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case 5:
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case 6:
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show_t5t6_ctxt(&cntxt, g.chip_id);
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break;
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default:
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show_t7_ctxt(&cntxt);
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}
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return (0);
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}
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@@ -122,6 +122,21 @@ struct reg_info t6vf_pl_regs[] = {
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{ NULL, 0, 0 }
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};
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struct reg_info t7vf_pl_regs[] = {
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{ "PL_WHOAMI", 0x200, 0 },
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{ "PortxMap", 24, 3 },
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{ "SourceBus", 16, 2 },
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{ "SourcePF", 9, 3 },
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{ "IsVF", 8, 1 },
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{ "VFID", 0, 8 },
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{ "PL_VF_REV", 0x204, 0 },
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{ "ChipID", 4, 4 },
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{ "Rev", 0, 4 },
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{ "PL_VF_REVISION", 0x208, 0 },
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{ NULL, 0, 0 }
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};
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struct reg_info t4vf_cim_regs[] = {
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/*
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* Note: the Mailbox Control register has read side-effects so
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File diff suppressed because it is too large
Load Diff
@@ -59,6 +59,15 @@ extern void t6_display_tcb_aux_2(_TCBVAR *tvp,int aux);
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extern void t6_display_tcb_aux_3(_TCBVAR *tvp,int aux);
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extern void t6_display_tcb_aux_4(_TCBVAR *tvp,int aux);
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extern _TCBVAR g_tcb_info7[];
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extern _TCBVAR g_scb_info7[];
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extern _TCBVAR g_fcb_info7[];
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extern void t7_display_tcb_aux_0(_TCBVAR *tvp,int aux);
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extern void t7_display_tcb_aux_1(_TCBVAR *tvp,int aux);
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extern void t7_display_tcb_aux_2(_TCBVAR *tvp,int aux);
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extern void t7_display_tcb_aux_3(_TCBVAR *tvp,int aux);
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extern void t7_display_tcb_aux_4(_TCBVAR *tvp,int aux);
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/***:-----------------------------------------------------------------------
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***: globals
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***:-----------------------------------------------------------------------
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@@ -437,7 +446,13 @@ display_tcb_compressed(_TCBVAR *tvp,int aux)
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if (1==aux) t6_display_tcb_aux_1(tvp,aux);
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else if (2==aux) t6_display_tcb_aux_2(tvp,aux);
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else if (3==aux) t6_display_tcb_aux_3(tvp,aux);
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else if (4==aux) t6_display_tcb_aux_4(tvp,aux);
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else if (4==aux) t6_display_tcb_aux_4(tvp,aux);
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} else if (g_tN==7) {
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t7_display_tcb_aux_0(tvp,aux);
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if (1==aux) t7_display_tcb_aux_1(tvp,aux);
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else if (2==aux) t7_display_tcb_aux_2(tvp,aux);
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else if (3==aux) t7_display_tcb_aux_3(tvp,aux);
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else if (4==aux) t7_display_tcb_aux_4(tvp,aux);
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}
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}
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@@ -692,6 +707,11 @@ set_tcb_info(unsigned int tidtype, unsigned int cardtype)
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g_scb_info = g_scb_info6;
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g_fcb_info = g_fcb_info6;
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}
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else if (7 == g_tN) {
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g_tcb_info = g_tcb_info7;
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g_scb_info = g_scb_info7;
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g_fcb_info = g_fcb_info7;
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}
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}
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void
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,412 @@
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/* Auto-generated file. Avoid direct editing. */
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||||
/* Edits will be lost when file regenerated. */
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||||
/* See tcb_common.c for auto-generation commands. */
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#include <stdio.h>
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#include "tcb_common.h"
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||||
|
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void t7_display_tcb_aux_0 (_TCBVAR *tvp, int aux)
|
||||
{
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PR("STATE:\n");
|
||||
PR(" %-12s (%-2u), %s, lock_tid %u, rss_fw %u\n",
|
||||
spr_tcp_state(val("t_state")),
|
||||
val("t_state"),
|
||||
spr_ip_version(val("ip_version")),
|
||||
val("lock_tid"),
|
||||
val("rss_fw")
|
||||
);
|
||||
PR(" l2t_ix 0x%x, smac sel 0x%x, tos 0x%x\n",
|
||||
val("l2t_ix"),
|
||||
val("smac_sel"),
|
||||
val("tos")
|
||||
);
|
||||
PR(" maxseg %u, recv_scaleflag %u, recv_tstmp %u, recv_sack %u\n",
|
||||
val("t_maxseg"), val("recv_scale"),
|
||||
val("recv_tstmp"), val("recv_sack"));
|
||||
|
||||
|
||||
PR("TIMERS:\n"); /* **************************************** */
|
||||
PR(" timer %u, dack_timer %u\n",
|
||||
val("timer"), val("dack_timer"));
|
||||
PR(" mod_schd: tx: %u, rx: %u, reason 0x%1x\n",
|
||||
val("mod_schd_tx"),
|
||||
val("mod_schd_rx"),
|
||||
((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) |
|
||||
val("mod_schd_reason0"))
|
||||
);
|
||||
|
||||
|
||||
PR(" max_rt %-2u, rxtshift %u, keepalive %u\n",
|
||||
val("max_rt"), val("t_rxtshift"),
|
||||
val("keepalive"));
|
||||
PR(" timestamp_offset 0x%x, timestamp 0x%x\n",
|
||||
val("timestamp_offset"),val("timestamp"));
|
||||
|
||||
|
||||
PR(" t_rtt_ts_recent_age %u t_rttseq_recent %u\n",
|
||||
val("t_rtt_ts_recent_age"), val("t_rtseq_recent"));
|
||||
PR(" t_srtt %u, t_rttvar %u\n",
|
||||
val("t_srtt"),val("t_rttvar"));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PR("TRANSMIT BUFFER:\n"); /* *************************** */
|
||||
PR(" snd_una %u, snd_nxt %u, snd_max %u, tx_max %u\n",
|
||||
val("snd_una"),val("snd_nxt"),
|
||||
val("snd_max"),val("tx_max"));
|
||||
PR(" core_fin %u, tx_hdr_offset %u\n",
|
||||
val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una"))
|
||||
);
|
||||
if (val("recv_scale") && !val("active_open")) {
|
||||
PR(" rcv_adv %-5u << %-2u == %u (recv_scaleflag %u rcv_scale %u active open %u)\n",
|
||||
val("rcv_adv"), val("rcv_scale"),
|
||||
val("rcv_adv") << val("rcv_scale"),
|
||||
val("recv_scale"), val("rcv_scale"), val("active_open"));
|
||||
} else {
|
||||
PR(" rcv_adv %-5u (rcv_scale %-2u recv_scaleflag %u active_open %u)\n",
|
||||
val("rcv_adv"), val("rcv_scale"),
|
||||
val("recv_scale"), val("active_open"));
|
||||
}
|
||||
|
||||
PR(" snd_cwnd %-5u snd_ssthresh %u snd_rec %u\n",
|
||||
val("snd_cwnd") , val("snd_ssthresh"), val("snd_rec")
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
PR(" cctrl: sel %s, ecn %u, ece %u, cwr %u, rfr %u\n",
|
||||
spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")),
|
||||
val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"),
|
||||
val("cctrl_rfr"));
|
||||
PR(" t_dupacks %u, dupack_count_odd %u, fast_recovery %u\n",
|
||||
val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery"));
|
||||
PR(" core_more %u, core_urg, %u core_push %u,",
|
||||
val("core_more"),val("core_urg"),val("core_push"));
|
||||
PR(" core_flush %u\n",val("core_flush"));
|
||||
PR(" nagle %u, ssws_disable %u, turbo %u,",
|
||||
val("nagle"), val("ssws_disabled"), val("turbo"));
|
||||
PR(" tx_pdu_out %u\n",val("tx_pdu_out"));
|
||||
PR(" tx_pace_auto %u, tx_pace_fixed %u, tx_queue %u",
|
||||
val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue"));
|
||||
|
||||
|
||||
PR(" tx_quiesce %u\n",val("tx_quiesce"));
|
||||
PR(" channel %u, channel_msb %u\n",
|
||||
val("channel"),
|
||||
val("channel_msb")
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
PR(" tx_hdr_ptr 0x%-6x tx_last_ptr 0x%-6x tx_compact %u\n",
|
||||
val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact"));
|
||||
|
||||
|
||||
|
||||
|
||||
PR("RECEIVE BUFFER:\n"); /* *************************** */
|
||||
PR(" last_ack_sent %-10u rx_compact %u\n",
|
||||
val("ts_last_ack_sent"),val("rx_compact"));
|
||||
PR(" rcv_nxt %-10u hdr_off %-10u\n",
|
||||
val("rcv_nxt"), val("rx_hdr_offset"));
|
||||
PR(" frag0_idx %-10u length %-10u frag0_ptr 0x%-8x\n",
|
||||
val("rx_frag0_start_idx"),
|
||||
val("rx_frag0_len"),
|
||||
val("rx_ptr"));
|
||||
PR(" frag1_idx %-10u length %-10u ",
|
||||
val("rx_frag1_start_idx_offset"),
|
||||
val("rx_frag1_len"));
|
||||
|
||||
|
||||
|
||||
|
||||
if (val("ulp_type")!=4 && val("ulp_type")!=7) { /* RDMA has FRAG1 idx && len, but no ptr? Should I not display frag1 at all? */
|
||||
PR("frag1_ptr 0x%-8x\n",val("rx_frag1_ptr"));
|
||||
} else {
|
||||
PR("\n");
|
||||
}
|
||||
|
||||
|
||||
if (val("ulp_type") != 9 && val("ulp_type")!=8 && val("ulp_type") !=6 &&
|
||||
val("ulp_type") != 5 && val("ulp_type") !=4 && val("ulp_type") !=7) {
|
||||
PR(" frag2_idx %-10u length %-10u frag2_ptr 0x%-8x\n",
|
||||
val("rx_frag2_start_idx_offset"),
|
||||
val("rx_frag2_len"),
|
||||
val("rx_frag2_ptr"));
|
||||
PR(" frag3_idx %-10u length %-10u frag3_ptr 0x%-8x\n",
|
||||
val("rx_frag3_start_idx_offset"),
|
||||
val("rx_frag3_len"),
|
||||
val("rx_frag3_ptr"));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PR(" peer_fin %u, rx_pdu_out %u, pdu_len %u\n",
|
||||
val("peer_fin"),val("rx_pdu_out"), val("pdu_len"));
|
||||
|
||||
|
||||
|
||||
|
||||
if (val("recv_scale")) {
|
||||
PR(" rcv_wnd %u >> snd_scale %u == %u, recv_scaleflag = %u\n",
|
||||
val("rcv_wnd"), val("snd_scale"),
|
||||
val("rcv_wnd") >> val("snd_scale"),
|
||||
val("recv_scale"));
|
||||
} else {
|
||||
PR(" rcv_wnd %u. (snd_scale %u, recv_scaleflag = %u)\n",
|
||||
val("rcv_wnd"), val("snd_scale"),
|
||||
val("recv_scale"));
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
PR(" dack_mss %u dack %u, dack_not_acked: %u\n",
|
||||
val("dack_mss"),val("dack"),val("dack_not_acked"));
|
||||
PR(" rcv_coal %u rcv_co_psh %u rcv_co_last_psh %u heart %u\n",
|
||||
val("rcv_coalesce_enable"),
|
||||
val("rcv_coalesce_push"),
|
||||
val("rcv_coalesce_last_psh"),
|
||||
val("rcv_coalesce_heartbeat"));
|
||||
|
||||
PR(" rx_quiesce %u rx_flow_ctrl_dis %u,",
|
||||
val("rx_quiesce"),
|
||||
val("rx_flow_control_disable"));
|
||||
PR(" rx_flow_ctrl_ddp %u\n",
|
||||
val("rx_flow_control_ddp"));
|
||||
|
||||
|
||||
PR("MISCELANEOUS:\n"); /* *************************** */
|
||||
PR(" pend_ctl: 0x%1x, core_bypass: 0x%x, main_slush: 0x%x\n",
|
||||
((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) |
|
||||
val("pend_ctl0")),
|
||||
val("core_bypass"),val("main_slush"));
|
||||
PR(" Migrating %u, ask_mode %u, non_offload %u, rss_info %u\n",
|
||||
val("migrating"),
|
||||
val("ask_mode"), val("non_offload"), val("rss_info"));
|
||||
PR(" ULP: ulp_type %u (%s), ulp_raw %u",
|
||||
val("ulp_type"), spr_ulp_type(val("ulp_type")),
|
||||
val("ulp_raw"));
|
||||
|
||||
|
||||
if (aux==1) {
|
||||
PR(", ulp_ext %u",val("ulp_ext"));
|
||||
}
|
||||
PR("\n");
|
||||
|
||||
|
||||
|
||||
|
||||
PR(" RDMA: error %u, flm_err %u\n",
|
||||
val("rdma_error"), val("rdma_flm_error"));
|
||||
|
||||
|
||||
}
|
||||
void t7_display_tcb_aux_1 (_TCBVAR *tvp, int aux)
|
||||
{
|
||||
|
||||
|
||||
|
||||
PR(" aux1_slush0: 0x%x aux1_slush1 0x%x\n",
|
||||
val("aux1_slush0"), val("aux1_slush1"));
|
||||
PR(" pdu_hdr_len %u\n",val("pdu_hdr_len"));
|
||||
|
||||
|
||||
|
||||
}
|
||||
void t7_display_tcb_aux_2 (_TCBVAR *tvp, int aux)
|
||||
{
|
||||
|
||||
|
||||
|
||||
|
||||
PR(" qp_id %u, pd_id %u, stag %u\n",
|
||||
val("qp_id"), val("pd_id"),val("stag"));
|
||||
PR(" irs_ulp %u, iss_ulp %u\n",
|
||||
val("irs_ulp"),val("iss_ulp"));
|
||||
PR(" tx_pdu_len %u\n",
|
||||
val("tx_pdu_len"));
|
||||
PR(" cq_idx_sq %u, cq_idx_rq %u\n",
|
||||
val("cq_idx_sq"),val("cq_idx_rq"));
|
||||
PR(" rq_start %u, rq_MSN %u, rq_max_off %u, rq_write_ptr %u\n",
|
||||
val("rq_start"),val("rq_msn"),val("rq_max_offset"),
|
||||
val("rq_write_ptr"));
|
||||
PR(" L_valid %u, rdmap opcode %u\n",
|
||||
val("ord_l_bit_vld"),val("rdmap_opcode"));
|
||||
PR(" tx_flush: %u, tx_oos_rxmt %u, tx_oos_txmt %u\n",
|
||||
val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt"));
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
void t7_display_tcb_aux_3 (_TCBVAR *tvp, int aux)
|
||||
{
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PR(" aux3_slush: 0x%x, unused: buf0 0x%x, buf1: 0x%x\n",
|
||||
val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused"));
|
||||
|
||||
|
||||
PR(" ind_full: %u, tls_key_mode: %u\n",
|
||||
val("ddp_indicate_fll"),val("tls_key_mode"));
|
||||
|
||||
|
||||
PR(" DDP: DDPOFF ActBuf IndOut WaitFrag Rx2Tx BufInf\n");
|
||||
PR(" %u %u %u %u %u %u\n",
|
||||
val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"),
|
||||
val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf")
|
||||
);
|
||||
|
||||
|
||||
PR(" Ind PshfEn PushDis Flush NoInvalidate\n");
|
||||
PR(" Buf0: %u %u %u %u %u\n",
|
||||
val("ddp_buf0_indicate"),
|
||||
val("ddp_pshf_enable_0"), val("ddp_push_disable_0"),
|
||||
val("ddp_buf0_flush"), val("ddp_psh_no_invalidate0")
|
||||
);
|
||||
PR(" Buf1: %u %u %u %u %u\n",
|
||||
val("ddp_buf1_indicate"),
|
||||
val("ddp_pshf_enable_1"), val("ddp_push_disable_1"),
|
||||
val("ddp_buf1_flush"), val("ddp_psh_no_invalidate1")
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PR(" Valid Offset Length Tag\n");
|
||||
PR(" Buf0: %u 0x%6.6x 0x%6.6x 0x%8.8x",
|
||||
val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"),
|
||||
val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag")
|
||||
|
||||
|
||||
);
|
||||
if (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
|
||||
PR(" (Active)\n");
|
||||
} else {
|
||||
PR(" (Inactive)\n");
|
||||
}
|
||||
|
||||
|
||||
PR(" Buf1: %u 0x%6.6x 0x%6.6x 0x%8.8x",
|
||||
val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"),
|
||||
val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag")
|
||||
|
||||
|
||||
);
|
||||
|
||||
|
||||
if (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
|
||||
PR(" (Active)\n");
|
||||
} else {
|
||||
PR(" (Inactive)\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
if (1==val("ddp_off")) {
|
||||
PR(" DDP is off (which also disables indicate)\n");
|
||||
} else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
|
||||
PR(" Data being DDP'ed to buf 0, ");
|
||||
PR("which has %u - %u = %u bytes of space left\n",
|
||||
val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
|
||||
val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
|
||||
);
|
||||
if (1==val("ddp_buf1_valid")) {
|
||||
PR(" And buf1, which is also valid, has %u - %u = %u bytes of space left\n",
|
||||
val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
|
||||
val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
|
||||
);
|
||||
}
|
||||
} else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
|
||||
PR(" Data being DDP'ed to buf 1, ");
|
||||
PR("which has %u - %u = %u bytes of space left\n",
|
||||
val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
|
||||
val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
|
||||
);
|
||||
if (1==val("ddp_buf0_valid")) {
|
||||
PR(" And buf0, which is also valid, has %u - %u = %u bytes of space left\n",
|
||||
val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
|
||||
val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
|
||||
);
|
||||
}
|
||||
} else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) {
|
||||
PR(" !!! Invalid DDP buf 1 valid, but buf 0 active.\n");
|
||||
} else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
|
||||
PR(" !!! Invalid DDP buf 0 valid, but buf 1 active.\n");
|
||||
} else {
|
||||
PR(" DDP is enabled, but no buffers are active && valid.\n");
|
||||
|
||||
|
||||
|
||||
|
||||
if (0==val("ddp_indicate_out")) {
|
||||
if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) {
|
||||
PR(" 0 length Indicate buffers ");
|
||||
if (0==val("rx_hdr_offset")) {
|
||||
PR("will cause new data to be held in PMRX.\n");
|
||||
} else {
|
||||
PR("is causing %u bytes to be held in PMRX\n",
|
||||
val("rx_hdr_offset"));
|
||||
}
|
||||
} else {
|
||||
PR(" Data being indicated to host\n");
|
||||
}
|
||||
} else if (1==val("ddp_indicate_out")) {
|
||||
PR(" Indicate is off, which ");
|
||||
if (0==val("rx_hdr_offset")) {
|
||||
PR("will cause new data to be held in PMRX.\n");
|
||||
} else {
|
||||
PR("is causing %u bytes to be held in PMRX\n",
|
||||
val("rx_hdr_offset"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
void t7_display_tcb_aux_4 (_TCBVAR *tvp, int aux)
|
||||
{
|
||||
|
||||
|
||||
|
||||
PR("TLS: offset: 0x%6.6x, len:0x%6.6x, flags: 0x%4.4x\n",
|
||||
val("rx_tls_buf_offset"),val("rx_tls_buf_len"),
|
||||
val("rx_tls_flags"));
|
||||
PR(" seq: 0x%llx \n",val64("rx_tls_seq"));
|
||||
PR(" tag: 0x%8.8x, key:0x%8.8x\n",
|
||||
val("rx_tls_buf_tag"),val("rx_tls_key_tag"));
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user