Disable the use of the quantum cache in the GICv3 ITS

This uses UMA to allocate space. It causes issues when there are multiple
ITS devices in the system where interrupts are not allocated from a low
address on some interrupt controllers. Disabling the quantum cache fixes
this on the Neoverse N1 SDP.

MFC after:	2 weeks
Sponsored by:	DARPA, AFRL

This commit is contained in:

Andrew Turner

2020-02-03 13:47:41 +00:00

parent b0af1e20e6

commit a58fc7cb88

1 changed files with 1 additions and 1 deletions

									
										sys/arm64/arm64/gicv3_its.c
									
		+1
		-1
	
												View File
												
				@@ -800,7 +800,7 @@ gicv3_its_attach(device_t dev)

					 * system.

					 */

					sc->sc_irq_alloc = vmem_create("GICv3 ITS IRQs", 0,

					    gicv3_get_nirqs(dev), 1, 1, M_FIRSTFIT | M_WAITOK);

					    gicv3_get_nirqs(dev), 1, 0, M_FIRSTFIT | M_WAITOK);

					sc->sc_irqs = malloc(sizeof(*sc->sc_irqs) * sc->sc_irq_length,

					    M_GICV3_ITS, M_WAITOK | M_ZERO);