dts: Revert its addition for rk356x

Rockchip have two erratas (#3568001 and #3568002) for the GIC on RK356x.

Until we have a way to handle them revert the changes that uses ITS instead of
GIC for PCIe.
This commit is contained in:
Emmanuel Vadot
2025-11-22 18:32:54 +01:00
parent 55d98b024f
commit 55de86dac8
2 changed files with 5 additions and 17 deletions
@@ -152,7 +152,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x10 0x1f>;
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>;
@@ -175,7 +175,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x1000 &its 0x1000 0x1000>;
msi-map = <0x0 &gic 0x1000 0x1000>;
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
@@ -205,7 +205,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x20 0x2f>;
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
@@ -228,7 +228,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
msi-map = <0x2000 &its 0x2000 0x1000>;
msi-map = <0x0 &gic 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
@@ -283,18 +283,6 @@
mbi-alias = <0x0 0xfd410000>;
mbi-ranges = <296 24>;
msi-controller;
ranges;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
its: msi-controller@fd440000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0xfd440000 0 0x20000>;
dma-noncoherent;
msi-controller;
#msi-cells = <1>;
};
};
usb_host0_ehci: usb@fd800000 {
@@ -968,7 +956,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <2>;
msi-map = <0x0 &its 0x0 0x1000>;
msi-map = <0x0 &gic 0x0 0x1000>;
num-lanes = <1>;
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";