Polish AHCI disk identify data and fix speed negotiation.
MFC after: 2 weeks
This commit is contained in:
Alexander Motin
+20
-2
@@ -96,13 +96,14 @@
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#define ATA_SS_SPD_NO_SPEED 0x00000000
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#define ATA_SS_SPD_GEN1 0x00000010
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#define ATA_SS_SPD_GEN2 0x00000020
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#define ATA_SS_SPD_GEN3 0x00000040
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#define ATA_SS_SPD_GEN3 0x00000030
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#define ATA_SS_IPM_MASK 0x00000f00
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#define ATA_SS_IPM_NO_DEVICE 0x00000000
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#define ATA_SS_IPM_ACTIVE 0x00000100
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#define ATA_SS_IPM_PARTIAL 0x00000200
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#define ATA_SS_IPM_SLUMBER 0x00000600
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#define ATA_SS_IPM_DEVSLEEP 0x00000800
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#define ATA_SERROR 14
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#define ATA_SE_DATA_CORRECTED 0x00000001
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@@ -133,17 +134,19 @@
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#define ATA_SC_SPD_NO_SPEED 0x00000000
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#define ATA_SC_SPD_SPEED_GEN1 0x00000010
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#define ATA_SC_SPD_SPEED_GEN2 0x00000020
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#define ATA_SC_SPD_SPEED_GEN3 0x00000040
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#define ATA_SC_SPD_SPEED_GEN3 0x00000030
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#define ATA_SC_IPM_MASK 0x00000f00
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#define ATA_SC_IPM_NONE 0x00000000
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#define ATA_SC_IPM_DIS_PARTIAL 0x00000100
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#define ATA_SC_IPM_DIS_SLUMBER 0x00000200
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#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
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#define ATA_SACTIVE 16
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#define AHCI_MAX_PORTS 32
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#define AHCI_MAX_SLOTS 32
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#define AHCI_MAX_IRQS 16
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/* SATA AHCI v1.0 register defines */
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#define AHCI_CAP 0x00
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@@ -208,6 +211,9 @@
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#define AHCI_CAP2_BOH 0x00000001
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#define AHCI_CAP2_NVMP 0x00000002
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#define AHCI_CAP2_APST 0x00000004
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#define AHCI_CAP2_SDS 0x00000008
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#define AHCI_CAP2_SADM 0x00000010
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#define AHCI_CAP2_DESO 0x00000020
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#define AHCI_OFFSET 0x100
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#define AHCI_STEP 0x80
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@@ -265,6 +271,7 @@
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#define AHCI_P_CMD_ACTIVE 0x10000000
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#define AHCI_P_CMD_PARTIAL 0x20000000
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#define AHCI_P_CMD_SLUMBER 0x60000000
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#define AHCI_P_CMD_DEVSLEEP 0x80000000
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#define AHCI_P_TFD 0x20
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#define AHCI_P_SIG 0x24
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@@ -284,6 +291,17 @@
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#define AHCI_P_FBS_ADO_SHIFT 12
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#define AHCI_P_FBS_DWE 0x000f0000
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#define AHCI_P_FBS_DWE_SHIFT 16
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#define AHCI_P_DEVSLP 0x44
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#define AHCI_P_DEVSLP_ADSE 0x00000001
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#define AHCI_P_DEVSLP_DSP 0x00000002
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#define AHCI_P_DEVSLP_DETO 0x000003fc
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#define AHCI_P_DEVSLP_DETO_SHIFT 2
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#define AHCI_P_DEVSLP_MDAT 0x00007c00
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#define AHCI_P_DEVSLP_MDAT_SHIFT 10
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#define AHCI_P_DEVSLP_DITO 0x01ff8000
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#define AHCI_P_DEVSLP_DITO_SHIFT 15
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#define AHCI_P_DEVSLP_DM 0x0e000000
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#define AHCI_P_DEVSLP_DM_SHIFT 25
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/* Just to be sure, if building as module. */
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#if MAXPHYS < 512 * 1024
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+29
-15
@@ -431,7 +431,6 @@ ahci_port_stop(struct ahci_port *p)
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static void
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ahci_port_reset(struct ahci_port *pr)
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{
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pr->sctl = 0;
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pr->serr = 0;
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pr->sact = 0;
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pr->xfermode = ATA_UDMA6;
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@@ -443,8 +442,11 @@ ahci_port_reset(struct ahci_port *pr)
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pr->tfd = 0x7F;
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return;
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}
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pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
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ATA_SS_IPM_ACTIVE;
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pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
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if (pr->sctl & ATA_SC_SPD_MASK)
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pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
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else
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pr->ssts |= ATA_SS_SPD_GEN3;
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pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
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if (!pr->atapi) {
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pr->sig = PxSIG_ATA;
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@@ -470,6 +472,7 @@ ahci_reset(struct pci_ahci_softc *sc)
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for (i = 0; i < sc->ports; i++) {
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sc->port[i].ie = 0;
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sc->port[i].is = 0;
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sc->port[i].sctl = 0;
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ahci_port_reset(&sc->port[i]);
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}
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}
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@@ -807,26 +810,36 @@ handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
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buf[53] = (1 << 1 | 1 << 2);
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if (p->mult_sectors)
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buf[59] = (0x100 | p->mult_sectors);
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buf[60] = sectors;
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buf[61] = (sectors >> 16);
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if (sectors <= 0x0fffffff) {
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buf[60] = sectors;
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buf[61] = (sectors >> 16);
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} else {
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buf[60] = 0xffff;
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buf[61] = 0x0fff;
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}
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buf[63] = 0x7;
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if (p->xfermode & ATA_WDMA0)
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buf[63] |= (1 << ((p->xfermode & 7) + 8));
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buf[64] = 0x3;
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buf[65] = 100;
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buf[66] = 100;
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buf[67] = 100;
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buf[68] = 100;
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buf[65] = 120;
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buf[66] = 120;
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buf[67] = 120;
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buf[68] = 120;
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buf[69] = 0;
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buf[75] = 31;
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buf[76] = (1 << 8 | 1 << 2);
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buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
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ATA_SUPPORT_NCQ);
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buf[80] = 0x1f0;
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buf[81] = 0x28;
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buf[82] = (1 << 5 | 1 << 14);
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buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
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buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
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ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
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buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
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ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
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buf[84] = (1 << 14);
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buf[85] = (1 << 5 | 1 << 14);
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buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
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buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
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ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
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buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
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ATA_SUPPORT_FLUSHCACHE48);
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buf[87] = (1 << 14);
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buf[88] = 0x7f;
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if (p->xfermode & ATA_UDMA0)
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@@ -853,6 +866,7 @@ handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
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buf[117] = sectsz / 2;
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buf[118] = ((sectsz / 2) >> 16);
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}
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buf[222] = 0x1020;
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ahci_write_fis_piosetup(p);
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write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
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ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
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@@ -1850,10 +1864,10 @@ pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
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WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
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break;
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case AHCI_P_SCTL:
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p->sctl = value;
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if (!(p->cmd & AHCI_P_CMD_ST)) {
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if (value & ATA_SC_DET_RESET)
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ahci_port_reset(p);
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p->sctl = value;
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}
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break;
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case AHCI_P_SERR:
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