hwpmc: Add extra_mask sysctls per counter type

Expose kern.hwpmc.{ibs_fetch,ibs_op,amd_core,amd_l3,amd_df}_extra_mask
as RWTUN uint64s that OR into the CPUID-derived allow mask at
validation time. Default 0, so the strict policy applies unless an
administrator opts bits back in — intended for testing the wrmsr_safe
path in PR #2157.

Reviewed by:	mhorne, Ali Mashtizadeh <ali@mashtizadeh.com>
Sponsored by:	AMD
Signed-off-by:	Andre Silva <andasilv@amd.com>
Pull Request:	https://github.com/freebsd/freebsd-src/pull/2140

sys/dev/hwpmc/hwpmc_amd.c

@@ -40,6 +40,7 @@
 #include <sys/pmc.h>
 #include <sys/pmckern.h>
 #include <sys/smp.h>
+#include <sys/sysctl.h>
 #include <sys/systm.h>
 
 #include <machine/cpu.h>
@@ -183,6 +184,24 @@ static uint64_t amd_core_allowed_mask;
 static uint64_t amd_l3_allowed_mask;
 static uint64_t amd_df_allowed_mask;
 
+static uint64_t amd_core_extra_mask;
+static uint64_t amd_l3_extra_mask;
+static uint64_t amd_df_extra_mask;
+
+SYSCTL_DECL(_kern_hwpmc);
+
+SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_core_extra_mask, CTLFLAG_RDTUN,
+    &amd_core_extra_mask, 0,
+    "Extra allowed bits in AMD core PMU PERFEVTSEL (override; default 0)");
+
+SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_l3_extra_mask, CTLFLAG_RDTUN,
+    &amd_l3_extra_mask, 0,
+    "Extra allowed bits in AMD L3 PMU control (override; default 0)");
+
+SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_df_extra_mask, CTLFLAG_RDTUN,
+    &amd_df_extra_mask, 0,
+    "Extra allowed bits in AMD DF PMU control (override; default 0)");
+
 static void
 amd_init_policy(void)
 {
@@ -205,13 +224,13 @@ amd_config_mask(enum sub_class subclass, uint64_t caps)
 
 	switch (subclass) {
 	case PMC_AMD_SUB_CLASS_CORE:
-		return (amd_core_allowed_mask |
+		return (amd_core_allowed_mask | amd_core_extra_mask |
 		    (((caps & PMC_CAP_PRECISE) != 0) ?
 		    AMD_PMC_PRECISERETIRE : 0));
 	case PMC_AMD_SUB_CLASS_L3_CACHE:
-		return (amd_l3_allowed_mask);
+		return (amd_l3_allowed_mask | amd_l3_extra_mask);
 	case PMC_AMD_SUB_CLASS_DATA_FABRIC:
-		return (amd_df_allowed_mask);
+		return (amd_df_allowed_mask | amd_df_extra_mask);
 	default:
 		return (0);
 	}

sys/dev/hwpmc/hwpmc_ibs.c

@@ -36,6 +36,7 @@
 #include <sys/pmckern.h>
 #include <sys/pmclog.h>
 #include <sys/smp.h>
+#include <sys/sysctl.h>
 #include <sys/systm.h>
 
 #define	EXTERR_CATEGORY	EXTERR_CAT_HWPMC_IBS
@@ -60,6 +61,19 @@ static uint64_t ibs_features;
 static uint64_t ibs_fetch_allowed_mask;
 static uint64_t ibs_op_allowed_mask;
 
+static uint64_t ibs_fetch_extra_mask;
+static uint64_t ibs_op_extra_mask;
+
+SYSCTL_DECL(_kern_hwpmc);
+
+SYSCTL_U64(_kern_hwpmc, OID_AUTO, ibs_fetch_extra_mask, CTLFLAG_RDTUN,
+    &ibs_fetch_extra_mask, 0,
+    "Extra allowed bits in the IBS fetch control MSR (override; default 0)");
+
+SYSCTL_U64(_kern_hwpmc, OID_AUTO, ibs_op_extra_mask, CTLFLAG_RDTUN,
+    &ibs_op_extra_mask, 0,
+    "Extra allowed bits in the IBS op control MSR (override; default 0)");
+
 /*
  * Per-processor information
  */
@@ -98,7 +112,7 @@ static int
 ibs_validate_fetch_config(uint64_t config)
 {
 
-	if ((config & ~ibs_fetch_allowed_mask) != 0)
+	if ((config & ~(ibs_fetch_allowed_mask | ibs_fetch_extra_mask)) != 0)
 		return (EINVAL);
 
 	return (0);
@@ -120,6 +134,8 @@ ibs_validate_op_config(uint64_t config)
 		allowed_mask |= IBS_OP_CTL_LDLATMASK | IBS_OP_CTL_L3MISSONLY;
 	}
 
+	allowed_mask |= ibs_op_extra_mask;
+
 	if ((config & ~allowed_mask) != 0)
 		return (EINVAL);