ufshci: add uic powermode parameter to sysctl

Adds parameters related to the performance of the UFS device.
Also update man page for the missing sysctl entries.

Sponsored by:           Samsung Electronics
Reviewed by:		imp (mentor)
Differential Revision:	https://reviews.freebsd.org/D55985

share/man/man4/ufshci.4

@@ -124,9 +124,41 @@ nodes are currently implemented:
 (R) Host controller minor version.
 .It Va dev.ufshci.0.major_version
 (R) Host controller major version.
+.It Va dev.ufshci.0.wb_enabled
+(R) WriteBooster enable/disable.
+.It Va dev.ufshci.0.wb_flush_enabled
+(R) WriteBooster flush enable/disable.
+.It Va dev.ufshci.0.wb_buffer_type
+(R) WriteBooster type.
+.It Va dev.ufshci.0.wb_buffer_size_mb
+(R) WriteBooster buffer size in MB.
+.It Va dev.ufshci.0.wb_user_space_config_option
+(R) WriteBooster preserve user space mode.
+.It Va dev.ufshci.0.auto_hibernation_supported
+(R) Device auto hibernation support.
+.It Va dev.ufshci.0.auto_hibernate_idle_timer_value
+(R) Auto-Hibernate Idle Timer Value (in microseconds).
+.It Va dev.ufshci.0.power_mode_supported
+(R) Device power mode support.
+.It Va dev.ufshci.0.power_mode
+(R) Current device power mode.
+.It Va dev.ufshci.0.tx_rx_power_mode
+(R) Current TX/RX PA_PWRMode value.
+.It Va dev.ufshci.0.max_tx_lanes
+(R) Maximum available TX data lanes.
+.It Va dev.ufshci.0.max_rx_lanes
+(R) Maximum available RX data lanes.
+.It Va dev.ufshci.0.tx_lanes
+(R) Active TX data lanes.
+.It Va dev.ufshci.0.rx_lanes
+(R) Active RX data lanes.
+.It Va dev.ufshci.0.max_rx_hs_gear
+(R) Maximum available RX HS gear.
+.It Va dev.ufshci.0.hs_gear
+(R) Active HS gear.
 .It Va dev.ufshci.0.utmrq.num_failures
 (R) Number of failed UTP task-management requests.
-.It Va dev.ufshci.0.utmrq.ioq.num_retries
+.It Va dev.ufshci.0.utmrq.num_retries
 (R) Number of retried UTP task-management requests.
 .It Va dev.ufshci.0.utmrq.num_intr_handler_calls
 (R) Number of interrupt handler calls caused by UTP task-management requests.

sys/dev/ufshci/ufshci_dev.c

@@ -325,7 +325,7 @@ ufshci_dev_init_uic_power_mode(struct ufshci_controller *ctrlr)
 	 */
 	const uint32_t fast_mode = 1;
 	const uint32_t rx_bit_shift = 4;
-	uint32_t power_mode, peer_granularity;
+	uint32_t peer_granularity;
 
 	/* Update lanes with available TX/RX lanes */
 	if (ufshci_uic_send_dme_get(ctrlr, PA_AvailTxDataLanes,
@@ -352,9 +352,11 @@ ufshci_dev_init_uic_power_mode(struct ufshci_controller *ctrlr)
 
 	if (ctrlr->quirks & UFSHCI_QUIRK_CHANGE_LANE_AND_GEAR_SEPARATELY) {
 		/* Before changing gears, first change the number of lanes. */
-		if (ufshci_uic_send_dme_get(ctrlr, PA_PWRMode, &power_mode))
+		if (ufshci_uic_send_dme_get(ctrlr, PA_PWRMode,
+			&ctrlr->tx_rx_power_mode))
 			return (ENXIO);
-		if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode, power_mode))
+		if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode,
+			ctrlr->tx_rx_power_mode))
 			return (ENXIO);
 
 		/* Wait for power mode changed. */
@@ -415,8 +417,8 @@ ufshci_dev_init_uic_power_mode(struct ufshci_controller *ctrlr)
 		return (ENXIO);
 
 	/* Set TX/RX PWRMode */
-	power_mode = (fast_mode << rx_bit_shift) | fast_mode;
-	if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode, power_mode))
+	ctrlr->tx_rx_power_mode = (fast_mode << rx_bit_shift) | fast_mode;
+	if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode, ctrlr->tx_rx_power_mode))
 		return (ENXIO);
 
 	/* Wait for power mode changed. */

sys/dev/ufshci/ufshci_pci.c

@@ -34,8 +34,7 @@ static device_method_t ufshci_pci_methods[] = {
 	DEVMETHOD(device_attach, ufshci_pci_attach),
 	DEVMETHOD(device_detach, ufshci_pci_detach),
 	DEVMETHOD(device_suspend, ufshci_pci_suspend),
-	DEVMETHOD(device_resume, ufshci_pci_resume),
-	DEVMETHOD_END
+	DEVMETHOD(device_resume, ufshci_pci_resume), DEVMETHOD_END
 };
 
 static driver_t ufshci_pci_driver = {

sys/dev/ufshci/ufshci_private.h

@@ -396,7 +396,8 @@ struct ufshci_controller {
 
 	/* UFS Interconnect Layer (UIC) */
 	struct mtx uic_cmd_lock;
-	uint8_t hs_gear;
+	uint32_t tx_rx_power_mode;
+	uint32_t hs_gear;
 	uint32_t tx_lanes;
 	uint32_t rx_lanes;
 	uint32_t max_rx_hs_gear;

sys/dev/ufshci/ufshci_sysctl.c

@@ -193,7 +193,7 @@ ufshci_sysctl_initialize_ctrlr(struct ufshci_controller *ctrlr)
 	    CTLFLAG_RD, &ctrlr->num_io_queues, 0, "Number of I/O queue pairs");
 
 	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "cap", CTLFLAG_RD,
-	    &ctrlr->cap, 0, "Number of I/O queue pairs");
+	    &ctrlr->cap, 0, "Host controller capabilities register value");
 
 	SYSCTL_ADD_BOOL(ctrlr_ctx, ctrlr_list, OID_AUTO, "wb_enabled",
 	    CTLFLAG_RD, &dev->is_wb_enabled, 0, "WriteBooster enable/disable");
@@ -214,10 +214,6 @@ ufshci_sysctl_initialize_ctrlr(struct ufshci_controller *ctrlr)
 	    &dev->wb_user_space_config_option, 0,
 	    "WriteBooster preserve user space mode");
 
-	SYSCTL_ADD_BOOL(ctrlr_ctx, ctrlr_list, OID_AUTO, "power_mode_supported",
-	    CTLFLAG_RD, &dev->power_mode_supported, 0,
-	    "Device power mode support");
-
 	SYSCTL_ADD_BOOL(ctrlr_ctx, ctrlr_list, OID_AUTO,
 	    "auto_hibernation_supported", CTLFLAG_RD,
 	    &dev->auto_hibernation_supported, 0,
@@ -229,9 +225,38 @@ ufshci_sysctl_initialize_ctrlr(struct ufshci_controller *ctrlr)
 	    ufshci_sysctl_ahit, "IU",
 	    "Auto-Hibernate Idle Timer Value (in microseconds)");
 
+	SYSCTL_ADD_BOOL(ctrlr_ctx, ctrlr_list, OID_AUTO, "power_mode_supported",
+	    CTLFLAG_RD, &dev->power_mode_supported, 0,
+	    "Device power mode support");
+
 	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "power_mode",
 	    CTLFLAG_RD, &dev->power_mode, 0, "Current device power mode");
 
+	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "tx_rx_power_mode",
+	    CTLFLAG_RD, &ctrlr->tx_rx_power_mode, 0,
+	    "Current TX/RX PA_PWRMode value");
+
+	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "max_tx_lanes",
+	    CTLFLAG_RD, &ctrlr->max_tx_lanes, 0,
+	    "Maximum available TX data lanes");
+
+	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "max_rx_lanes",
+	    CTLFLAG_RD, &ctrlr->max_rx_lanes, 0,
+	    "Maximum available RX data lanes");
+
+	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "tx_lanes", CTLFLAG_RD,
+	    &ctrlr->tx_lanes, 0, "Active TX data lanes");
+
+	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "rx_lanes", CTLFLAG_RD,
+	    &ctrlr->rx_lanes, 0, "Active RX data lanes");
+
+	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "max_rx_hs_gear",
+	    CTLFLAG_RD, &ctrlr->max_rx_hs_gear, 0,
+	    "Maximum available RX HS gear");
+
+	SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "hs_gear", CTLFLAG_RD,
+	    &ctrlr->hs_gear, 0, "Active HS gear");
+
 	SYSCTL_ADD_PROC(ctrlr_ctx, ctrlr_list, OID_AUTO, "timeout_period",
 	    CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, &ctrlr->timeout_period,
 	    0, ufshci_sysctl_timeout_period, "IU",