mirror of
https://github.com/BoredDevNL/BoredOS.git
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647 lines
21 KiB
C
647 lines
21 KiB
C
// Copyright (c) 2023-2026 Chris (boreddevnl)
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// This software is released under the GNU General Public License v3.0. See LICENSE file for details.
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// This header needs to maintain in any file it is present in, as per the GPL license terms.
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#include "ahci.h"
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#include "pci.h"
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#include "disk.h"
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#include "memory_manager.h"
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#include "paging.h"
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#include "io.h"
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#include <stddef.h>
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#include "../sys/spinlock.h"
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extern void serial_write(const char *str);
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extern void serial_write_num(uint64_t num);
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extern void serial_write_hex(uint32_t val);
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// ============================================================================
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// AHCI Driver State
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// ============================================================================
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static HBA_MEM *abar = NULL; // MMIO-mapped AHCI Base Address
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static bool ahci_initialized = false;
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static int active_port_count = 0;
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#define MAX_AHCI_PORTS 32
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typedef struct {
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bool active;
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int port_num;
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HBA_PORT *port;
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HBA_CMD_HEADER *cmd_list; // 1KB, 1KB aligned
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void *fis_base; // 256B, 256B aligned
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HBA_CMD_TBL *cmd_tbl; // Command table for slot 0
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spinlock_t lock; // Port-level lock for thread-safety
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} ahci_port_state_t;
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static ahci_port_state_t ports[MAX_AHCI_PORTS];
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// ============================================================================
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// String Helpers
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// ============================================================================
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static void ahci_strcpy(char *d, const char *s) {
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while ((*d++ = *s++));
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}
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// Kernel virtual to physical address conversion
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extern uint64_t v2p(uint64_t vaddr);
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extern uint64_t p2v(uint64_t paddr);
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static int ahci_disk_sync(Disk *disk);
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static int ahci_find_free_slot(HBA_PORT *port);
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static void ahci_stop_cmd(HBA_PORT *port) {
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// Clear ST (Start)
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port->cmd &= ~HBA_PORT_CMD_ST;
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// Clear FRE (FIS Receive Enable)
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port->cmd &= ~HBA_PORT_CMD_FRE;
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// Wait until FR and CR clear
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int timeout = 500000;
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while (timeout-- > 0) {
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if (port->cmd & HBA_PORT_CMD_FR) continue;
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if (port->cmd & HBA_PORT_CMD_CR) continue;
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break;
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}
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}
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static void ahci_start_cmd(HBA_PORT *port) {
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// Wait until CR clears
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while (port->cmd & HBA_PORT_CMD_CR);
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// Set FRE and ST
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port->cmd |= HBA_PORT_CMD_FRE;
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port->cmd |= HBA_PORT_CMD_ST;
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}
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static int ahci_check_port_type(HBA_PORT *port) {
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uint32_t ssts = port->ssts;
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uint8_t ipm = (ssts >> 8) & 0x0F;
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uint8_t det = ssts & 0x0F;
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if (det != 3) return -1; // No device detected
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if (ipm != 1) return -1; // Not in active state
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switch (port->sig) {
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case SATA_SIG_ATA: return 0; // SATA drive
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case SATA_SIG_ATAPI: return 1; // SATAPI drive
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case SATA_SIG_SEMB: return 2; // SEMB
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case SATA_SIG_PM: return 3; // Port multiplier
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default: return -1;
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}
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}
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static void ahci_port_rebase(ahci_port_state_t *ps) {
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HBA_PORT *port = ps->port;
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ahci_stop_cmd(port);
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// Allocate command list (1KB, 1024-byte aligned)
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ps->cmd_list = (HBA_CMD_HEADER*)kmalloc_aligned(1024, 1024);
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if (!ps->cmd_list) return;
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mem_memset(ps->cmd_list, 0, 1024);
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uint64_t clb_phys = v2p((uint64_t)ps->cmd_list);
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port->clb = (uint32_t)(clb_phys & 0xFFFFFFFF);
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port->clbu = (uint32_t)(clb_phys >> 32);
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// Allocate FIS receive area (256 bytes, 256-byte aligned)
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ps->fis_base = kmalloc_aligned(256, 256);
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if (!ps->fis_base) return;
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mem_memset(ps->fis_base, 0, 256);
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uint64_t fb_phys = v2p((uint64_t)ps->fis_base);
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port->fb = (uint32_t)(fb_phys & 0xFFFFFFFF);
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port->fbu = (uint32_t)(fb_phys >> 32);
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int cmd_tbl_size = sizeof(HBA_CMD_TBL) + 32 * sizeof(HBA_PRDT_ENTRY);
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ps->cmd_tbl = (HBA_CMD_TBL*)kmalloc_aligned(cmd_tbl_size, 256);
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if (!ps->cmd_tbl) return;
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mem_memset(ps->cmd_tbl, 0, cmd_tbl_size);
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// Set command header 0 to point to our command table
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uint64_t ctba_phys = v2p((uint64_t)ps->cmd_tbl);
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ps->cmd_list[0].ctba = (uint32_t)(ctba_phys & 0xFFFFFFFF);
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ps->cmd_list[0].ctbau = (uint32_t)(ctba_phys >> 32);
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ps->cmd_list[0].prdtl = 1; // 1 PRDT entry default
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// Clear error and interrupt status
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port->serr = 0xFFFFFFFF;
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port->is = 0xFFFFFFFF;
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ahci_start_cmd(port);
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}
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static int ahci_find_free_slot(HBA_PORT *port) {
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uint32_t slots = (port->sact | port->ci);
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for (int i = 0; i < 32; i++) {
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if (!(slots & (1 << i))) return i;
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}
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return -1;
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}
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static int ahci_identify(int port_num, uint32_t *sectors, char *model) {
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ahci_port_state_t *ps = &ports[port_num];
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HBA_PORT *port = ps->port;
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uint64_t rflags = spinlock_acquire_irqsave(&ps->lock);
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port->is = 0xFFFFFFFF;
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int slot = ahci_find_free_slot(port);
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if (slot < 0) { spinlock_release_irqrestore(&ps->lock, rflags); return -1; }
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HBA_CMD_HEADER *cmd_hdr = &ps->cmd_list[slot];
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cmd_hdr->cfl = sizeof(FIS_REG_H2D) / sizeof(uint32_t);
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cmd_hdr->w = 0;
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cmd_hdr->prdtl = 1;
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HBA_CMD_TBL *cmd_tbl = ps->cmd_tbl;
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mem_memset(cmd_tbl, 0, sizeof(HBA_CMD_TBL) + 32 * sizeof(HBA_PRDT_ENTRY));
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uint16_t *buf = (uint16_t*)kmalloc_aligned(512, 512);
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uint64_t phys = v2p((uint64_t)buf);
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cmd_tbl->prdt[0].dba = (uint32_t)(phys & 0xFFFFFFFF);
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cmd_tbl->prdt[0].dbau = (uint32_t)(phys >> 32);
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cmd_tbl->prdt[0].dbc = 511; // 512 bytes
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cmd_tbl->prdt[0].i = 1;
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FIS_REG_H2D *fis = (FIS_REG_H2D*)(&cmd_tbl->cfis);
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fis->fis_type = FIS_TYPE_REG_H2D;
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fis->c = 1; // Command
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fis->command = 0xEC; // IDENTIFY DEVICE
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// Wait for port to be idle
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int timeout = 1000000;
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while ((port->tfd & (ATA_SR_BSY | ATA_SR_DRQ)) && --timeout > 0);
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if (timeout <= 0) { kfree(buf); spinlock_release_irqrestore(&ps->lock, rflags); return -1; }
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port->ci = (1 << slot);
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while (1) {
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if ((port->ci & (1 << slot)) == 0) break;
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if (port->is & HBA_PORT_IS_TFES) { kfree(buf); spinlock_release_irqrestore(&ps->lock, rflags); return -1; }
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}
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// Extract sectors (28-bit LBA for now, or 48-bit if supported)
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uint32_t s28 = *((uint32_t*)&buf[60]);
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uint64_t s48 = *((uint64_t*)&buf[100]);
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if (s48 > 0) *sectors = (uint32_t)s48;
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else *sectors = s28;
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// Extract model name (Words 27-46, 40 bytes, big-endian shorts)
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for (int i = 0; i < 20; i++) {
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model[i*2] = (char)(buf[27+i] >> 8);
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model[i*2+1] = (char)(buf[27+i] & 0xFF);
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}
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model[40] = 0;
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// Swap bytes in model string (ATA strings are byte-swapped)
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for (int i = 0; i < 40; i += 2) {
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char tmp = model[i];
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model[i] = model[i+1];
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model[i+1] = tmp;
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}
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kfree(buf);
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spinlock_release_irqrestore(&ps->lock, rflags);
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return 0;
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}
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int ahci_read_sectors(int port_num, uint64_t lba, uint32_t count, uint8_t *buffer) {
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if (!ahci_initialized || port_num < 0 || port_num >= MAX_AHCI_PORTS) return -1;
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ahci_port_state_t *ps = &ports[port_num];
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if (!ps->active) return -1;
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uint64_t rflags = spinlock_acquire_irqsave(&ps->lock);
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HBA_PORT *port = ps->port;
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// Clear any pending interrupts/errors
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port->is = 0xFFFFFFFF;
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int slot = ahci_find_free_slot(port);
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if (slot < 0) return -1;
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HBA_CMD_HEADER *cmd_hdr = &ps->cmd_list[slot];
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cmd_hdr->cfl = sizeof(FIS_REG_H2D) / sizeof(uint32_t);
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cmd_hdr->w = 0; // Read
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cmd_hdr->prdtl = 1;
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HBA_CMD_TBL *cmd_tbl = ps->cmd_tbl;
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mem_memset(cmd_tbl, 0, sizeof(HBA_CMD_TBL) + 32 * sizeof(HBA_PRDT_ENTRY));
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extern uint64_t paging_get_pml4_phys(void);
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extern uint64_t paging_virt2phys(uint64_t pml4_phys, uint64_t virtual_addr);
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uint64_t pml4 = paging_get_pml4_phys();
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uint64_t buf_addr = (uint64_t)buffer;
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uint32_t remaining = count * 512;
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int prd_idx = 0;
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while (remaining > 0 && prd_idx < 32) {
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uint64_t phys = paging_virt2phys(pml4, buf_addr);
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if (!phys) {
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spinlock_release_irqrestore(&ps->lock, rflags);
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return -1;
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}
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uint32_t offset = buf_addr & 0xFFF;
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uint32_t can_do = 4096 - offset;
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if (can_do > remaining) can_do = remaining;
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cmd_tbl->prdt[prd_idx].dba = (uint32_t)(phys & 0xFFFFFFFF);
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cmd_tbl->prdt[prd_idx].dbau = (uint32_t)(phys >> 32);
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cmd_tbl->prdt[prd_idx].dbc = can_do - 1; // 0-based
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cmd_tbl->prdt[prd_idx].i = 0;
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buf_addr += can_do;
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remaining -= can_do;
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prd_idx++;
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}
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if (prd_idx > 0) cmd_tbl->prdt[prd_idx - 1].i = 1; // Interrupt on last
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cmd_hdr->prdtl = prd_idx;
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// Setup Command FIS
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FIS_REG_H2D *fis = (FIS_REG_H2D*)&cmd_tbl->cfis;
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fis->fis_type = FIS_TYPE_REG_H2D;
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fis->c = 1; // Command
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fis->command = ATA_CMD_READ_DMA_EX;
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fis->lba0 = (uint8_t)(lba);
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fis->lba1 = (uint8_t)(lba >> 8);
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fis->lba2 = (uint8_t)(lba >> 16);
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fis->device = 1 << 6; // LBA mode
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fis->lba3 = (uint8_t)(lba >> 24);
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fis->lba4 = (uint8_t)(lba >> 32);
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fis->lba5 = (uint8_t)(lba >> 40);
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fis->countl = (uint8_t)(count);
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fis->counth = (uint8_t)(count >> 8);
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// Issue command
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port->ci = (1 << slot);
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// Wait for completion
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int timeout = 1000000;
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while (timeout-- > 0) {
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if (!(port->ci & (1 << slot))) break;
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if (port->is & (1 << 30)) { // Task File Error
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serial_write("\n");
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spinlock_release_irqrestore(&ps->lock, rflags);
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return -1;
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}
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}
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if (timeout <= 0) {
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serial_write("[AHCI] Read timeout on port ");
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serial_write_num(port_num);
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serial_write("\n");
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spinlock_release_irqrestore(&ps->lock, rflags);
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return -1;
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}
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spinlock_release_irqrestore(&ps->lock, rflags);
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return 0;
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}
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int ahci_write_sectors(int port_num, uint64_t lba, uint32_t count, const uint8_t *buffer) {
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if (!ahci_initialized || port_num < 0 || port_num >= MAX_AHCI_PORTS) return -1;
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ahci_port_state_t *ps = &ports[port_num];
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if (!ps->active) return -1;
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uint64_t rflags = spinlock_acquire_irqsave(&ps->lock);
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HBA_PORT *port = ps->port;
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port->is = 0xFFFFFFFF;
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int slot = ahci_find_free_slot(port);
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if (slot < 0) return -1;
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HBA_CMD_HEADER *cmd_hdr = &ps->cmd_list[slot];
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cmd_hdr->cfl = sizeof(FIS_REG_H2D) / sizeof(uint32_t);
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cmd_hdr->w = 1; // Write
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cmd_hdr->prdtl = 1;
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HBA_CMD_TBL *cmd_tbl = ps->cmd_tbl;
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mem_memset(cmd_tbl, 0, sizeof(HBA_CMD_TBL) + 32 * sizeof(HBA_PRDT_ENTRY));
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// Setup PRDT - handle buffers spanning multiple physical pages
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extern uint64_t paging_get_pml4_phys(void);
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extern uint64_t paging_virt2phys(uint64_t pml4_phys, uint64_t virtual_addr);
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uint64_t pml4 = paging_get_pml4_phys();
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uint64_t buf_addr = (uint64_t)buffer;
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uint32_t remaining = count * 512;
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int prd_idx = 0;
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while (remaining > 0 && prd_idx < 32) {
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uint64_t phys = paging_virt2phys(pml4, buf_addr);
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if (!phys) {
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spinlock_release_irqrestore(&ps->lock, rflags);
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return -1;
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}
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uint32_t offset = buf_addr & 0xFFF;
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uint32_t can_do = 4096 - offset;
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if (can_do > remaining) can_do = remaining;
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cmd_tbl->prdt[prd_idx].dba = (uint32_t)(phys & 0xFFFFFFFF);
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cmd_tbl->prdt[prd_idx].dbau = (uint32_t)(phys >> 32);
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cmd_tbl->prdt[prd_idx].dbc = can_do - 1; // 0-based
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cmd_tbl->prdt[prd_idx].i = 0;
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buf_addr += can_do;
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remaining -= can_do;
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prd_idx++;
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}
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if (prd_idx > 0) cmd_tbl->prdt[prd_idx - 1].i = 1; // Interrupt on last
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cmd_hdr->prdtl = prd_idx;
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FIS_REG_H2D *fis = (FIS_REG_H2D*)&cmd_tbl->cfis;
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fis->fis_type = FIS_TYPE_REG_H2D;
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fis->c = 1;
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fis->command = ATA_CMD_WRITE_DMA_EX;
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fis->lba0 = (uint8_t)(lba);
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fis->lba1 = (uint8_t)(lba >> 8);
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fis->lba2 = (uint8_t)(lba >> 16);
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fis->device = 1 << 6;
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fis->lba3 = (uint8_t)(lba >> 24);
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fis->lba4 = (uint8_t)(lba >> 32);
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fis->lba5 = (uint8_t)(lba >> 40);
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fis->countl = (uint8_t)(count);
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fis->counth = (uint8_t)(count >> 8);
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port->ci = (1 << slot);
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int timeout = 1000000;
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while (timeout-- > 0) {
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if (!(port->ci & (1 << slot))) break;
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if (port->is & (1 << 30)) {
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serial_write("[AHCI] Write error on port ");
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serial_write_num(port_num);
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serial_write("\n");
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spinlock_release_irqrestore(&ps->lock, rflags);
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return -1;
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}
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}
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if (timeout <= 0) {
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serial_write("[AHCI] Write timeout on port ");
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serial_write_num(port_num);
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serial_write("\n");
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spinlock_release_irqrestore(&ps->lock, rflags);
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return -1;
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}
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spinlock_release_irqrestore(&ps->lock, rflags);
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return 0;
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}
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// ============================================================================
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// AHCI Disk Integration — wrap AHCI into Disk read/write_sector
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// ============================================================================
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typedef struct {
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int ahci_port;
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} AHCIDriverData;
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static int ahci_disk_read_sector(Disk *disk, uint32_t sector, uint8_t *buffer) {
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AHCIDriverData *data = (AHCIDriverData*)disk->driver_data;
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// For partitions, add offset and use parent's port
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if (disk->is_partition && disk->parent) {
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AHCIDriverData *pdata = (AHCIDriverData*)disk->parent->driver_data;
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return ahci_read_sectors(pdata->ahci_port,
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(uint64_t)sector + disk->partition_lba_offset, 1, buffer);
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}
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return ahci_read_sectors(data->ahci_port, (uint64_t)sector, 1, buffer);
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}
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static int ahci_disk_write_sector(Disk *disk, uint32_t sector, const uint8_t *buffer) {
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AHCIDriverData *data = (AHCIDriverData*)disk->driver_data;
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if (disk->is_partition && disk->parent) {
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AHCIDriverData *pdata = (AHCIDriverData*)disk->parent->driver_data;
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return ahci_write_sectors(pdata->ahci_port,
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(uint64_t)sector + disk->partition_lba_offset, 1, buffer);
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}
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return ahci_write_sectors(data->ahci_port, (uint64_t)sector, 1, buffer);
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}
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static int ahci_disk_read_sectors(Disk *disk, uint32_t sector, uint32_t count, uint8_t *buffer) {
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AHCIDriverData *data = (AHCIDriverData*)disk->driver_data;
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if (disk->is_partition && disk->parent) {
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AHCIDriverData *pdata = (AHCIDriverData*)disk->parent->driver_data;
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return ahci_read_sectors(pdata->ahci_port, (uint64_t)sector + disk->partition_lba_offset, count, buffer);
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}
|
|
return ahci_read_sectors(data->ahci_port, (uint64_t)sector, count, buffer);
|
|
}
|
|
|
|
static int ahci_disk_write_sectors(Disk *disk, uint32_t sector, uint32_t count, const uint8_t *buffer) {
|
|
AHCIDriverData *data = (AHCIDriverData*)disk->driver_data;
|
|
if (disk->is_partition && disk->parent) {
|
|
AHCIDriverData *pdata = (AHCIDriverData*)disk->parent->driver_data;
|
|
return ahci_write_sectors(pdata->ahci_port, (uint64_t)sector + disk->partition_lba_offset, count, buffer);
|
|
}
|
|
return ahci_write_sectors(data->ahci_port, (uint64_t)sector, count, buffer);
|
|
}
|
|
|
|
// ============================================================================
|
|
// Initialization
|
|
// ============================================================================
|
|
|
|
int ahci_get_port_count(void) {
|
|
return active_port_count;
|
|
}
|
|
|
|
bool ahci_port_is_active(int port_num) {
|
|
if (port_num < 0 || port_num >= MAX_AHCI_PORTS) return false;
|
|
return ports[port_num].active;
|
|
}
|
|
|
|
void ahci_init(void) {
|
|
serial_write("[AHCI] Scanning PCI for AHCI controller...\n");
|
|
|
|
// Find AHCI controller (Class 0x01, Subclass 0x06)
|
|
pci_device_t pci_dev;
|
|
if (!pci_find_device_by_class(PCI_CLASS_MASS_STORAGE, PCI_SUBCLASS_SATA, &pci_dev)) {
|
|
serial_write("[AHCI] No AHCI controller found\n");
|
|
return;
|
|
}
|
|
|
|
serial_write("[AHCI] Found AHCI controller (");
|
|
serial_write("vendor=0x");
|
|
serial_write_hex(pci_dev.vendor_id);
|
|
serial_write(", device=0x");
|
|
serial_write_hex(pci_dev.device_id);
|
|
serial_write(")\n");
|
|
|
|
// Enable Bus Mastering and MMIO
|
|
pci_enable_bus_mastering(&pci_dev);
|
|
pci_enable_mmio(&pci_dev);
|
|
|
|
// Read ABAR (BAR5)
|
|
uint32_t abar_raw = pci_get_bar(&pci_dev, 5);
|
|
uint64_t abar_phys = abar_raw & 0xFFFFF000; // Mask out lower bits
|
|
|
|
if (abar_phys == 0) {
|
|
serial_write("[AHCI] Invalid ABAR address\n");
|
|
return;
|
|
}
|
|
|
|
serial_write("[AHCI] ABAR physical address: 0x");
|
|
serial_write_hex((uint32_t)abar_phys);
|
|
serial_write("\n");
|
|
|
|
uint64_t abar_virt = p2v(abar_phys);
|
|
for (uint64_t offset = 0; offset < 0x2000; offset += 4096) {
|
|
paging_map_page(paging_get_pml4_phys(), abar_virt + offset,
|
|
abar_phys + offset,
|
|
PT_PRESENT | PT_RW | PT_CACHE_DISABLE);
|
|
}
|
|
|
|
abar = (HBA_MEM*)abar_virt;
|
|
|
|
// Enable AHCI mode
|
|
abar->ghc |= (1 << 31); // AE (AHCI Enable)
|
|
|
|
serial_write("[AHCI] Version: ");
|
|
serial_write_num(abar->vs >> 16);
|
|
serial_write(".");
|
|
serial_write_num(abar->vs & 0xFFFF);
|
|
serial_write("\n");
|
|
|
|
// Probe ports
|
|
uint32_t pi = abar->pi;
|
|
active_port_count = 0;
|
|
|
|
for (int i = 0; i < 32; i++) {
|
|
ports[i].active = false;
|
|
|
|
HBA_PORT *port = &abar->ports[i];
|
|
ports[i].lock = SPINLOCK_INIT;
|
|
int type = ahci_check_port_type(port);
|
|
|
|
if (type == 0) { // SATA drive
|
|
serial_write("[AHCI] Port ");
|
|
serial_write_num(i);
|
|
serial_write(": SATA drive detected\n");
|
|
|
|
ports[i].port_num = i;
|
|
ports[i].port = port;
|
|
ahci_port_rebase(&ports[i]);
|
|
ports[i].active = true;
|
|
active_port_count++;
|
|
ahci_initialized = true;
|
|
|
|
// Register as a block device
|
|
Disk *disk = (Disk*)kmalloc(sizeof(Disk));
|
|
if (disk) {
|
|
AHCIDriverData *drv = (AHCIDriverData*)kmalloc(sizeof(AHCIDriverData));
|
|
drv->ahci_port = i;
|
|
|
|
disk->devname[0] = 0; // Auto-assign
|
|
disk->type = DISK_TYPE_SATA;
|
|
|
|
uint32_t sectors = 0;
|
|
char model[64];
|
|
if (ahci_identify(i, §ors, model) == 0) {
|
|
ahci_strcpy(disk->label, model);
|
|
disk->total_sectors = sectors;
|
|
} else {
|
|
ahci_strcpy(disk->label, "SATA Drive");
|
|
disk->total_sectors = 0;
|
|
}
|
|
|
|
disk->read_sector = ahci_disk_read_sector;
|
|
disk->write_sector = ahci_disk_write_sector;
|
|
disk->read_sectors = ahci_disk_read_sectors;
|
|
disk->write_sectors = ahci_disk_write_sectors;
|
|
disk->sync = ahci_disk_sync;
|
|
disk->driver_data = drv;
|
|
disk->partition_lba_offset = 0;
|
|
disk->parent = NULL;
|
|
disk->is_partition = false;
|
|
disk->is_fat32 = false;
|
|
|
|
disk_register(disk);
|
|
|
|
extern void serial_write(const char *str);
|
|
extern int disk_rescan(Disk *disk);
|
|
serial_write("[AHCI] Probing partitions on /dev/");
|
|
serial_write(disk->devname);
|
|
serial_write("...\n");
|
|
disk_rescan(disk);
|
|
}
|
|
} else if (type == 1) {
|
|
serial_write("[AHCI] Port ");
|
|
serial_write_num(i);
|
|
serial_write(": SATAPI drive (ignored)\n");
|
|
}
|
|
}
|
|
|
|
if (active_port_count > 0) {
|
|
ahci_initialized = true;
|
|
serial_write("[AHCI] Initialization complete: ");
|
|
serial_write_num(active_port_count);
|
|
serial_write(" SATA port(s) active\n");
|
|
} else {
|
|
serial_write("[AHCI] No active SATA ports found\n");
|
|
}
|
|
}
|
|
|
|
int ahci_flush_cache(int port_num) {
|
|
HBA_PORT *port = &abar->ports[port_num];
|
|
ahci_port_state_t *ps = &ports[port_num];
|
|
|
|
if (port_num < 0 || port_num >= 32 || !ps->active) return -1;
|
|
|
|
uint64_t rflags = spinlock_acquire_irqsave(&ps->lock);
|
|
|
|
port->is = 0xFFFFFFFF; // Clear interrupts
|
|
int slot = ahci_find_free_slot(port);
|
|
if (slot == -1) { spinlock_release_irqrestore(&ps->lock, rflags); return -1; }
|
|
|
|
HBA_CMD_HEADER *cmd_header = (HBA_CMD_HEADER*)p2v(port->clb);
|
|
cmd_header += slot;
|
|
cmd_header->cfl = sizeof(FIS_REG_H2D) / 4;
|
|
cmd_header->w = 0;
|
|
cmd_header->prdtl = 0;
|
|
|
|
HBA_CMD_TBL *cmd_tbl = (HBA_CMD_TBL*)p2v(cmd_header->ctba);
|
|
for (int i = 0; i < 256; i++) ((uint8_t*)cmd_tbl)[i] = 0;
|
|
|
|
FIS_REG_H2D *fis = (FIS_REG_H2D*)(&cmd_tbl->cfis);
|
|
fis->fis_type = FIS_TYPE_REG_H2D;
|
|
fis->c = 1;
|
|
fis->command = 0xEA; // FLUSH CACHE EXT
|
|
|
|
// Wait for port to be ready
|
|
int timeout = 1000000;
|
|
while ((port->tfd & (ATA_SR_BSY | ATA_SR_DRQ)) && --timeout > 0);
|
|
if (timeout == 0) { spinlock_release_irqrestore(&ps->lock, rflags); return -1; }
|
|
|
|
port->ci = (1 << slot);
|
|
|
|
while (1) {
|
|
if ((port->ci & (1 << slot)) == 0) break;
|
|
if (port->is & HBA_PORT_IS_TFES) { spinlock_release_irqrestore(&ps->lock, rflags); return -1; }
|
|
}
|
|
|
|
spinlock_release_irqrestore(&ps->lock, rflags);
|
|
return 0;
|
|
}
|
|
|
|
static int ahci_disk_sync(Disk *disk) {
|
|
AHCIDriverData *drv = (AHCIDriverData*)disk->driver_data;
|
|
if (!drv) return -1;
|
|
return ahci_flush_cache(drv->ahci_port);
|
|
}
|
|
|