David E. O'Brien
d1ca01059d
Reviewed by: khng Differential Revision: https://reviews.freebsd.org/D53309
357 lines
11 KiB
Plaintext
357 lines
11 KiB
Plaintext
#
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# NOTES -- Lines that can be cut/pasted into kernel and hints configs.
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#
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# This file contains machine dependent kernel configuration notes. For
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# machine independent notes, look in /sys/conf/NOTES. For notes shared
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# with amd64, look in /sys/x86/conf/NOTES.
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#
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#
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#####################################################################
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# SMP OPTIONS:
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#
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# The apic device enables the use of the I/O APIC for interrupt delivery.
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# The apic device can be used in both UP and SMP kernels, but is required
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# for SMP kernels. Thus, the apic device is not strictly an SMP option,
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# but it is a prerequisite for SMP.
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#
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# Notes:
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#
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# HTT CPUs should only be used if they are enabled in the BIOS. For
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# the ACPI case, ACPI only correctly tells us about any HTT CPUs if
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# they are enabled. However, most HTT systems do not list HTT CPUs
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# in the MP Table if they are enabled, thus we guess at the HTT CPUs
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# for the MP Table case. However, we shouldn't try to guess and use
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# these CPUs if HTT is disabled. Thus, HTT guessing is only enabled
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# for the MP Table if the user explicitly asks for it via the
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# MPTABLE_FORCE_HTT option. Do NOT use this option if you have HTT
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# disabled in your BIOS.
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#
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# IPI_PREEMPTION instructs the kernel to preempt threads running on other
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# CPUS if needed. Relies on the PREEMPTION option
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# Mandatory:
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device apic # I/O apic
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# Optional:
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options MPTABLE_FORCE_HTT # Enable HTT CPUs with the MP Table
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#####################################################################
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# CPU OPTIONS
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#
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# You must specify at least one CPU (the one you intend to run on);
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# deleting the specification for CPUs you don't need to use may make
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# parts of the system run faster.
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#
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cpu I486_CPU
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cpu I586_CPU # aka Pentium(tm)
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cpu I686_CPU # aka Pentium Pro(tm)
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#
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# Options for CPU features.
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#
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# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has
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# forgotten to enable them.
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#
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# CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning
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# CPU if CPU supports it. The default is double-clock mode on
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# BlueLightning CPU box.
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#
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# CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM
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# BlueLightning CPU. It works only with Cyrix FPU, and this option
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# should not be used with Intel FPU.
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#
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# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
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#
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# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
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# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
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# Otherwise, the NO_LOCK bit of CCR1 is cleared. (NOTE 3)
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#
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# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
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# mapped mode. Default is 2-way set associative mode.
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#
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# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e., enables
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# reorder). This option should not be used if you use memory mapped
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# I/O device(s).
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#
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# CPU_ELAN enables support for AMDs ElanSC520 CPU.
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# CPU_ELAN_PPS enables precision timestamp code.
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# CPU_ELAN_XTAL sets the clock crystal frequency in Hz.
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#
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# CPU_ENABLE_LONGRUN enables support for Transmeta Crusoe LongRun
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# technology which allows to restrict power consumption of the CPU by
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# using group of hw.crusoe.* sysctls.
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#
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# CPU_FASTER_5X86_FPU enables faster FPU exception handler.
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#
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# CPU_GEODE is for the SC1100 Geode embedded processor. This option
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# is necessary because the i8254 timecounter is toast.
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#
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# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
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# for i386 machines.
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#
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# CPU_IORT defines I/O clock delay time (NOTE 1). Default values of
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# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
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# (no clock delay).
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#
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# CPU_L2_LATENCY specifies the L2 cache latency value. This option is used
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# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
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# The default value is 5.
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#
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# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
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# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
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# 1).
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#
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# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option
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# is useful when you use Socket 8 to Socket 370 converter, because most Pentium
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# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
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#
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# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
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#
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# CPU_SOEKRIS enables support www.soekris.com hardware.
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#
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# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
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# enters suspend mode following execution of HALT instruction.
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#
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# CPU_UPGRADE_HW_CACHE eliminates unneeded cache flush instruction(s).
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#
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# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
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# K5/K6/K6-2 CPUs.
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#
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# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
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# flush at hold state.
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#
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# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs
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# without cache flush at hold state, and (2) write-back CPU cache on
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# Cyrix 6x86 whose revision < 2.7 (NOTE 2).
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#
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# NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY
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# Pentiums) from locking up when a LOCK CMPXCHG8B instruction is
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# executed. This option is only needed if I586_CPU is also defined,
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# and should be included for any non-Pentium CPU that defines it.
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#
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# NO_MEMORY_HOLE is an optimisation for systems with AMD K6 processors
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# which indicates that the 15-16MB range is *definitely* not being
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# occupied by an ISA memory hole.
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#
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# NOTE 1: The options, CPU_BTB_EN, CPU_LOOP_EN, CPU_IORT,
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# CPU_LOOP_EN and CPU_RSTK_EN should not be used because of CPU bugs.
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# These options may crash your system.
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#
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# NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled
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# in write-through mode when revision < 2.7. If revision of Cyrix
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# 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
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#
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# NOTE 3: This option may cause failures for software that requires
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# locked cycles in order to operate correctly.
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#
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options CPU_ATHLON_SSE_HACK
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options CPU_BLUELIGHTNING_3X
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options CPU_BLUELIGHTNING_FPU_OP_CACHE
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options CPU_BTB_EN
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options CPU_DIRECT_MAPPED_CACHE
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options CPU_DISABLE_5X86_LSSER
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options CPU_ELAN
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options CPU_ELAN_PPS
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options CPU_ELAN_XTAL=32768000
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options CPU_ENABLE_LONGRUN
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options CPU_FASTER_5X86_FPU
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options CPU_GEODE
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options CPU_I486_ON_386
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options CPU_IORT
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options CPU_L2_LATENCY=5
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options CPU_LOOP_EN
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options CPU_PPRO2CELERON
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options CPU_RSTK_EN
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options CPU_SOEKRIS
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options CPU_SUSP_HLT
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options CPU_UPGRADE_HW_CACHE
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options CPU_WT_ALLOC
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options CYRIX_CACHE_WORKS
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options CYRIX_CACHE_REALLY_WORKS
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#options NO_F00F_HACK
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# Debug options
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options NPX_DEBUG # enable npx debugging
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#
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# PERFMON causes the driver for Pentium/Pentium Pro performance counters
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# to be compiled. See perfmon(4) for more information.
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#
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options PERFMON
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#
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# Hints for the non-optional Numeric Processing eXtension driver.
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envvar hint.npx.0.flags="0x0"
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envvar hint.npx.0.irq="13"
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#
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# `flags' for npx0:
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# 0x01 don't use the npx registers to optimize bcopy.
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# 0x02 don't use the npx registers to optimize bzero.
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# 0x04 don't use the npx registers to optimize copyin or copyout.
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# The npx registers are normally used to optimize copying and zeroing when
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# all of the following conditions are satisfied:
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# I586_CPU is an option
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# the cpu is an i586 (perhaps not a Pentium)
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# the probe for npx0 succeeds
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# INT 16 exception handling works.
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# Then copying and zeroing using the npx registers is normally 30-100% faster.
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# The flags can be used to control cases where it doesn't work or is slower.
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# Setting them at boot time using hints works right (the optimizations
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# are not used until later in the bootstrap when npx0 is attached).
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# Flag 0x08 automatically disables the i586 optimized routines.
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#
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#####################################################################
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# HARDWARE DEVICE CONFIGURATION
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#
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# Optional devices:
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#
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# 3Dfx Voodoo Graphics, Voodoo II /dev/3dfx CDEV support. This will create
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# the /dev/3dfx0 device to work with glide implementations. This should get
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# linked to /dev/3dfx and /dev/voodoo. Note that this is not the same as
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# the tdfx DRI module from XFree86 and is completely unrelated.
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#
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# To enable Linuxulator support, one must also load linux.ko and tdfx_linux.ko.
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device tdfx # Enable 3Dfx Voodoo support
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#
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# RAID adapters
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#
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device pst
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#
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# Adaptec by PMC RAID controllers, Series 6/7/8 and upcoming families
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device aacraid # Container interface, CAM required
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#
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# Network interfaces:
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#
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# sbni: Granch SBNI12-xx ISA and PCI adapters
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# vmx: VMware VMXNET3 Ethernet (BSD open source)
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# wpi: Intel 3945ABG Wireless LAN controller
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# Requires the wpi firmware module
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# Order for ISA/EISA devices is important here
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envvar hint.cs.0.at="isa"
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envvar hint.cs.0.port="0x300"
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envvar hint.ed.0.at="isa"
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envvar hint.ed.0.port="0x280"
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envvar hint.ed.0.irq="5"
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envvar hint.ed.0.maddr="0xd8000"
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# Hint for the i386-only ISA front-end of le(4).
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envvar hint.le.0.at="isa"
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envvar hint.le.0.port="0x280"
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envvar hint.le.0.irq="10"
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envvar hint.le.0.drq="0"
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device sbni
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envvar hint.sbni.0.at="isa"
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envvar hint.sbni.0.port="0x210"
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envvar hint.sbni.0.irq="0xefdead"
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envvar hint.sbni.0.flags="0"
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#####################################################################
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#
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# Miscellaneous hardware:
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#
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# smapi: System Management Application Program Interface driver
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device smapi
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#
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# Laptop/Notebook options:
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#
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# See also:
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# apm under `Miscellaneous hardware'
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# above.
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# For older notebooks that signal a powerfail condition (external
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# power supply dropped, or battery state low) by issuing an NMI:
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options POWERFAIL_NMI # make it beep instead of panicing
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#
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# I2C Bus
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#
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# Requires 'device iicbus'.
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#
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# Supported interfaces:
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# glxiic: AMD Geode LX CS5536 System Management Bus
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# pcf: Philips PCF8584 ISA-bus controller
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#
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device glxiic # AMD Geode LX CS5536 System Management Bus
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device pcf
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envvar hint.pcf.0.at="isa"
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envvar hint.pcf.0.port="0x320"
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envvar hint.pcf.0.irq="5"
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#
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# glxsb is a driver for the Security Block in AMD Geode LX processors.
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# Requires 'device crypto'.
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#
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device glxsb # AMD Geode LX Security Block
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#
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# padlock is a driver for the cryptographic functions and RNG in
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# VIA C3, C7, and Eden processors.
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# Requires 'device crypto'.
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#
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device padlock_rng # VIA Padlock RNG
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#####################################################################
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# ABI Emulation
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# Enable (32-bit) a.out binary support
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options COMPAT_AOUT
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#####################################################################
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# VM OPTIONS
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#
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# Set the number of PV entries per process. Increasing this can
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# stop panics related to heavy use of shared memory. However, that can
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# (combined with large amounts of physical memory) cause panics at
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# boot time due the kernel running out of VM space.
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#
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# If you're tweaking this, you might also want to increase the sysctls
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# "vm.v_free_min", "vm.v_free_reserved", and "vm.v_free_target".
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#
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# The value below is the one more than the default.
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#
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options PMAP_SHPGPERPROC=201
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#
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# Number of initial kernel page table pages used for early bootstrap.
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# This number should include enough pages to map the kernel, any
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# modules or other data loaded with the kernel by the loader, and data
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# structures allocated before the VM system is initialized such as the
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# vm_page_t array. Each page table page maps 4MB (2MB with PAE).
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#
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options NKPT=31
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# KSTACK_PAGES is the number of memory pages to assign to the kernel
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# stack of each thread.
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options KSTACK_PAGES=5
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# Enable detailed accounting by the PV entry allocator.
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options PV_STATS
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#####################################################################
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# Items broken on i386 that are generally available elsewhere
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# Device uses bus_read_8 and friends, so can't work. Remove it from lint.
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nodevice bnxt
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