Multiple issues existed within the powerpc FP/VSX save/restore functionality,
leading to register corruption and loss of register contents in specific
scenarios involving high signal load and use of both floating point and VSX
instructions.
Issue #1
On little endian systems the PCB used the wrong location for the shadowed
FP register within the larger VSX register. This appears to have been an
attempt to correct issue #2 without understanding how the vector load/store
instructions actually operate.
Issue #2
On little endian systems, the VSX state save/restore routines swapped 32-bit
words within the 64-bit aliased double word for the associated floating point
register. This was due to the use of a word-oriented load/store vs. doubleword
oriented load/store.
Issue #3
The FPU was turned off in the PCB but not in hardware, leading to a potential
race condition if the same thread was scheduled immediately after sigreturn.
The triggering codebase for this is Go, which makes heavy use of signals and
and generates an unusual mix of floating point and VSX assembler. As a result,
when combined with th powerpc lazy FPU restore, a condition was repeatedly hit
whereby the thread was interrupted in FP+VSX mode, then restored in FP only
mode, thus reliably triggering the issues above.
Also clean up the associated asm() style issue flagged by GitHub Actions.
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
MFC after: 1 week
Pull Request: https://github.com/freebsd/freebsd-src/pull/1756
Timothy Pearson
077e30e61d