Adrian Chadd
4e3fdced7f
* migrate the MSM8916 (snapdragon 410) support to qcom_gcc * add the full qcom_gcc / qcom_clk list to files.arm64, replacing the MSM8916 stub in sys/arm64/qualcomm . Differential Revision: https://reviews.freebsd.org/D49706
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __QCOM_GCC_VAR_H__
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#define __QCOM_GCC_VAR_H__
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typedef enum {
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QCOM_GCC_CHIPSET_NONE = 0,
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QCOM_GCC_CHIPSET_IPQ4018 = 1,
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QCOM_GCC_CHIPSET_MSM8916 = 2,
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} qcom_gcc_chipset_t;
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struct qcom_gcc_reset_entry {
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uint32_t reg;
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uint32_t bit;
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};
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struct qcom_gcc_hw_callbacks {
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/* Reset block */
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int (*hw_reset_assert)(device_t, intptr_t, bool);
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int (*hw_reset_is_asserted)(device_t, intptr_t, bool *);
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/* Clock block */
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};
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struct qcom_gcc_softc {
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device_t dev;
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int reg_rid;
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struct resource *reg;
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struct mtx mtx;
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struct clkdom *clkdom;
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qcom_gcc_chipset_t sc_chipset;
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struct qcom_gcc_hw_callbacks sc_cb;
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};
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/*
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* reset block
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*/
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extern int qcom_gcc_hwreset_assert(device_t dev, intptr_t id,
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bool reset);
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extern int qcom_gcc_hwreset_is_asserted(device_t dev, intptr_t id,
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bool *reset);
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/*
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* clock block
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*/
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extern int qcom_gcc_clock_read(device_t dev, bus_addr_t addr,
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uint32_t *val);
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extern int qcom_gcc_clock_write(device_t dev, bus_addr_t addr,
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uint32_t val);
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extern int qcom_gcc_clock_modify(device_t dev, bus_addr_t addr,
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uint32_t clear_mask, uint32_t set_mask);
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extern void qcom_gcc_clock_setup(struct qcom_gcc_softc *sc);
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extern void qcom_gcc_clock_lock(device_t dev);
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extern void qcom_gcc_clock_unlock(device_t dev);
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#endif /* __QCOM_GCC_VAR_H__ */
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