Brad Smith
3f3cc6fd69
e574c2d36cbcacf2556088879be336775e80154b Add support for RTL8125D revision 0x6890000 Reviewed by: adrian Differential Revision: https://reviews.freebsd.org/D54922 MFC after: 2 weeks
272 lines
7.4 KiB
C
272 lines
7.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019, 2020, 2025 Kevin Lo <kevlo@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/* $OpenBSD: if_rgereg.h,v 1.15 2025/09/19 00:41:14 kevlo Exp $ */
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#ifndef __IF_RGEVAR_H__
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#define __IF_RGEVAR_H__
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#define RGE_LOCK(sc) (mtx_lock(&sc->sc_mtx))
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#define RGE_UNLOCK(sc) (mtx_unlock(&sc->sc_mtx))
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#define RGE_ASSERT_LOCKED(sc) (mtx_assert(&sc->sc_mtx, MA_OWNED))
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#define RGE_ASSERT_UNLOCKED(sc) (mtx_assert(&sc->sc_mtx, MA_NOTOWNED))
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enum rge_mac_type {
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MAC_UNKNOWN = 1,
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MAC_R25,
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MAC_R25B,
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MAC_R25D_1,
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MAC_R25D_2,
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MAC_R26_1,
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MAC_R26_2,
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MAC_R27
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};
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struct rge_drv_stats {
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/* How many times if_transmit() was called */
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uint64_t transmit_call_cnt;
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/* Transmitted frame failed because the interface was stopped */
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uint64_t transmit_stopped_cnt;
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/* Transmitted frame failed because the TX queue is full */
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uint64_t transmit_full_cnt;
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/* How many transmit frames were queued for transmit */
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uint64_t transmit_queued_cnt;
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/* How many times the interrupt routine was called */
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uint64_t intr_cnt;
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/* How many times SYSTEM_ERR was set, requiring a hardware reset */
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uint64_t intr_system_err_cnt;
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/* How many times rge_rxeof was called */
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uint64_t rxeof_cnt;
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/* How many times rge_txeof was called */
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uint64_t txeof_cnt;
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/* How many times the link state changed */
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uint64_t link_state_change_cnt;
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/* How many times tx_task was run */
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uint64_t tx_task_cnt;
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/* Count of frames passed up into if_input() */
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uint64_t recv_input_cnt;
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/*
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* For now - driver doesn't support multi descriptor
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* RX frames; so count if it happens so it'll be noticed.
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*/
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uint64_t rx_desc_err_multidesc;
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/*
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* Number of TX watchdog timeouts.
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*/
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uint64_t tx_watchdog_timeout_cnt;
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uint64_t tx_encap_cnt;
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uint64_t tx_encap_refrag_cnt;
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uint64_t tx_encap_err_toofrag;
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uint64_t tx_offload_ip_csum_set;
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uint64_t tx_offload_tcp_csum_set;
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uint64_t tx_offload_udp_csum_set;
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uint64_t tx_offload_vlan_tag_set;
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uint64_t rx_ether_csum_err;
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uint64_t rx_desc_jumbo_frag;
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uint64_t rx_offload_vlan_tag;
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uint64_t rx_offload_csum_ipv4_exists;
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uint64_t rx_offload_csum_ipv4_valid;
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uint64_t rx_offload_csum_tcp_exists;
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uint64_t rx_offload_csum_tcp_valid;
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uint64_t rx_offload_csum_udp_exists;
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uint64_t rx_offload_csum_udp_valid;
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};
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struct rge_txq {
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struct mbuf *txq_mbuf;
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bus_dmamap_t txq_dmamap;
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int txq_descidx;
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};
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struct rge_rxq {
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struct mbuf *rxq_mbuf;
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bus_dmamap_t rxq_dmamap;
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};
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struct rge_tx {
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struct rge_txq rge_txq[RGE_TX_LIST_CNT];
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int rge_txq_prodidx;
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int rge_txq_considx;
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bus_addr_t rge_tx_list_paddr;
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bus_dmamap_t rge_tx_list_map;
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struct rge_tx_desc *rge_tx_list;
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};
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struct rge_rx {
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struct rge_rxq rge_rxq[RGE_RX_LIST_CNT];
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int rge_rxq_prodidx;
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int rge_rxq_considx;
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// struct if_rxring rge_rx_ring;
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bus_addr_t rge_rx_list_paddr;
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bus_dmamap_t rge_rx_list_map;
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struct rge_rx_desc *rge_rx_list;
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struct mbuf *rge_head;
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struct mbuf **rge_tail;
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};
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struct rge_queues {
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struct rge_softc *q_sc;
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void *q_ihc;
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int q_index;
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char q_name[16];
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// pci_intr_handle_t q_ih;
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struct rge_tx q_tx;
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struct rge_rx q_rx;
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};
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struct rge_mac_stats {
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bus_addr_t paddr;
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bus_dmamap_t map;
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/* NIC dma buffer, NIC order */
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struct rge_hw_mac_stats *stats;
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/* Local copy for retrieval, host order */
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struct rge_hw_mac_stats lcl_stats;
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};
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struct rge_softc {
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device_t sc_dev;
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if_t sc_ifp; /* Ethernet common data */
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bool sc_ether_attached;
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struct mtx sc_mtx;
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struct resource *sc_irq[RGE_MSI_MESSAGES];
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void *sc_ih[RGE_MSI_MESSAGES];
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uint32_t sc_expcap; /* PCe exp cap */
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struct resource *sc_bres; /* bus space MMIO/IOPORT resource */
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bus_space_handle_t rge_bhandle; /* bus space handle */
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bus_space_tag_t rge_btag; /* bus space tag */
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bus_size_t rge_bsize;
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bus_dma_tag_t sc_dmat;
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bus_dma_tag_t sc_dmat_tx_desc;
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bus_dma_tag_t sc_dmat_tx_buf;
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bus_dma_tag_t sc_dmat_rx_desc;
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bus_dma_tag_t sc_dmat_rx_buf;
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bus_dma_tag_t sc_dmat_stats_buf;
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// pci_chipset_tag_t sc_pc;
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// pcitag_t sc_tag;
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struct ifmedia sc_media; /* media info */
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enum rge_mac_type rge_type;
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struct rge_queues *sc_queues;
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unsigned int sc_nqueues;
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bool sc_detaching;
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bool sc_stopped;
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bool sc_suspended;
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/* Note: these likely should be per-TXQ */
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struct mbufq sc_txq;
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struct taskqueue * sc_tq;
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char sc_tq_name[32];
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char sc_tq_thr_name[32];
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struct task sc_tx_task;
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struct callout sc_timeout; /* 1 second tick */
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uint64_t rge_mcodever;
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uint16_t rge_rcodever;
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uint32_t rge_flags;
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#define RGE_FLAG_MSI 0x00000001
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#define RGE_FLAG_PCIE 0x00000002
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uint32_t rge_intrs;
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int rge_timerintr;
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#define RGE_IMTYPE_NONE 0
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#define RGE_IMTYPE_SIM 1
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int sc_watchdog;
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uint32_t sc_debug;
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struct rge_drv_stats sc_drv_stats;
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struct rge_mac_stats sc_mac_stats;
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};
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/*
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* Register space access macros.
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*/
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#define RGE_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val)
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#define RGE_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val)
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#define RGE_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val)
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#define RGE_WRITE_BARRIER_4(sc, reg) \
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bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4, \
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BUS_SPACE_BARRIER_WRITE)
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#define RGE_READ_BARRIER_4(sc, reg) \
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bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4, \
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BUS_SPACE_BARRIER_READ)
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#define RGE_READ_4(sc, reg) \
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bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg)
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#define RGE_READ_2(sc, reg) \
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bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg)
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#define RGE_READ_1(sc, reg) \
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bus_space_read_1(sc->rge_btag, sc->rge_bhandle, reg)
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#define RGE_SETBIT_4(sc, reg, val) \
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RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val))
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#define RGE_SETBIT_2(sc, reg, val) \
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RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val))
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#define RGE_SETBIT_1(sc, reg, val) \
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RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val))
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#define RGE_CLRBIT_4(sc, reg, val) \
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RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val))
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#define RGE_CLRBIT_2(sc, reg, val) \
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RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val))
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#define RGE_CLRBIT_1(sc, reg, val) \
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RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val))
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#define RGE_EPHY_SETBIT(sc, reg, val) \
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rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val))
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#define RGE_EPHY_CLRBIT(sc, reg, val) \
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rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val))
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#define RGE_PHY_SETBIT(sc, reg, val) \
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rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val))
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#define RGE_PHY_CLRBIT(sc, reg, val) \
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rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val))
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#define RGE_MAC_SETBIT(sc, reg, val) \
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rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val))
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#define RGE_MAC_CLRBIT(sc, reg, val) \
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rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val))
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#endif /* __IF_RGEVAR_H__ */
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