Andre Silva
0aa4c25f3e
Add kernel and userland support for Zen6 IBS extensions per AMD pub 69205 (rev 1.00, March 2026): alternate fetch/op disable via ctl2[0], fetch latency filtering, virtual address bit 63 filtering, and streaming-store filtering. Decode the new IbsOpData2 StrmSt and RmtSocket bits. Update libpmc, pmcstat and manpage. Pre-Zen6 systems work unchanged with ibs_ctl2 == 0. Signed-off-by: Andre Silva <andasilv@amd.com> Reviewed by: Ali Mashtizadeh <ali@mashtizadeh.com>, mhorne Sponsored by: AMD Differential Revision: https://reviews.freebsd.org/D56914
225 lines
6.8 KiB
Plaintext
225 lines
6.8 KiB
Plaintext
.\"
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.\" SPDX-License-Identifier: BSD-2-Clause
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.\"
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.\" Copyright (c) 2026, Netflix, Inc.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.Dd March 15, 2026
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.Dt PMC.IBS 3
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.Os
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.Sh NAME
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.Nm pmc.ibs
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.Nd Instruction Based Sampling for
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.Tn AMD
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CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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AMD Instruction Based Sampling (IBS) was introduced with the K10 family of
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CPUs.
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AMD IBS is an alternative approach that samples instructions or micro-ops and
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provides a per-instruction or micro-op breakdown of the sources of stalls.
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.Pp
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Unlike traditional counters, IBS can only be used in the sampling mode and
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provides extra data embedded in the callchain.
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IBS events set the PMC_F_MULTIPART flag to signify multiple payload types are
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contained in the callchain.
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The first 8 bytes of the callchain contain four tuples with a one byte type and
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a one byte length field.
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The regular PMC callchain can be found following the multipart payload.
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.Pp
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IBS only provides two events that analyze instruction fetches and instruction
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execution.
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The instruction fetch (ibs-fetch) event provides data on the processor
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front-end including reporting instruction cache and TLB events.
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The instruction execution (ibs-op) event provides data on the processor
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execution including reporting mispredictions, data cache and TLB events.
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You should use the AMD PMC counters documented in
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.Xr pmc.amd 3
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to analyze stalls relating instruction issue including reservation contention.
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.Pp
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A guide to analyzing IBS data is provided in Appendix G of the
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.Rs
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.%B "Software Optimization Guide for AMD Family 10h and 12h Processors"
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.%N "Publication No. 40546"
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.%D "February 2011"
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.%Q "Advanced Micro Devices, Inc."
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.Re
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A more recent document should be used for decoding all of the flags and fields
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in the IBS data.
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For example, see the AMD Zen 5 documentation
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.Rs
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.%B "Processor Programming Reference (PPR) for AMD Family 1Ah Model 02h"
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.%N "Publication No. 57238"
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.%D "March 6, 2026"
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.%Q "Advanced Micro Devices, Inc."
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.Re
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.Ss PMC Features
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AMD IBS supports the following capabilities.
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta Yes
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.It PMC_CAP_INVERT Ta \&No
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.It PMC_CAP_READ Ta \&No
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.It PMC_CAP_PRECISE Ta Yes
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.It PMC_CAP_SYSTEM Ta Yes
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta \&No
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.It PMC_CAP_USER Ta Yes (Zen 6)
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.It PMC_CAP_WRITE Ta \&No
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.El
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.Pp
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By default AMD IBS enables the edge, interrupt, system and precise flags.
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.Ss Event Qualifiers
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Event specifiers for AMD IBS can have the following optional
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qualifiers:
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.Bl -tag -width "fetchlat=value"
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.It Li usr
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Valid for both
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.Ar ibs-fetch
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and
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.Ar ibs-op
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events.
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Configure the counter to only sample user-mode events.
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Requires Zen 6 IBS extensions
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.Pq CPUID Fn Fn8000_0001B
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.Va EAX[IbsAddrBit63Filtering] ,
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and is rejected when the CPU does not advertise support.
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.It Li os
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Valid for both
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.Ar ibs-fetch
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and
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.Ar ibs-op
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events.
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Configure the counter to only sample kernel-mode events.
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Requires Zen 6 IBS extensions
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.Pq CPUID Fn Fn8000_0001B
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.Va EAX[IbsAddrBit63Filtering] ,
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and is rejected when the CPU does not advertise support.
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.It Li fetchlat= Ns Ar value
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Valid only for
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.Ar ibs-fetch
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events.
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Configure the counter to only sample fetches whose latency is greater than or
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equal to
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.Ar value
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core clock cycles.
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The valid range is 128 to 1920 in steps of 128.
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Requires Zen 6 IBS extensions
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.Pq CPUID Fn Fn8000_0001B
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.Va EAX[IbsFetchLatencyFiltering] ,
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and is rejected when the CPU does not advertise support.
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.It Li l3miss
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Valid for both
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.Ar ibs-fetch
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and
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.Ar ibs-op
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events.
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Configure IBS to only sample if an l3miss occurred.
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.It Li ldlat= Ns Ar value
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Valid only for
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.Ar ibs-op
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events.
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Configure the counter to only sample events with load latencies above
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.Ar ldlat .
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IBS only supports filtering latencies that are a multiple of 128 and between
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128 and 2048.
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On pre-Zen 6 hardware this qualifier implies the
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.Li l3miss
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qualifier; on Zen 6 and later, latency-only filtering without
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.Li l3miss
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is permitted.
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.It Li opcount
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Valid only for
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.Ar ibs-op
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events.
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Count ops rather than cycles.
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.It Li randomize
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Valid only for
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.Ar ibs-fetch
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events.
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Randomize the sampling rate.
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.It Li streamstore
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Valid only for
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.Ar ibs-op
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events.
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Configure the counter to only sample streaming
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.Pq non-temporal
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store operations.
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Requires Zen 6 IBS extensions
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.Pq CPUID Fn Fn8000_0001B
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.Va EAX[IbsStrmStAndRmtSocket] ,
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and is rejected when the CPU does not advertise support.
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.El
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.Ss AMD IBS Events Specifiers
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The IBS event class provides only two event specifiers:
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.Bl -tag -width indent
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.It Li ibs-fetch Xo
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.Op ,usr
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.Op ,os
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.Op ,fetchlat= Ns Ar value
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.Op ,l3miss
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.Op ,randomize
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.Xc
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Collect performance samples during instruction fetch.
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The
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.Ar randomize
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qualifier randomly sets the bottom four bits of the sample rate.
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.It Li ibs-op Xo
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.Op ,usr
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.Op ,os
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.Op ,l3miss
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.Op ,ldlat= Ns Ar ldlat
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.Op ,opcount
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.Op ,streamstore
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.Xc
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Collect performance samples during instruction execution.
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The
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.Ar opcount
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qualifier, upon reaching the maximum count, restarts the count with a random
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value between 1 and 127.
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.El
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.Pp
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You may collect both events at the same time.
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N.B. AMD discouraged doing so with certain older processors, stating that
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sampling both simultaneously perturbs the results.
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Please see the processor programming reference for your specific processor.
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.Sh SEE ALSO
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.Xr pmc 3 ,
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.Xr pmc.amd 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmclog 3 ,
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.Xr hwpmc 4
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.Sh HISTORY
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AMD IBS support was first introduced in
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.Fx 16.0 .
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.Sh AUTHORS
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AMD IBS support and this manual page were written
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.An Ali Mashtizadeh Aq Mt ali@mashtizadeh.com
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and sponsored by Netflix, Inc.
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