diff --git a/lib/msun/aarch64/fenv.c b/lib/msun/aarch64/fenv.c
index cce9f33e4f3..4c54656be7d 100644
--- a/lib/msun/aarch64/fenv.c
+++ b/lib/msun/aarch64/fenv.c
@@ -38,7 +38,12 @@ const fenv_t __fe_dfl_env = 0;
 #error "This file must be compiled with C99 'inline' semantics"
 #endif
 
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+	return (__feclearexcept_int(excepts));
+}
+
 extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
 extern inline int feraiseexcept(int __excepts);
diff --git a/lib/msun/aarch64/fenv.h b/lib/msun/aarch64/fenv.h
index a435a9de522..d125978b887 100644
--- a/lib/msun/aarch64/fenv.h
+++ b/lib/msun/aarch64/fenv.h
@@ -81,8 +81,11 @@ extern const fenv_t	__fe_dfl_env;
 #define	__mrs_fpsr(__r)	__asm __volatile("mrs %0, fpsr" : "=r" (__r))
 #define	__msr_fpsr(__r)	__asm __volatile("msr fpsr, %0" : : "r" (__r))
 
-__fenv_static __inline int
-feclearexcept(int __excepts)
+int feclearexcept(int);
+#define	feclearexcept(a)	__feclearexcept_int(a)
+
+__fenv_static inline int
+__feclearexcept_int(int __excepts)
 {
 	fexcept_t __r;
 
diff --git a/lib/msun/amd64/fenv.c b/lib/msun/amd64/fenv.c
index 4d271f8d456..cd3b83d1158 100644
--- a/lib/msun/amd64/fenv.c
+++ b/lib/msun/amd64/fenv.c
@@ -46,7 +46,12 @@ const fenv_t __fe_dfl_env = {
 	__INITIAL_MXCSR__
 };
 
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+	return (__feclearexcept_int(excepts));
+}
+
 extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 
 int
diff --git a/lib/msun/arm/fenv.c b/lib/msun/arm/fenv.c
index 05b3adb05f8..c8edf3fef03 100644
--- a/lib/msun/arm/fenv.c
+++ b/lib/msun/arm/fenv.c
@@ -70,7 +70,12 @@ const fenv_t __fe_dfl_env = 0;
 #error "This file must be compiled with C99 'inline' semantics"
 #endif
 
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+	return (__feclearexcept_int(excepts));
+}
+
 extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
 extern inline int feraiseexcept(int __excepts);
diff --git a/lib/msun/arm/fenv.h b/lib/msun/arm/fenv.h
index e8a30fcf496..14638dd33aa 100644
--- a/lib/msun/arm/fenv.h
+++ b/lib/msun/arm/fenv.h
@@ -111,8 +111,11 @@ int fegetexcept(void);
 
 #define _FPU_MASK_SHIFT	8
 
+int feclearexcept(int);
+#define	feclearexcept(a)	__feclearexcept_int(a)
+
 __fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
 {
 	fexcept_t __fpsr;
 
diff --git a/lib/msun/i387/fenv.c b/lib/msun/i387/fenv.c
index ebb4111a5fa..e0485a3597f 100644
--- a/lib/msun/i387/fenv.c
+++ b/lib/msun/i387/fenv.c
@@ -88,7 +88,12 @@ __test_sse(void)
 	return (0);
 }
 
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+	return (__feclearexcept_int(excepts));
+}
+
 extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 
 int
diff --git a/lib/msun/powerpc/fenv.c b/lib/msun/powerpc/fenv.c
index cc0b518bb7c..bcf78d5c096 100644
--- a/lib/msun/powerpc/fenv.c
+++ b/lib/msun/powerpc/fenv.c
@@ -35,7 +35,12 @@
 
 const fenv_t __fe_dfl_env = 0x00000000;
 
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+	return (__feclearexcept_int(excepts));
+}
+
 extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
 extern inline int feraiseexcept(int __excepts);
diff --git a/lib/msun/powerpc/fenv.h b/lib/msun/powerpc/fenv.h
index 09fd4caafb4..74a71ef39e5 100644
--- a/lib/msun/powerpc/fenv.h
+++ b/lib/msun/powerpc/fenv.h
@@ -111,8 +111,11 @@ union __fpscr {
 	} __bits;
 };
 
+int feclearexcept(int);
+#define	feclearexcept(a)	__feclearexcept_int(a)
+
 __fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
 {
 	union __fpscr __r;
 
diff --git a/lib/msun/riscv/fenv.c b/lib/msun/riscv/fenv.c
index a4dde02a6dd..4d1b2cb2f61 100644
--- a/lib/msun/riscv/fenv.c
+++ b/lib/msun/riscv/fenv.c
@@ -37,7 +37,12 @@
  */
 const fenv_t __fe_dfl_env = 0;
 
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+	return (__feclearexcept_int(excepts));
+}
+
 extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
 extern inline int feraiseexcept(int __excepts);
diff --git a/lib/msun/riscv/fenv.h b/lib/msun/riscv/fenv.h
index fd50463d479..4e8f81aa04c 100644
--- a/lib/msun/riscv/fenv.h
+++ b/lib/msun/riscv/fenv.h
@@ -79,8 +79,11 @@ extern const fenv_t	__fe_dfl_env;
 #define	__rfs(__fcsr)	__asm __volatile("csrr %0, fcsr" : "=r" (__fcsr))
 #define	__wfs(__fcsr)	__asm __volatile("csrw fcsr, %0" :: "r" (__fcsr))
 
+int feclearexcept(int);
+#define	feclearexcept(a)	__feclearexcept_int(a)
+
 __fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
 {
 
 	__asm __volatile("csrc fflags, %0" :: "r"(__excepts));
diff --git a/lib/msun/x86/fenv.h b/lib/msun/x86/fenv.h
index e558d037236..b806222e5ef 100644
--- a/lib/msun/x86/fenv.h
+++ b/lib/msun/x86/fenv.h
@@ -143,6 +143,9 @@ fegetexcept(void)
 
 #endif /* __BSD_VISIBLE */
 
+int feclearexcept(int);
+#define	feclearexcept(a)	__feclearexcept_int(a)
+
 #ifdef __i386__
 
 /* After testing for SSE support once, we cache the result in __has_sse. */
@@ -164,7 +167,7 @@ int __test_sse(void);
 } while (0)
 
 __fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
 {
 	fenv_t __env;
 	__uint32_t __mxcsr;
@@ -262,7 +265,7 @@ fesetenv(const fenv_t *__envp)
 #else /* __amd64__ */
 
 __fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
 {
 	fenv_t __env;