From e31b1dc89407bfc0e6855055b29eee05eff01c8e Mon Sep 17 00:00:00 2001 From: Sean Bruno Date: Thu, 8 Jan 2015 16:50:35 +0000 Subject: [PATCH] Update Features2 to display SDBG capability of processor. This is showing up on Haswell-class CPUs From the Intel SDM, "Table 3-20. Feature Information Returned in the ECX Register" 11 | SDBG | A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug. Submitted by: jiashiun@gmail.com Reviewed by: jhb neel MFC after: 2 weeks --- sys/x86/include/specialreg.h | 1 + sys/x86/x86/identcpu.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index e6079e77e79..4d1086eeae6 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -154,6 +154,7 @@ #define CPUID2_TM2 0x00000100 #define CPUID2_SSSE3 0x00000200 #define CPUID2_CNXTID 0x00000400 +#define CPUID2_SDBG 0x00000800 #define CPUID2_FMA 0x00001000 #define CPUID2_CX16 0x00002000 #define CPUID2_XTPR 0x00004000 diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c index bae430a4110..2f10b1a3f50 100644 --- a/sys/x86/x86/identcpu.c +++ b/sys/x86/x86/identcpu.c @@ -781,7 +781,7 @@ printcpuinfo(void) "\011TM2" /* Thermal Monitor 2 */ "\012SSSE3" /* SSSE3 */ "\013CNXT-ID" /* L1 context ID available */ - "\014" + "\014SDBG" /* IA32 silicon debug */ "\015FMA" /* Fused Multiply Add */ "\016CX16" /* CMPXCHG16B Instruction */ "\017xTPR" /* Send Task Priority Messages*/