From d47f5f2886f082281ae6f97dd5fe9440ad31e6d5 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 15 Nov 2022 13:54:49 +0100 Subject: [PATCH] usb/dwc3: Only force USB2 based on the PHY register and IP version We shouldn't force USB2 only based on if we have an external PHY. The internal PHY register tell us what link speed we can acheive and we need to force USB2 only if it cannot do USB3. This is only available after revision 0x290A of the dwc3 IP. Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D37394 Fixed: 1331c0f44b6a ("Add support for RockChip RK356X to DWC3 driver.") Sponsored by: Beckhoff Automation GmbH & Co. KG --- sys/dev/usb/controller/dwc3.c | 19 +++++++++++++------ sys/dev/usb/controller/dwc3.h | 5 +++++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/sys/dev/usb/controller/dwc3.c b/sys/dev/usb/controller/dwc3.c index 40405927685..d5e3b3f50a9 100644 --- a/sys/dev/usb/controller/dwc3.c +++ b/sys/dev/usb/controller/dwc3.c @@ -458,12 +458,19 @@ snps_dwc3_common_attach(device_t dev, bool is_fdt) error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy); if (error == 0 && usb3_phy != NULL) phy_enable(usb3_phy); - else { - reg = DWC3_READ(sc, DWC3_GUCTL1); - if (bootverbose) - device_printf(dev, "Forcing USB2 clock only\n"); - reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; - DWC3_WRITE(sc, DWC3_GUCTL1, reg); + if (sc->snpsversion == DWC3_IP_ID) { + if (sc->snpsrevision >= 0x290A) { + uint32_t hwparams3; + + hwparams3 = DWC3_READ(sc, DWC3_GHWPARAMS3); + if (DWC3_HWPARAMS3_SSPHY(hwparams3) == DWC3_HWPARAMS3_SSPHY_DISABLE) { + reg = DWC3_READ(sc, DWC3_GUCTL1); + if (bootverbose) + device_printf(dev, "Forcing USB2 clock only\n"); + reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + DWC3_WRITE(sc, DWC3_GUCTL1, reg); + } + } } snps_dwc3_configure_phy(sc, node); skip_phys: diff --git a/sys/dev/usb/controller/dwc3.h b/sys/dev/usb/controller/dwc3.h index c6967207220..fd61d1129df 100644 --- a/sys/dev/usb/controller/dwc3.h +++ b/sys/dev/usb/controller/dwc3.h @@ -110,6 +110,11 @@ #define DWC3_GUSB3PIPECTL0_DELAYP1TRANS (1 << 18) #define DWC3_GUSB3PIPECTL0_SUSPENDUSB3 (1 << 17) +#define DWC3_HWPARAMS3_SSPHY(x) (x & 0x3) +#define DWC3_HWPARAMS3_SSPHY_DISABLE 0 +#define DWC3_HWPARAMS3_SSPHY_GEN1 1 +#define DWC3_HWPARAMS3_SSPHY_GEN2 2 + #define DWC3_GTXFIFOSIZ(x) (0xc300 + 0x4 * (x)) #define DWC3_GRXFIFOSIZ(x) (0xc380 + 0x4 * (x)) #define DWC3_GEVNTADRLO0 0xc400