diff --git a/sys/powerpc/aim/mmu_oea64.c b/sys/powerpc/aim/mmu_oea64.c
index 4757e469b5d..c82c5c539de 100644
--- a/sys/powerpc/aim/mmu_oea64.c
+++ b/sys/powerpc/aim/mmu_oea64.c
@@ -125,7 +125,7 @@ uintptr_t moea64_get_unique_vsid(void);
 #define PV_LOCK_COUNT	MAXCPU
 static struct mtx_padalign pv_lock[PV_LOCK_COUNT];
 
-#define	PV_LOCK_SHIFT	HPT_SP_SIZE
+#define	PV_LOCK_SHIFT	HPT_SP_SHIFT
 #define	pa_index(pa)	((pa) >> PV_LOCK_SHIFT)
 
 /*
@@ -890,7 +890,7 @@ moea64_early_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend)
 	int		rm_pavail;
 
 	/* Level 0 reservations consist of 4096 pages (16MB superpage). */
-	vm_level_0_order = 12;
+	vm_level_0_order = VM_LEVEL_0_ORDER_HPT;
 
 #ifndef __powerpc64__
 	/* We don't have a direct map since there is no BAT */
diff --git a/sys/powerpc/include/pte.h b/sys/powerpc/include/pte.h
index ed926f80c87..2e8cdacbe16 100644
--- a/sys/powerpc/include/pte.h
+++ b/sys/powerpc/include/pte.h
@@ -145,10 +145,11 @@ typedef	struct lpte lpte_t;
 #define	LPTE_RO		LPTE_BR
 
 /* HPT superpage definitions */
-#define	HPT_SP_SHIFT		(VM_LEVEL_0_ORDER + PAGE_SHIFT)
+#define	VM_LEVEL_0_ORDER_HPT	12
+#define	HPT_SP_SHIFT		(VM_LEVEL_0_ORDER_HPT + PAGE_SHIFT)
 #define	HPT_SP_SIZE		(1 << HPT_SP_SHIFT)
 #define	HPT_SP_MASK		(HPT_SP_SIZE - 1)
-#define	HPT_SP_PAGES		(1 << VM_LEVEL_0_ORDER)
+#define	HPT_SP_PAGES		(1 << VM_LEVEL_0_ORDER_HPT)
 
 /* POWER ISA 3.0 Radix Table Definitions */
 #define	RPTE_VALID		0x8000000000000000ULL