smartpqi: Update to vendor version 14.4690.0.2008 - 15.2.0.2008
Update to versions: FreeBSD14 14.4690.2008 FreeBSD15 15.2.0.2008 Included in this update are: - Support for new controllers - Add code that utilizes the new BIG_IOCTL_Command_struct and allows the I/O buffer size for a single passthrough ioctl to be stored as a 32 bit integer instead of the original 16 bit integer. - Update occurrences of Microsemi to Microchip - Some format changes including converting comments from C++ to C style, remove instances of /* $FreeBSD$ */, and updating copyright dates. Update to versions: FreeBSD14 14.4690.2008 FreeBSD15 15.2.0.2008 Included in this update are: - Support for new controllers _ Add code that utilizes the new BIG_IOCTL_Command_struct and allows the I/O buffer size for a single passthrough ioctl to be stored as a 32 bit integer instead of the original 16 bit integer. - Update occurrences of Microsemi to Microchip - Some format changes including converting comments from C++ to C style, remove instances of /* $FreeBSD$ */, and updating copyright dates. Reviewed by: imp Approved by: imp MFC after: 1 week Sponsored by: Microchip Technology Inc. Differential Revision: https://reviews.freebsd.org/D54787
This commit is contained in:
@@ -54,7 +54,7 @@ update_sim_properties(struct cam_sim *sim, struct ccb_pathinq *cpi)
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cpi->initiator_id = 255;
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strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN-1);
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cpi->sim_vid[sizeof(cpi->sim_vid)-1] = '\0';
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strncpy(cpi->hba_vid, "Microsemi", HBA_IDLEN-1);
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strncpy(cpi->hba_vid, "Microchip", HBA_IDLEN-1);
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cpi->hba_vid[sizeof(cpi->hba_vid)-1] = '\0';
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strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN-1);
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cpi->dev_name[sizeof(cpi->dev_name)-1] = '\0';
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@@ -122,6 +122,7 @@ struct pqi_ident
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{0x9005, 0x028f, 0x1f51, 0x1044, PQI_HWIF_SRCV, "SmartHBA P6500-8i"},
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{0x9005, 0x028f, 0x1f3f, 0x0610, PQI_HWIF_SRCV, "3SNIC SSSRAID 3S610"},
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{0x9005, 0x028f, 0x207d, 0x4840, PQI_HWIF_SRCV, "HRDT TrustHBA H3100s-8i"},
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{0x9005, 0x028f, 0x207d, 0x4940, PQI_HWIF_SRCV, "HRDT TrustRAID D3102s-8i"},
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/* (SRCx MSCC FVB 24x12G based) */
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{0x9005, 0x028f, 0x103c, 0x1001, PQI_HWIF_SRCV, "MSCC FVB"},
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@@ -151,11 +152,13 @@ struct pqi_ident
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{0x9005, 0x028f, 0x1cf2, 0x0B27, PQI_HWIF_SRCV, "ZTE SmartROC3100 SDPSA/B-18i 4G"},
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{0x9005, 0x028f, 0x1cf2, 0x0B45, PQI_HWIF_SRCV, "ZTE SmartROC3100 SDPSA/B_L-18i 2G"},
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{0x9005, 0x028f, 0x1cf2, 0x5445, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM241-18i 2G"},
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{0x9005, 0x028f, 0x1cf2, 0x544D, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM241B-18i 2G"},
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{0x9005, 0x028f, 0x1cf2, 0x5446, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM242-18i 4G"},
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{0x9005, 0x028f, 0x1cf2, 0x544E, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM242B-18i 4G"},
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{0x9005, 0x028f, 0x1cf2, 0x5451, PQI_HWIF_SRCV, "ZTE SmartROC3100 RS231-8i 2G"},
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{0x9005, 0x028f, 0x1cf2, 0x5452, PQI_HWIF_SRCV, "ZTE SmartROC3100 RS232-8i 4G"},
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{0x9005, 0x028f, 0x1cf2, 0x5449, PQI_HWIF_SRCV, "ZTE SmartROC3100 RS241-18i 2G"},
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{0x9005, 0x028f, 0x1cf2, 0x544A, PQI_HWIF_SRCV, "ZTE SmartROC3100 RS242-18i 4G"},
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{0x9005, 0x028f, 0x1cf2, 0x544D, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM241B-18i 2G"},
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{0x9005, 0x028f, 0x1cf2, 0x544E, PQI_HWIF_SRCV, "ZTE SmartROC3100 RM242B-18i 4G"},
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{0x9005, 0x028f, 0x1bd4, 0x006F, PQI_HWIF_SRCV, "RS0804M5R16i"},
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{0x9005, 0x028f, 0x1ff9, 0x006F, PQI_HWIF_SRCV, "RS0804M5R16i"},
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{0x9005, 0x028f, 0x1f51, 0x1010, PQI_HWIF_SRCV, "SmartRAID P7504N-16i"},
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@@ -178,6 +181,7 @@ struct pqi_ident
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{0x9005, 0x028f, 0x1458, 0x1000, PQI_HWIF_SRCV, "GIGABYTE SmartHBA CLN1832"},
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{0x9005, 0x028f, 0x1cf2, 0x0B29, PQI_HWIF_SRCV, "ZTE SmartIOC2100 SDPSA/B_I-18i"},
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{0x9005, 0x028f, 0x1cf2, 0x5447, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RM243-18i"},
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{0x9005, 0x028f, 0x1cf2, 0x5453, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RS233-8i"},
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{0x9005, 0x028f, 0x1cf2, 0x544B, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RS243-18i"},
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{0x9005, 0x028f, 0x1cf2, 0x544F, PQI_HWIF_SRCV, "ZTE SmartIOC2100 RM243B-18i"},
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{0x9005, 0x028f, 0x1bd4, 0x0071, PQI_HWIF_SRCV, "RS0800M5H16i"},
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@@ -911,9 +911,14 @@ static inline uint64_t CALC_PERCENT_TOTAL(uint64_t val, uint64_t total)
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#define CCISS_GETDRIVVER _IOWR(SMARTPQI_IOCTL_BASE, 0, driver_info)
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#define CCISS_GETPCIINFO _IOWR(SMARTPQI_IOCTL_BASE, 1, pqi_pci_info_t)
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#define SMARTPQI_PASS_THRU _IOWR(SMARTPQI_IOCTL_BASE, 2, IOCTL_Command_struct)
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#define SMARTPQI_BIG_PASS_THRU _IOWR(SMARTPQI_IOCTL_BASE, 3, BIG_IOCTL_Command_struct)
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#define CCISS_PASSTHRU _IOWR('C', 210, IOCTL_Command_struct)
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#define CCISS_REGNEWD _IO(CCISS_IOC_MAGIC, 14)
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#if !defined(SMARTPQI_BIG_PASSTHRU_SUPPORTED)
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#define SMARTPQI_BIG_PASSTHRU_SUPPORTED _IO(SMARTPQI_IOCTL_BASE, 4)
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#endif
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/*IOCTL pci_info structure */
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typedef struct pqi_pci_info
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{
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@@ -939,12 +944,12 @@ typedef uint8_t *passthru_buf_type_t;
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#define PQISRC_DRIVER_MAJOR __FreeBSD__
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#if __FreeBSD__ <= 14
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#define PQISRC_DRIVER_MINOR 4660
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#define PQISRC_DRIVER_MINOR 4690
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#else
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#define PQISRC_DRIVER_MINOR 0
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#define PQISRC_DRIVER_MINOR 2
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#endif
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#define PQISRC_DRIVER_RELEASE 0
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#define PQISRC_DRIVER_REVISION 2002
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#define PQISRC_DRIVER_REVISION 2008
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#define STR(s) # s
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#define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d)
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@@ -417,7 +417,7 @@ pqisrc_report_event_config(pqisrc_softstate_t *softs)
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softs->event_config.num_event_descriptors = MIN(event_config_p->num_event_descriptors,
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PQI_MAX_EVENT_DESCRIPTORS) ;
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for (i = 0; i < softs->event_config.num_event_descriptors; i++) {
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for (i=0; i < softs->event_config.num_event_descriptors; i++) {
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softs->event_config.descriptors[i].event_type =
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event_config_p->descriptors[i].event_type;
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}
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@@ -477,7 +477,7 @@ pqisrc_set_event_config(pqisrc_softstate_t *softs)
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event_config_p->num_event_descriptors = softs->event_config.num_event_descriptors;
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for (i = 0; i < softs->event_config.num_event_descriptors; i++) {
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for (i=0; i < softs->event_config.num_event_descriptors; i++) {
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event_config_p->descriptors[i].event_type =
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softs->event_config.descriptors[i].event_type;
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if( pqisrc_event_type_to_event_index(event_config_p->descriptors[i].event_type) != -1)
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@@ -1,5 +1,5 @@
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/*-
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* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
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* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -333,6 +333,8 @@ check_struct_sizes(void)
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64 bit and 32 bit system*/
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ASSERT(sizeof(IOCTL_Command_struct)== 86 ||
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sizeof(IOCTL_Command_struct)== 82);
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ASSERT(sizeof(BIG_IOCTL_Command_struct)== 88 ||
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sizeof(BIG_IOCTL_Command_struct)== 84);
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ASSERT(sizeof(struct bmic_host_wellness_driver_version)== 44);
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ASSERT(sizeof(struct bmic_host_wellness_time)== 20);
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ASSERT(sizeof(struct pqi_dev_adminq_cap)== 8);
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@@ -386,7 +388,7 @@ void
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check_device_pending_commands_to_complete(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device)
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{
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uint32_t tag = softs->max_outstanding_io, active_requests;
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uint64_t timeout = 0, delay_in_usec = 1000; /* In micro Seconds */
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uint64_t timeout = 0, delay_in_usec = 1000; /* In microseconds */
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rcb_t* rcb;
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DBG_FUNC("IN\n");
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@@ -1,5 +1,5 @@
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/*-
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* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
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* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -1,5 +1,5 @@
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/*-
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* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
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* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -169,6 +169,13 @@ smartpqi_ioctl(struct cdev *cdev, u_long cmd, caddr_t udata,
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pqi_status = pqisrc_passthru_ioctl(softs, udata, 0);
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bsd_status = pqi_status_to_bsd_ioctl_status(pqi_status);
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break;
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case SMARTPQI_BIG_PASS_THRU:
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pqi_status = pqisrc_big_passthru_ioctl(softs, udata, 0);
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bsd_status = pqi_status_to_bsd_ioctl_status(pqi_status);
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break;
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case SMARTPQI_BIG_PASSTHRU_SUPPORTED:
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bsd_status = BSD_SUCCESS;
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break;
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case CCISS_REGNEWD:
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pqi_status = pqisrc_scan_devices(softs);
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bsd_status = pqi_status_to_bsd_ioctl_status(pqi_status);
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@@ -422,3 +429,195 @@ pqisrc_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
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DBG_FUNC("Failed OUT\n");
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return PQI_STATUS_FAILURE;
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}
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/*
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* Function used to send big passthru commands to adapter
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* to support management tools. For eg. ssacli, sscon.
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*/
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int
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pqisrc_big_passthru_ioctl(struct pqisrc_softstate *softs, void *arg, int mode)
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{
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int ret;
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char *drv_buf = NULL;
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uint32_t tag = 0;
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BIG_IOCTL_Command_struct *iocommand = (BIG_IOCTL_Command_struct *)arg;
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dma_mem_t ioctl_dma_buf;
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pqisrc_raid_req_t request;
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raid_path_error_info_elem_t error_info;
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ib_queue_t *ib_q = &softs->op_raid_ib_q[PQI_DEFAULT_IB_QUEUE];
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ob_queue_t const *ob_q = &softs->op_ob_q[PQI_DEFAULT_IB_QUEUE];
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rcb_t *rcb = NULL;
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memset(&request, 0, sizeof(request));
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memset(&error_info, 0, sizeof(error_info));
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DBG_FUNC("IN\n");
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if (pqisrc_ctrl_offline(softs))
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return PQI_STATUS_FAILURE;
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if (!arg)
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return PQI_STATUS_FAILURE;
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if (iocommand->buf_size < 1 &&
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iocommand->Request.Type.Direction != PQIIOCTL_NONE)
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return PQI_STATUS_FAILURE;
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if (iocommand->Request.CDBLen > sizeof(request.cmd.cdb))
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return PQI_STATUS_FAILURE;
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switch (iocommand->Request.Type.Direction) {
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case PQIIOCTL_NONE:
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case PQIIOCTL_WRITE:
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case PQIIOCTL_READ:
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case PQIIOCTL_BIDIRECTIONAL:
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break;
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default:
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return PQI_STATUS_FAILURE;
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}
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if (iocommand->buf_size > 0) {
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memset(&ioctl_dma_buf, 0, sizeof(struct dma_mem));
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os_strlcpy(ioctl_dma_buf.tag, "Ioctl_PassthruCmd_Buffer", sizeof(ioctl_dma_buf.tag));
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ioctl_dma_buf.size = iocommand->buf_size;
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ioctl_dma_buf.align = PQISRC_DEFAULT_DMA_ALIGN;
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/* allocate memory */
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ret = os_dma_mem_alloc(softs, &ioctl_dma_buf);
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if (ret) {
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DBG_ERR("Failed to Allocate dma mem for Ioctl PassthruCmd Buffer : %d\n", ret);
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goto out;
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}
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DBG_IO("ioctl_dma_buf.dma_addr = %p\n",(void*)ioctl_dma_buf.dma_addr);
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DBG_IO("ioctl_dma_buf.virt_addr = %p\n",(void*)ioctl_dma_buf.virt_addr);
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drv_buf = (char *)ioctl_dma_buf.virt_addr;
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if (iocommand->Request.Type.Direction & PQIIOCTL_WRITE) {
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ret = os_copy_from_user(softs, (void *)drv_buf, (void *)iocommand->buf, iocommand->buf_size, mode);
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if (ret != 0) {
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goto free_mem;
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}
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}
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}
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request.header.iu_type = PQI_IU_TYPE_RAID_PATH_IO_REQUEST;
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request.header.iu_length = offsetof(pqisrc_raid_req_t, sg_descriptors[1]) -
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PQI_REQUEST_HEADER_LENGTH;
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memcpy(request.lun_number, iocommand->LUN_info.LunAddrBytes,
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sizeof(request.lun_number));
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memcpy(request.cmd.cdb, iocommand->Request.CDB, iocommand->Request.CDBLen);
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request.additional_cdb_bytes_usage = PQI_ADDITIONAL_CDB_BYTES_0;
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switch (iocommand->Request.Type.Direction) {
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case PQIIOCTL_NONE:
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request.data_direction = SOP_DATA_DIR_NONE;
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break;
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case PQIIOCTL_WRITE:
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request.data_direction = SOP_DATA_DIR_FROM_DEVICE;
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break;
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case PQIIOCTL_READ:
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request.data_direction = SOP_DATA_DIR_TO_DEVICE;
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break;
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case PQIIOCTL_BIDIRECTIONAL:
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request.data_direction = SOP_DATA_DIR_BIDIRECTIONAL;
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break;
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}
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request.task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
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if (iocommand->buf_size > 0) {
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request.buffer_length = iocommand->buf_size;
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request.sg_descriptors[0].addr = ioctl_dma_buf.dma_addr;
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request.sg_descriptors[0].len = iocommand->buf_size;
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request.sg_descriptors[0].flags = SG_FLAG_LAST;
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}
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tag = pqisrc_get_tag(&softs->taglist);
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if (INVALID_ELEM == tag) {
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DBG_ERR("Tag not available\n");
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goto free_mem;
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}
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request.request_id = tag;
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request.response_queue_id = ob_q->q_id;
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request.error_index = request.request_id;
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if (softs->timeout_in_passthrough) {
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request.timeout_in_sec = iocommand->Request.Timeout;
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}
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rcb = &softs->rcb[tag];
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rcb->success_cmp_callback = pqisrc_process_internal_raid_response_success;
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rcb->error_cmp_callback = pqisrc_process_internal_raid_response_error;
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rcb->tag = tag;
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rcb->req_pending = true;
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/* Submit Command */
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ret = pqisrc_submit_cmnd(softs, ib_q, &request);
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if (ret != PQI_STATUS_SUCCESS) {
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DBG_ERR("Unable to submit command\n");
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goto err_out;
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}
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ret = pqisrc_wait_on_condition(softs, rcb, PQISRC_PASSTHROUGH_CMD_TIMEOUT);
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if (ret != PQI_STATUS_SUCCESS) {
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DBG_ERR("Passthru IOCTL cmd timed out !!\n");
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goto err_out;
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}
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memset(&iocommand->error_info, 0, sizeof(iocommand->error_info));
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if (rcb->status) {
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size_t sense_data_length;
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memcpy(&error_info, rcb->error_info, sizeof(error_info));
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iocommand->error_info.ScsiStatus = error_info.status;
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sense_data_length = error_info.sense_data_len;
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if (!sense_data_length)
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sense_data_length = error_info.resp_data_len;
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if (sense_data_length &&
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(sense_data_length > sizeof(error_info.data)))
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sense_data_length = sizeof(error_info.data);
|
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if (sense_data_length) {
|
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if (sense_data_length >
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sizeof(iocommand->error_info.SenseInfo))
|
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sense_data_length =
|
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sizeof(iocommand->error_info.SenseInfo);
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memcpy (iocommand->error_info.SenseInfo,
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error_info.data, sense_data_length);
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iocommand->error_info.SenseLen = sense_data_length;
|
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}
|
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|
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if (error_info.data_out_result == PQI_RAID_DATA_IN_OUT_UNDERFLOW) {
|
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rcb->status = PQI_STATUS_SUCCESS;
|
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}
|
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}
|
||||
|
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if (rcb->status == PQI_STATUS_SUCCESS && iocommand->buf_size > 0 &&
|
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(iocommand->Request.Type.Direction & PQIIOCTL_READ)) {
|
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|
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ret = os_copy_to_user(softs, (void*)iocommand->buf, (void*)drv_buf, iocommand->buf_size, mode);
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if (ret != 0) {
|
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DBG_ERR("Failed to copy the response\n");
|
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goto err_out;
|
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}
|
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}
|
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|
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os_reset_rcb(rcb);
|
||||
pqisrc_put_tag(&softs->taglist, request.request_id);
|
||||
if (iocommand->buf_size > 0)
|
||||
os_dma_mem_free(softs,&ioctl_dma_buf);
|
||||
|
||||
DBG_FUNC("OUT\n");
|
||||
return PQI_STATUS_SUCCESS;
|
||||
|
||||
err_out:
|
||||
os_reset_rcb(rcb);
|
||||
pqisrc_put_tag(&softs->taglist, request.request_id);
|
||||
|
||||
free_mem:
|
||||
if (iocommand->buf_size > 0)
|
||||
os_dma_mem_free(softs, &ioctl_dma_buf);
|
||||
|
||||
out:
|
||||
DBG_FUNC("Failed OUT\n");
|
||||
return PQI_STATUS_FAILURE;
|
||||
}
|
||||
@@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
|
||||
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -137,5 +137,12 @@ typedef struct pqi_ioctl_passthruCmd_struct {
|
||||
|
||||
}OS_ATTRIBUTE_PACKED IOCTL_Command_struct;
|
||||
|
||||
typedef struct _BIG_IOCTL_Command_struct {
|
||||
LUNAddr_struct LUN_info;
|
||||
RequestBlock_struct Request;
|
||||
ErrorInfo_struct error_info;
|
||||
DWORD buf_size; /* size in bytes of the buf */
|
||||
passthru_buf_type_t buf;
|
||||
}OS_ATTRIBUTE_PACKED BIG_IOCTL_Command_struct;
|
||||
|
||||
#endif /* _PQI_IOCTL_H_ */
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
|
||||
|
||||
/*
|
||||
* Driver for the Microsemi Smart storage controllers
|
||||
* Driver for the Microchip Smart storage controllers
|
||||
*/
|
||||
|
||||
#include "smartpqi_includes.h"
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
|
||||
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -251,6 +251,7 @@ int pqisrc_process_task_management_response(pqisrc_softstate_t *,
|
||||
|
||||
/* smartpqi_ioctl.c*/
|
||||
int pqisrc_passthru_ioctl(struct pqisrc_softstate *, void *, int);
|
||||
int pqisrc_big_passthru_ioctl(struct pqisrc_softstate *, void *, int);
|
||||
|
||||
/* Functions Prototypes */
|
||||
/* smartpqi_mem.c */
|
||||
|
||||
@@ -688,7 +688,7 @@ pqisrc_create_op_obq(pqisrc_softstate_t *softs,
|
||||
int i = 0;
|
||||
DBG_WARN("Error Status Descriptors\n");
|
||||
for (i = 0; i < 4; i++)
|
||||
DBG_WARN(" %x ",admin_resp.resp_type.create_op_oq.status_desc[i]);
|
||||
DBG_WARN(" %x\n",admin_resp.resp_type.create_op_oq.status_desc[i]);
|
||||
}
|
||||
|
||||
DBG_FUNC("OUT ret : %d\n", ret);
|
||||
@@ -731,7 +731,7 @@ pqisrc_create_op_ibq(pqisrc_softstate_t *softs,
|
||||
int i = 0;
|
||||
DBG_WARN("Error Status Decsriptors\n");
|
||||
for (i = 0; i < 4; i++)
|
||||
DBG_WARN(" %x ",admin_resp.resp_type.create_op_iq.status_desc[i]);
|
||||
DBG_WARN(" %x\n",admin_resp.resp_type.create_op_iq.status_desc[i]);
|
||||
}
|
||||
|
||||
DBG_FUNC("OUT ret : %d\n", ret);
|
||||
|
||||
@@ -1180,7 +1180,7 @@ fill_lba_for_scsi_rw(pqisrc_softstate_t *softs, uint8_t *cdb, aio_req_locator_t
|
||||
|
||||
|
||||
/* determine whether writes to certain types of RAID are supported. */
|
||||
static inline boolean_t
|
||||
static boolean_t
|
||||
pqisrc_is_supported_write(pqisrc_softstate_t const *softs,
|
||||
pqi_scsi_dev_t const *device)
|
||||
{
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* Copyright 2016-2023 Microchip Technology, Inc. and/or its subsidiaries.
|
||||
* Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
Reference in New Issue
Block a user