diff --git a/sys/powerpc/include/openpicvar.h b/sys/powerpc/include/openpicvar.h
index 4f086f809f0..2aca4b38e84 100644
--- a/sys/powerpc/include/openpicvar.h
+++ b/sys/powerpc/include/openpicvar.h
@@ -36,6 +36,7 @@
 
 #define	OPENPIC_QUIRK_SINGLE_BIND	1	/* Bind interrupts to only 1 CPU */
 #define	OPENPIC_QUIRK_HIDDEN_IRQS	2	/* May have IRQs beyond FRR[NIRQ] */
+#define	OPENPIC_QUIRK_WHOAMI_WORKS	4	/* WHOAMI register is present */
 
 /* Names match the macros in openpicreg.h. */
 struct openpic_timer {
diff --git a/sys/powerpc/ofw/openpic_ofw.c b/sys/powerpc/ofw/openpic_ofw.c
index 4083e9eba74..48e2038f2f5 100644
--- a/sys/powerpc/ofw/openpic_ofw.c
+++ b/sys/powerpc/ofw/openpic_ofw.c
@@ -125,6 +125,7 @@ openpic_ofw_attach(device_t dev)
 	if (ofw_bus_is_compatible(dev, "fsl,mpic")) {
 		sc->sc_quirks = OPENPIC_QUIRK_SINGLE_BIND;
 		sc->sc_quirks |= OPENPIC_QUIRK_HIDDEN_IRQS;
+		sc->sc_quirks |= OPENPIC_QUIRK_WHOAMI_WORKS;
 	}
 
 	return (openpic_common_attach(dev, xref));
diff --git a/sys/powerpc/powerpc/openpic.c b/sys/powerpc/powerpc/openpic.c
index 3cb4c544a91..d0c0cc59afe 100644
--- a/sys/powerpc/powerpc/openpic.c
+++ b/sys/powerpc/powerpc/openpic.c
@@ -469,8 +469,23 @@ openpic_ap_init(device_t dev)
 	if (dev != root_pic)
 		return;
 
+	/*
+	 * Not everything implements the full OpenPIC specification.
+	 *
+	 * Notably the CPC945 Bridge and Memory Controller User Manual, which
+	 * is in the PPC 970 (ie Apple G5) CPUs, calls out a set of
+	 * deviations from the specification.  Thus we can't just assume
+	 * WHOAMI is available everywhere.
+	 *
+	 * See 9.5.3.3 - Deviations from the OpenPIC specification.
+	 * Notably - the WhoAmI register is actually 0xF8000050 for all CPUs.
+	 */
+
 	sc = device_get_softc(dev);
-	PCPU_SET(pic, bus_read_4(sc->sc_memr, OPENPIC_WHOAMI));
+	if (sc->sc_quirks & OPENPIC_QUIRK_WHOAMI_WORKS)
+		PCPU_SET(pic, bus_read_4(sc->sc_memr, OPENPIC_WHOAMI));
+	else
+		PCPU_SET(pic, PCPU_GET(cpuid));
 }
 
 static device_method_t openpic_methods[] = {