aq(4): style(9) cleanup

sys/dev/aq/aq_common.h

@@ -68,4 +68,3 @@ do { \
 #define AQ_VER        "0.0.5"
 
 #endif // _AQ_COMMON_H_
-

sys/dev/aq/aq_dbg.c

@@ -56,7 +56,8 @@ const uint32_t dbg_categories_ = dbg_init | dbg_config | dbg_fw;
 
 #define __field(TYPE, VAR) TYPE VAR;
 void
-trace_aq_tx_descr(int ring_idx, unsigned int pointer, volatile uint64_t descr[2])
+trace_aq_tx_descr(int ring_idx, unsigned int pointer,
+    volatile uint64_t descr[2])
 {
 #if AQ_CFG_DEBUG_LVL > 2
 	struct __entry{
@@ -211,7 +212,8 @@ DumpHex(const void* data, size_t size) {
 	for (i = 0; i < size; ++i) {
 		sprintf(buf, "%02X ", ((const unsigned char*)data)[i]);
 		strcat(line, buf);
-		if (((const unsigned char*)data)[i] >= ' ' && ((const unsigned char*)data)[i] <= '~') {
+		if (((const unsigned char*)data)[i] >= ' ' &&
+		    ((const unsigned char*)data)[i] <= '~') {
 			ascii[i % 16] = ((const unsigned char*)data)[i];
 		} else {
 			ascii[i % 16] = '.';

sys/dev/aq/aq_device.h

@@ -147,4 +147,4 @@ void aq_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
 int aq_mediachange(struct ifnet *ifp);
 void aq_if_update_admin_status(if_ctx_t ctx);
 
-#endif
+#endif // _AQ_DEVICE_H_

sys/dev/aq/aq_fw.c

@@ -62,6 +62,7 @@ typedef enum aq_fw_bootloader_mode
 } aq_fw_bootloader_mode;
 
 #define AQ_CFG_HOST_BOOT_DISABLE 0
+
 // Timeouts
 #define RBL_TIMEOUT_MS              10000
 #define MAC_FW_START_TIMEOUT_MS     10000
@@ -215,12 +216,14 @@ mac_soft_reset_flb_(struct aq_hw* hw)
 	int k;
 
 	reg_global_ctl2_set(hw, 0x40e1);
-	// Let Felicity hardware to complete SMBUS transaction before Global software reset.
+	// Let Felicity hardware complete SMBUS transaction before Global
+	// software reset.
 	msec_delay(50);
 
 	/*
-	 * If SPI burst transaction was interrupted(before running the script), global software
-	 * reset may not clear SPI interface. Clean it up manually before global reset.
+	 * If SPI burst transaction was interrupted(before running the script),
+	 * global software reset may not clear SPI interface. Clean it up
+	 * manually before global reset.
 	 */
 	reg_glb_nvr_provisioning2_set(hw, 0xa0);
 	reg_glb_nvr_interface1_set(hw, 0x9f);
@@ -236,8 +239,8 @@ mac_soft_reset_flb_(struct aq_hw* hw)
 		reg_glb_general_provisioning9_set(hw, 1);
 
 	/*
-	 * For the case SPI burst transaction was interrupted (by MCP reset above),
-	 * wait until it is completed by hardware.
+	 * For the case SPI burst transaction was interrupted (by MCP reset
+	 * above), wait until it is completed by hardware.
 	 */
 	msec_delay(50); // Sleep for 10 ms.
 
@@ -263,7 +266,8 @@ mac_soft_reset_flb_(struct aq_hw* hw)
 		trace(dbg_init, "FLB> MAC kickstart done, %d ms", k);
 		/* FW reset */
 		reg_global_ctl2_set(hw, 0x80e0);
-		// Let Felicity hardware complete SMBUS transaction before Global software reset.
+		// Let Felicity hardware complete SMBUS transaction before
+		// Global software reset.
 		msec_delay(50);
 	}
 	reg_glb_cpu_sem_set(hw, 1, 0);

sys/dev/aq/aq_fw1x.c

@@ -171,7 +171,8 @@ fw1x_reset(struct aq_hw* hal)
 	const int retryCount = 1000;
 
 	for (int i = 0; i < retryCount; ++i) {
-		// Read the beginning of Statistics structure to capture the Transaction ID.
+		// Read the beginning of Statistics structure to capture the
+		// Transaction ID.
 		aq_hw_fw_downld_dwords(hal, hal->mbox_addr, (uint32_t*)&mbox,
 		    (uint32_t)((char*)&mbox.stats - (char*)&mbox) / sizeof(uint32_t));
 
@@ -185,7 +186,6 @@ fw1x_reset(struct aq_hw* hal)
 			 * Compare transaction ID to initial value.
 			 * If it's different means f/w is alive. We're done.
 			 */
-
 			return (EOK);
 		}
 
@@ -321,4 +321,3 @@ struct aq_firmware_ops aq_fw1x_ops =
 	.get_mac_addr = fw1x_get_mac_addr,
 	.get_stats = fw1x_get_stats,
 };
-

sys/dev/aq/aq_fw2x.c

@@ -193,7 +193,6 @@ typedef struct fw2x_mailbox // struct fwHostInterface
 #define FW2X_LED_DEFAULT  0x0U
 
 // Firmware v2-3.x specific functions.
-//@{
 int fw2x_reset(struct aq_hw* hw);
 
 int fw2x_set_mode(struct aq_hw* hw, enum aq_hw_fw_mpi_state_e mode,
@@ -203,8 +202,6 @@ int fw2x_get_mode(struct aq_hw* hw, enum aq_hw_fw_mpi_state_e* mode,
 
 int fw2x_get_mac_addr(struct aq_hw* hw, uint8_t* mac);
 int fw2x_get_stats(struct aq_hw* hw, struct aq_hw_stats_s* stats);
-//@}
-
 
 
 static uint64_t
@@ -474,7 +471,7 @@ fw2x_get_stats(struct aq_hw* hw, struct aq_hw_stats_s* stats)
 		return (-ENOTSUP);
 	}
 
-	// Say to F/W to update the statistics
+	// Tell F/W to update the statistics.
 	if (!toggle_mpi_ctrl_and_wait_(hw, FW2X_CAP_STATISTICS, 1, 25)) {
 		trace_error(dbg_fw, "fw2x> statistics update timeout");
 		AQ_DBG_EXIT(-ETIME);

sys/dev/aq/aq_hw.c

@@ -796,9 +796,11 @@ hw_atl_b0_hw_vlan_promisc_set(struct aq_hw_s *self, bool promisc)
 
 
 void
-aq_hw_set_promisc(struct aq_hw_s *self, bool l2_promisc, bool vlan_promisc, bool mc_promisc)
+aq_hw_set_promisc(struct aq_hw_s *self, bool l2_promisc, bool vlan_promisc,
+    bool mc_promisc)
 {
-	AQ_DBG_ENTERA("promisc %d, vlan_promisc %d, allmulti %d", l2_promisc, vlan_promisc, mc_promisc);
+	AQ_DBG_ENTERA("promisc %d, vlan_promisc %d, allmulti %d", l2_promisc,
+	    vlan_promisc, mc_promisc);
 
 	rpfl2promiscuous_mode_en_set(self, l2_promisc);
 
@@ -811,7 +813,8 @@ aq_hw_set_promisc(struct aq_hw_s *self, bool l2_promisc, bool vlan_promisc, bool
 }
 
 int
-aq_hw_rss_hash_set(struct aq_hw_s *self, uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE])
+aq_hw_rss_hash_set(struct aq_hw_s *self,
+    uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE])
 {
 	uint32_t rss_key_dw[HW_ATL_RSS_HASHKEY_SIZE / 4];
 	uint32_t addr = 0U;
@@ -841,7 +844,8 @@ aq_hw_rss_hash_set(struct aq_hw_s *self, uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE
 }
 
 int
-aq_hw_rss_hash_get(struct aq_hw_s *self, uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE])
+aq_hw_rss_hash_get(struct aq_hw_s *self,
+    uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE])
 {
 	uint32_t rss_key_dw[HW_ATL_RSS_HASHKEY_SIZE / 4];
 	uint32_t addr = 0U;
@@ -863,7 +867,8 @@ aq_hw_rss_hash_get(struct aq_hw_s *self, uint8_t rss_key[HW_ATL_RSS_HASHKEY_SIZE
 }
 
 int
-aq_hw_rss_set(struct aq_hw_s *self, uint8_t rss_table[HW_ATL_RSS_INDIRECTION_TABLE_MAX])
+aq_hw_rss_set(struct aq_hw_s *self,
+    uint8_t rss_table[HW_ATL_RSS_INDIRECTION_TABLE_MAX])
 {
 	uint16_t bitary[(HW_ATL_RSS_INDIRECTION_TABLE_MAX *
 					3 / 16U)];

sys/dev/aq/aq_hw.h

@@ -357,4 +357,3 @@ int aq_hw_rss_set(struct aq_hw_s *self, uint8_t rss_table[HW_ATL_RSS_INDIRECTION
 int aq_hw_udp_rss_enable(struct aq_hw_s *self, bool enable);
 
 #endif // _AQ_HW_H_
-

sys/dev/aq/aq_hw_llh.c

@@ -89,7 +89,8 @@ reg_global_ctl2_get(struct aq_hw* hw)
 }
 
 void
-reg_glb_daisy_chain_status1_set(struct aq_hw* hw, uint32_t glb_daisy_chain_status1)
+reg_glb_daisy_chain_status1_set(struct aq_hw* hw,
+    uint32_t glb_daisy_chain_status1)
 {
 	AQ_WRITE_REG(hw, glb_daisy_chain_status1_adr, glb_daisy_chain_status1);
 }
@@ -459,7 +460,8 @@ itr_mif_int_map_en_get(struct aq_hw *aq_hw, uint32_t mif)
 }
 
 void
-itr_mif_int_map_set(struct aq_hw *aq_hw, uint32_t mifInterruptMapping, uint32_t mif)
+itr_mif_int_map_set(struct aq_hw *aq_hw, uint32_t mifInterruptMapping,
+    uint32_t mif)
 {
 	AQ_WRITE_REG_BIT(aq_hw, itrImrMifM_ADR(mif), itrImrMifM_MSK(mif),
 	    itrImrMifM_SHIFT(mif), mifInterruptMapping);
@@ -516,8 +518,8 @@ rdm_rx_dca_mode_set(struct aq_hw *aq_hw, uint32_t rx_dca_mode)
 }
 
 void
-rdm_rx_desc_data_buff_size_set(struct aq_hw *aq_hw, uint32_t rx_desc_data_buff_size,
-    uint32_t descriptor)
+rdm_rx_desc_data_buff_size_set(struct aq_hw *aq_hw,
+    uint32_t rx_desc_data_buff_size, uint32_t descriptor)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rdm_descddata_size_adr(descriptor),
 	    rdm_descddata_size_msk, rdm_descddata_size_shift,
@@ -525,14 +527,16 @@ rdm_rx_desc_data_buff_size_set(struct aq_hw *aq_hw, uint32_t rx_desc_data_buff_s
 }
 
 void
-rdm_rx_desc_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_desc_dca_en, uint32_t dca)
+rdm_rx_desc_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_desc_dca_en,
+    uint32_t dca)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rdm_dcaddesc_en_adr(dca), rdm_dcaddesc_en_msk,
 	    rdm_dcaddesc_en_shift, rx_desc_dca_en);
 }
 
 void
-rdm_rx_desc_en_set(struct aq_hw *aq_hw, uint32_t rx_desc_en, uint32_t descriptor)
+rdm_rx_desc_en_set(struct aq_hw *aq_hw, uint32_t rx_desc_en,
+    uint32_t descriptor)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rdm_descden_adr(descriptor), rdm_descden_msk,
 	    rdm_descden_shift, rx_desc_en);
@@ -564,14 +568,16 @@ rdm_rx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor)
 }
 
 void
-rdm_rx_desc_len_set(struct aq_hw *aq_hw, uint32_t rx_desc_len, uint32_t descriptor)
+rdm_rx_desc_len_set(struct aq_hw *aq_hw, uint32_t rx_desc_len,
+    uint32_t descriptor)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rdm_descdlen_adr(descriptor), rdm_descdlen_msk,
 	    rdm_descdlen_shift, rx_desc_len);
 }
 
 void
-rdm_rx_desc_res_set(struct aq_hw *aq_hw, uint32_t rx_desc_res, uint32_t descriptor)
+rdm_rx_desc_res_set(struct aq_hw *aq_hw, uint32_t rx_desc_res,
+    uint32_t descriptor)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rdm_descdreset_adr(descriptor),
 	    rdm_descdreset_msk, rdm_descdreset_shift, rx_desc_res);
@@ -587,7 +593,8 @@ rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw *aq_hw,
 }
 
 void
-rdm_rx_head_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_head_dca_en, uint32_t dca)
+rdm_rx_head_dca_en_set(struct aq_hw *aq_hw, uint32_t rx_head_dca_en,
+    uint32_t dca)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rdm_dcadhdr_en_adr(dca), rdm_dcadhdr_en_msk,
 	    rdm_dcadhdr_en_shift, rx_head_dca_en);
@@ -960,7 +967,8 @@ rpf_rss_redir_tbl_addr_set(struct aq_hw *aq_hw, uint32_t rss_redir_tbl_addr)
 }
 
 void
-rpf_rss_redir_tbl_wr_data_set(struct aq_hw *aq_hw, uint32_t rss_redir_tbl_wr_data)
+rpf_rss_redir_tbl_wr_data_set(struct aq_hw *aq_hw,
+    uint32_t rss_redir_tbl_wr_data)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rpf_rss_redir_wr_data_adr,
 	    rpf_rss_redir_wr_data_msk, rpf_rss_redir_wr_data_shift,
@@ -1010,7 +1018,8 @@ hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, uint32_t vlan_outer_etht)
 }
 
 void
-hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, uint32_t vlan_prom_mode_en)
+hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
+    uint32_t vlan_prom_mode_en)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
 			    HW_ATL_RPF_VL_PROMIS_MODE_MSK,
@@ -1029,7 +1038,8 @@ hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
 }
 
 void
-hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, uint32_t vlan_untagged_act)
+hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
+    uint32_t vlan_untagged_act)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
 			    HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
@@ -1038,7 +1048,8 @@ hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, uint32_t vlan_untagged_a
 }
 
 void
-hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, uint32_t vlan_flr_en, uint32_t filter)
+hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, uint32_t vlan_flr_en,
+    uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
 			    HW_ATL_RPF_VL_EN_F_MSK,
@@ -1047,7 +1058,8 @@ hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, uint32_t vlan_flr_en, uint32_t
 }
 
 void
-hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, uint32_t vlan_flr_act, uint32_t filter)
+hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, uint32_t vlan_flr_act,
+    uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
 			    HW_ATL_RPF_VL_ACT_F_MSK,
@@ -1056,7 +1068,8 @@ hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, uint32_t vlan_flr_act, uint32
 }
 
 void
-hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_id_flr, uint32_t filter)
+hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_id_flr,
+    uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
 			    HW_ATL_RPF_VL_ID_F_MSK,
@@ -1075,7 +1088,8 @@ hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_rxq_en,
 }
 
 void
-hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_rxq, uint32_t filter)
+hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_rxq,
+    uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),
 			    HW_ATL_RPF_VL_RXQ_F_MSK,
@@ -1084,7 +1098,8 @@ hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, uint32_t vlan_rxq, uint32_t f
 };
 
 void
-hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, uint32_t etht_flr_en, uint32_t filter)
+hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, uint32_t etht_flr_en,
+    uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
 			    HW_ATL_RPF_ET_ENF_MSK,
@@ -1101,8 +1116,8 @@ hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
 }
 
 void
-hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, uint32_t etht_rx_queue_en,
-    uint32_t filter)
+hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
+    uint32_t etht_rx_queue_en, uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
 			    HW_ATL_RPF_ET_RXQFEN_MSK,
@@ -1111,8 +1126,8 @@ hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, uint32_t etht_rx_queue_en
 }
 
 void
-hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, uint32_t etht_user_priority,
-    uint32_t filter)
+hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
+    uint32_t etht_user_priority, uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
 			    HW_ATL_RPF_ET_UPF_MSK,
@@ -1148,7 +1163,8 @@ hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, uint32_t etht_flr_act,
 }
 
 void
-hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, uint32_t etht_flr, uint32_t filter)
+hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, uint32_t etht_flr,
+    uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
 			    HW_ATL_RPF_ET_VALF_MSK,
@@ -1220,7 +1236,8 @@ hw_atl_rpf_l3_arpf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter)
 }
 
 void
-hw_atl_rpf_l3_l4_rxqf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter)
+hw_atl_rpf_l3_l4_rxqf_en_set(struct aq_hw_s *aq_hw, uint32_t val,
+    uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_L4_RXQF_EN_ADR(filter),
 			HW_ATL_RPF_L3_L4_RXQF_EN_MSK,
@@ -1228,7 +1245,8 @@ hw_atl_rpf_l3_l4_rxqf_en_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filte
 }
 
 void
-hw_atl_rpf_l3_l4_mng_rxqf_set(struct aq_hw_s *aq_hw, uint32_t val, uint32_t filter)
+hw_atl_rpf_l3_l4_mng_rxqf_set(struct aq_hw_s *aq_hw, uint32_t val,
+    uint32_t filter)
 {
 	aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L3_L4_MNG_RXQF_ADR(filter),
 			HW_ATL_RPF_L3_L4_MNG_RXQF_MSK,
@@ -1321,7 +1339,8 @@ rpf_vlan_flr_en_set(struct aq_hw *aq_hw, uint32_t vlan_flr_en, uint32_t filter)
 }
 
 void
-rpf_vlan_flr_act_set(struct aq_hw *aq_hw, uint32_t vlan_flr_act, uint32_t filter)
+rpf_vlan_flr_act_set(struct aq_hw *aq_hw, uint32_t vlan_flr_act,
+    uint32_t filter)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rpf_vl_act_f_adr(filter), rpf_vl_act_f_msk,
 	    rpf_vl_act_f_shift, vlan_flr_act);
@@ -1366,21 +1385,24 @@ rpf_etht_user_priority_set(struct aq_hw *aq_hw, uint32_t etht_user_priority,
 }
 
 void
-rpf_etht_rx_queue_set(struct aq_hw *aq_hw, uint32_t etht_rx_queue, uint32_t filter)
+rpf_etht_rx_queue_set(struct aq_hw *aq_hw, uint32_t etht_rx_queue,
+    uint32_t filter)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rpf_et_rxqf_adr(filter), rpf_et_rxqf_msk,
 	    rpf_et_rxqf_shift, etht_rx_queue);
 }
 
 void
-rpf_etht_mgt_queue_set(struct aq_hw *aq_hw, uint32_t etht_mgt_queue, uint32_t filter)
+rpf_etht_mgt_queue_set(struct aq_hw *aq_hw, uint32_t etht_mgt_queue,
+    uint32_t filter)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rpf_et_mng_rxqf_adr(filter),
 	    rpf_et_mng_rxqf_msk, rpf_et_mng_rxqf_shift, etht_mgt_queue);
 }
 
 void
-rpf_etht_flr_act_set(struct aq_hw *aq_hw, uint32_t etht_flr_act, uint32_t filter)
+rpf_etht_flr_act_set(struct aq_hw *aq_hw, uint32_t etht_flr_act,
+    uint32_t filter)
 {
 	AQ_WRITE_REG_BIT(aq_hw, rpf_et_actf_adr(filter), rpf_et_actf_msk,
 	    rpf_et_actf_shift, etht_flr_act);
@@ -1565,14 +1587,16 @@ tdm_tx_dca_mode_set(struct aq_hw *aq_hw, uint32_t tx_dca_mode)
 }
 
 void
-tdm_tx_desc_dca_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_dca_en, uint32_t dca)
+tdm_tx_desc_dca_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_dca_en,
+    uint32_t dca)
 {
 	AQ_WRITE_REG_BIT(aq_hw, tdm_dcaddesc_en_adr(dca), tdm_dcaddesc_en_msk,
 	    tdm_dcaddesc_en_shift, tx_desc_dca_en);
 }
 
 void
-tdm_tx_desc_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_en, uint32_t descriptor)
+tdm_tx_desc_en_set(struct aq_hw *aq_hw, uint32_t tx_desc_en,
+    uint32_t descriptor)
 {
 	AQ_WRITE_REG_BIT(aq_hw, tdm_descden_adr(descriptor), tdm_descden_msk,
 	    tdm_descden_shift, tx_desc_en);
@@ -1586,7 +1610,8 @@ tdm_tx_desc_head_ptr_get(struct aq_hw *aq_hw, uint32_t descriptor)
 }
 
 void
-tdm_tx_desc_len_set(struct aq_hw *aq_hw, uint32_t tx_desc_len, uint32_t descriptor)
+tdm_tx_desc_len_set(struct aq_hw *aq_hw, uint32_t tx_desc_len,
+    uint32_t descriptor)
 {
 	AQ_WRITE_REG_BIT(aq_hw, tdm_descdlen_adr(descriptor), tdm_descdlen_msk,
 	    tdm_descdlen_shift, tx_desc_len);
@@ -1721,7 +1746,8 @@ tpo_ipv4header_crc_offload_en_set(struct aq_hw *aq_hw,
 }
 
 void
-tpo_tcp_udp_crc_offload_en_set(struct aq_hw *aq_hw, uint32_t tcp_udp_crc_offload_en)
+tpo_tcp_udp_crc_offload_en_set(struct aq_hw *aq_hw,
+    uint32_t tcp_udp_crc_offload_en)
 {
 	AQ_WRITE_REG_BIT(aq_hw, tpol4chk_en_adr, tpol4chk_en_msk,
 	    tpol4chk_en_shift, tcp_udp_crc_offload_en);
@@ -1876,7 +1902,8 @@ pci_pci_reg_res_dis_set(struct aq_hw *aq_hw, uint32_t pci_reg_res_dis)
 uint32_t
 reg_glb_cpu_scratch_scp_get(struct aq_hw *hw, uint32_t glb_cpu_scratch_scp_idx)
 {
-	return AQ_READ_REG(hw, glb_cpu_scratch_scp_adr(glb_cpu_scratch_scp_idx));
+	return AQ_READ_REG(hw,
+	    glb_cpu_scratch_scp_adr(glb_cpu_scratch_scp_idx));
 }
 void
 reg_glb_cpu_scratch_scp_set(struct aq_hw *aq_hw, uint32_t glb_cpu_scratch_scp,
@@ -1892,7 +1919,8 @@ reg_glb_cpu_no_reset_scratchpad_get(struct aq_hw *hw, uint32_t index)
 	return AQ_READ_REG(hw, glb_cpu_no_reset_scratchpad_adr(index));
 }
 void
-reg_glb_cpu_no_reset_scratchpad_set(struct aq_hw* hw, uint32_t value, uint32_t index)
+reg_glb_cpu_no_reset_scratchpad_set(struct aq_hw* hw, uint32_t value,
+    uint32_t index)
 {
 	AQ_WRITE_REG(hw, glb_cpu_no_reset_scratchpad_adr(index), value);
 }

sys/dev/aq/aq_media.c

@@ -119,7 +119,9 @@ aq_mediachange(if_t ifp)
 	AQ_DBG_ENTERA("media 0x%x", user_media);
 
 	if (!(ifm->ifm_media & IFM_ETHER)) {
-		device_printf(aq_dev->dev, "%s(): aq_dev interface - bad media: 0x%X", __FUNCTION__, ifm->ifm_media);
+		device_printf(aq_dev->dev,
+		    "%s(): aq_dev interface - bad media: 0x%X", __FUNCTION__,
+		    ifm->ifm_media);
 		return (0);    // should never happen
 	}
 

sys/dev/aq/aq_ring.c

@@ -107,9 +107,11 @@ aq_ring_rx_init(struct aq_hw *hw, struct aq_ring *ring)
 
 	rdm_rx_desc_len_set(hw, ring->rx_size / 8U, ring->index);
 
-	device_printf(ring->dev->dev, "ring %d: __PAGESIZE=%d MCLBYTES=%d hw->max_frame_size=%d\n",
+	device_printf(ring->dev->dev,
+	    "ring %d: __PAGESIZE=%d MCLBYTES=%d hw->max_frame_size=%d\n",
 	    ring->index, PAGE_SIZE, MCLBYTES, ring->rx_max_frame_size);
-	rdm_rx_desc_data_buff_size_set(hw, ring->rx_max_frame_size / 1024U, ring->index);
+	rdm_rx_desc_data_buff_size_set(hw, ring->rx_max_frame_size / 1024U,
+	    ring->index);
 
 	rdm_rx_desc_head_buff_size_set(hw, 0U, ring->index);
 	rdm_rx_desc_head_splitting_set(hw, 0U, ring->index);
@@ -279,7 +281,8 @@ aq_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget)
 
 	for (iter = 0, cnt = 0, i = idx;
 	    iter < ring->rx_size && cnt <= budget;) {
-		trace_aq_rx_descr(ring->index, i, (volatile uint64_t*)&rx_desc[i]);
+		trace_aq_rx_descr(ring->index, i,
+		    (volatile uint64_t*)&rx_desc[i]);
 		if (!rx_desc[i].wb.dd)
 			break;
 
@@ -355,7 +358,8 @@ aq_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
 	do {
 		rx_desc = (aq_rx_desc_t *) &ring->rx_descs[cidx];
 
-		trace_aq_rx_descr(ring->index, cidx, (volatile uint64_t*)rx_desc);
+		trace_aq_rx_descr(ring->index, cidx,
+		    (volatile uint64_t *)rx_desc);
 
 		if ((rx_desc->wb.rx_stat & BIT(0)) != 0) {
 			ring->stats.rx_err++;