From 3d8bbe001115f3e9742c128716335e654729ce1a Mon Sep 17 00:00:00 2001 From: Chandrakanth patil Date: Sat, 27 Apr 2024 23:53:05 +0530 Subject: [PATCH] bnxt_en: Firmware header version update to 1.10.3.42 This file is automatically generated from the firmware code to export the driver interfaces. Reviewed by: imp Approved by: imp Differential revision: https://reviews.freebsd.org/D45009 --- sys/dev/bnxt/bnxt_en/bnxt.h | 2 +- sys/dev/bnxt/bnxt_en/hsi_struct_def.h | 20689 +++++++++++++++++++----- 2 files changed, 16910 insertions(+), 3781 deletions(-) diff --git a/sys/dev/bnxt/bnxt_en/bnxt.h b/sys/dev/bnxt/bnxt_en/bnxt.h index 2faea00e426..cf4f99077b5 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt.h +++ b/sys/dev/bnxt/bnxt_en/bnxt.h @@ -771,7 +771,7 @@ struct bnxt_ctx_mem_type { #define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW #define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC #define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC -#define BNXT_CTX_MAX (BNXT_CTX_QRKC + 1) +#define BNXT_CTX_MAX (BNXT_CTX_TIM + 1) struct bnxt_ctx_mem_info { u8 tqm_fp_rings_count; diff --git a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h index 4aec765e1b2..baecfc8f659 100644 --- a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h +++ b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright (c) 2016 Broadcom, All Rights Reserved. + * Copyright (c) 2024 Broadcom, All Rights Reserved. * The term Broadcom refers to Broadcom Limited and/or its subsidiaries * * Redistribution and use in source and binary forms, with or without @@ -31,7 +31,7 @@ __FBSDID("$FreeBSD$"); /* - * Copyright(c) 2001-2023, Broadcom. All rights reserved. The + * Copyright(c) 2001-2024, Broadcom. All rights reserved. The * term Broadcom refers to Broadcom Inc. and/or its subsidiaries. * Proprietary and Confidential Information. * @@ -45,6 +45,10 @@ __FBSDID("$FreeBSD$"); #ifndef _HSI_STRUCT_DEF_H_ #define _HSI_STRUCT_DEF_H_ +#if defined(HAVE_STDINT_H) +#include +#endif + /* This is the HWRM command header. */ /* hwrm_cmd_hdr (size:128b/16B) */ @@ -76,7 +80,7 @@ typedef struct hwrm_cmd_hdr { * physical address (HPA) or a guest physical address (GPA) and must * point to a physically contiguous block of memory. */ - uint64_t resp_addr; + uint64_t resp_addr; } hwrm_cmd_hdr_t, *phwrm_cmd_hdr_t; /* This is the HWRM response header. */ @@ -111,6 +115,10 @@ typedef struct hwrm_resp_hdr { #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4) /* RoCE slow path command to modify CC Gen1 support. */ #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5) +/* RoCE slow path command to query CC Gen2 support. */ +#define TLV_TYPE_QUERY_ROCE_CC_GEN2 UINT32_C(0x6) +/* RoCE slow path command to modify CC Gen2 support. */ +#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 UINT32_C(0x7) /* Engine CKV - The Alias key EC curve and ECC public key information. */ #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001) /* Engine CKV - Initialization vector. */ @@ -193,14 +201,14 @@ typedef struct tlv { typedef struct input { /* - * This value indicates what type of request this is. The format + * This value indicates what type of request this is. The format * for the rest of the command is determined by this field. */ uint16_t req_type; /* * This value indicates the what completion ring the request will - * be optionally completed on. If the value is -1, then no - * CR completion will be generated. Any other value must be a + * be optionally completed on. If the value is -1, then no + * CR completion will be generated. Any other value must be a * valid CR ring_id value for this function. */ uint16_t cmpl_ring; @@ -216,7 +224,7 @@ typedef struct input { uint16_t target_id; /* * This is the host address where the response will be written - * when the request is complete. This area must be 16B aligned + * when the request is complete. This area must be 16B aligned * and must be cleared to zero before the request is made. */ uint64_t resp_addr; @@ -238,7 +246,7 @@ typedef struct output { /* This field provides original sequence number of the command. */ uint16_t seq_id; /* - * This field is the length of the response in bytes. The + * This field is the length of the response in bytes. The * last byte of the response is a valid flag that will read * as '1' when the command has been completely written to * memory. @@ -374,6 +382,14 @@ typedef struct hwrm_short_input { ((x) == 0x85 ? "HWRM_QUEUE_VLANPRI2PRI_CFG": \ ((x) == 0x86 ? "HWRM_QUEUE_GLOBAL_CFG": \ ((x) == 0x87 ? "HWRM_QUEUE_GLOBAL_QCFG": \ + ((x) == 0x88 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG": \ + ((x) == 0x89 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG": \ + ((x) == 0x8a ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG": \ + ((x) == 0x8b ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG": \ + ((x) == 0x8c ? "HWRM_QUEUE_QCAPS": \ + ((x) == 0x8d ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG": \ + ((x) == 0x8e ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG": \ + ((x) == 0x8f ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG": \ ((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \ ((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \ ((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \ @@ -392,6 +408,7 @@ typedef struct hwrm_short_input { ((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \ ((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \ ((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \ + ((x) == 0xa3 ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG": \ ((x) == 0xaf ? "HWRM_STAT_CTX_ENG_QUERY": \ ((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \ ((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \ @@ -439,6 +456,7 @@ typedef struct hwrm_short_input { ((x) == 0xdb ? "HWRM_PORT_EP_TX_CFG": \ ((x) == 0xdc ? "HWRM_PORT_CFG": \ ((x) == 0xdd ? "HWRM_PORT_QCFG": \ + ((x) == 0xdf ? "HWRM_PORT_MAC_QCAPS": \ ((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \ ((x) == 0xe1 ? "HWRM_REG_POWER_QUERY": \ ((x) == 0xe2 ? "HWRM_CORE_FREQUENCY_QUERY": \ @@ -456,7 +474,7 @@ typedef struct hwrm_short_input { ((x) == 0xfa ? "HWRM_CFA_METER_INSTANCE_CFG": \ ((x) == 0xfd ? "HWRM_CFA_VFR_ALLOC": \ ((x) == 0xfe ? "HWRM_CFA_VFR_FREE": \ - "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x180) ? \ ((x) == 0x100 ? "HWRM_CFA_VF_PAIR_ALLOC": \ ((x) == 0x101 ? "HWRM_CFA_VF_PAIR_FREE": \ @@ -500,6 +518,7 @@ typedef struct hwrm_short_input { ((x) == 0x127 ? "HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR": \ ((x) == 0x128 ? "HWRM_CFA_TLS_FILTER_ALLOC": \ ((x) == 0x129 ? "HWRM_CFA_TLS_FILTER_FREE": \ + ((x) == 0x12a ? "HWRM_CFA_RELEASE_AFM_FUNC": \ ((x) == 0x12e ? "HWRM_ENGINE_CKV_STATUS": \ ((x) == 0x12f ? "HWRM_ENGINE_CKV_CKEK_ADD": \ ((x) == 0x130 ? "HWRM_ENGINE_CKV_CKEK_DELETE": \ @@ -539,7 +558,7 @@ typedef struct hwrm_short_input { ((x) == 0x163 ? "HWRM_ENGINE_NQ_FREE": \ ((x) == 0x164 ? "HWRM_ENGINE_ON_DIE_RQE_CREDITS": \ ((x) == 0x165 ? "HWRM_ENGINE_FUNC_QCFG": \ - "Unknown decode" ))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x200) ? \ ((x) == 0x190 ? "HWRM_FUNC_RESOURCE_QCAPS": \ ((x) == 0x191 ? "HWRM_FUNC_VF_RESOURCE_CFG": \ @@ -570,7 +589,14 @@ typedef struct hwrm_short_input { ((x) == 0x1aa ? "HWRM_FUNC_DBR_RECOVERY_COMPLETED": \ ((x) == 0x1ab ? "HWRM_FUNC_SYNCE_CFG": \ ((x) == 0x1ac ? "HWRM_FUNC_SYNCE_QCFG": \ - "Unknown decode" ))))))))))))))))))))))))))))) : \ + ((x) == 0x1ad ? "HWRM_FUNC_KEY_CTX_FREE": \ + ((x) == 0x1ae ? "HWRM_FUNC_LAG_MODE_CFG": \ + ((x) == 0x1af ? "HWRM_FUNC_LAG_MODE_QCFG": \ + ((x) == 0x1b0 ? "HWRM_FUNC_LAG_CREATE": \ + ((x) == 0x1b1 ? "HWRM_FUNC_LAG_UPDATE": \ + ((x) == 0x1b2 ? "HWRM_FUNC_LAG_FREE": \ + ((x) == 0x1b3 ? "HWRM_FUNC_LAG_QCFG": \ + "Unknown decode" )))))))))))))))))))))))))))))))))))) : \ (((x) < 0x280) ? \ ((x) == 0x200 ? "HWRM_SELFTEST_QLIST": \ ((x) == 0x201 ? "HWRM_SELFTEST_EXEC": \ @@ -586,9 +612,9 @@ typedef struct hwrm_short_input { ((x) == 0x20b ? "HWRM_MFG_FRU_EEPROM_READ": \ ((x) == 0x20c ? "HWRM_MFG_SOC_IMAGE": \ ((x) == 0x20d ? "HWRM_MFG_SOC_QSTATUS": \ - ((x) == 0x20e ? "HWRM_MFG_PARAM_SEEPROM_SYNC": \ - ((x) == 0x20f ? "HWRM_MFG_PARAM_SEEPROM_READ": \ - ((x) == 0x210 ? "HWRM_MFG_PARAM_SEEPROM_HEALTH": \ + ((x) == 0x20e ? "HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE": \ + ((x) == 0x20f ? "HWRM_MFG_PARAM_CRITICAL_DATA_READ": \ + ((x) == 0x210 ? "HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH": \ ((x) == 0x211 ? "HWRM_MFG_PRVSN_EXPORT_CSR": \ ((x) == 0x212 ? "HWRM_MFG_PRVSN_IMPORT_CERT": \ ((x) == 0x213 ? "HWRM_MFG_PRVSN_GET_STATE": \ @@ -597,12 +623,22 @@ typedef struct hwrm_short_input { ((x) == 0x216 ? "HWRM_MFG_SELFTEST_QLIST": \ ((x) == 0x217 ? "HWRM_MFG_SELFTEST_EXEC": \ ((x) == 0x218 ? "HWRM_STAT_GENERIC_QSTATS": \ - "Unknown decode" ))))))))))))))))))))))))) : \ + ((x) == 0x219 ? "HWRM_MFG_PRVSN_EXPORT_CERT": \ + ((x) == 0x21a ? "HWRM_STAT_DB_ERROR_QSTATS": \ + ((x) == 0x258 ? "HWRM_UDCC_QCAPS": \ + ((x) == 0x259 ? "HWRM_UDCC_CFG": \ + ((x) == 0x25a ? "HWRM_UDCC_QCFG": \ + ((x) == 0x25b ? "HWRM_UDCC_SESSION_CFG": \ + ((x) == 0x25c ? "HWRM_UDCC_SESSION_QCFG": \ + ((x) == 0x25d ? "HWRM_UDCC_SESSION_QUERY": \ + ((x) == 0x25e ? "HWRM_UDCC_COMP_CFG": \ + ((x) == 0x25f ? "HWRM_UDCC_COMP_QCFG": \ + ((x) == 0x260 ? "HWRM_UDCC_COMP_QUERY": \ + "Unknown decode" )))))))))))))))))))))))))))))))))))) : \ (((x) < 0x300) ? \ ((x) == 0x2bc ? "HWRM_TF": \ ((x) == 0x2bd ? "HWRM_TF_VERSION_GET": \ ((x) == 0x2c6 ? "HWRM_TF_SESSION_OPEN": \ - ((x) == 0x2c7 ? "HWRM_TF_SESSION_ATTACH": \ ((x) == 0x2c8 ? "HWRM_TF_SESSION_REGISTER": \ ((x) == 0x2c9 ? "HWRM_TF_SESSION_UNREGISTER": \ ((x) == 0x2ca ? "HWRM_TF_SESSION_CLOSE": \ @@ -617,14 +653,6 @@ typedef struct hwrm_short_input { ((x) == 0x2da ? "HWRM_TF_TBL_TYPE_GET": \ ((x) == 0x2db ? "HWRM_TF_TBL_TYPE_SET": \ ((x) == 0x2dc ? "HWRM_TF_TBL_TYPE_BULK_GET": \ - ((x) == 0x2e2 ? "HWRM_TF_CTXT_MEM_ALLOC": \ - ((x) == 0x2e3 ? "HWRM_TF_CTXT_MEM_FREE": \ - ((x) == 0x2e4 ? "HWRM_TF_CTXT_MEM_RGTR": \ - ((x) == 0x2e5 ? "HWRM_TF_CTXT_MEM_UNRGTR": \ - ((x) == 0x2e6 ? "HWRM_TF_EXT_EM_QCAPS": \ - ((x) == 0x2e7 ? "HWRM_TF_EXT_EM_OP": \ - ((x) == 0x2e8 ? "HWRM_TF_EXT_EM_CFG": \ - ((x) == 0x2e9 ? "HWRM_TF_EXT_EM_QCFG": \ ((x) == 0x2ea ? "HWRM_TF_EM_INSERT": \ ((x) == 0x2eb ? "HWRM_TF_EM_DELETE": \ ((x) == 0x2ec ? "HWRM_TF_EM_HASH_INSERT": \ @@ -637,7 +665,13 @@ typedef struct hwrm_short_input { ((x) == 0x2fd ? "HWRM_TF_GLOBAL_CFG_GET": \ ((x) == 0x2fe ? "HWRM_TF_IF_TBL_SET": \ ((x) == 0x2ff ? "HWRM_TF_IF_TBL_GET": \ - "Unknown decode" )))))))))))))))))))))))))))))))))))))) : \ + "Unknown decode" ))))))))))))))))))))))))))))) : \ + (((x) < 0x380) ? \ + ((x) == 0x300 ? "HWRM_TF_RESC_USAGE_SET": \ + ((x) == 0x301 ? "HWRM_TF_RESC_USAGE_QUERY": \ + ((x) == 0x302 ? "HWRM_TF_TBL_TYPE_ALLOC": \ + ((x) == 0x303 ? "HWRM_TF_TBL_TYPE_FREE": \ + "Unknown decode" )))) : \ (((x) < 0x400) ? \ ((x) == 0x380 ? "HWRM_TFC_TBL_SCOPE_QCAPS": \ ((x) == 0x381 ? "HWRM_TFC_TBL_SCOPE_ID_ALLOC": \ @@ -663,11 +697,19 @@ typedef struct hwrm_short_input { ((x) == 0x395 ? "HWRM_TFC_TCAM_ALLOC": \ ((x) == 0x396 ? "HWRM_TFC_TCAM_ALLOC_SET": \ ((x) == 0x397 ? "HWRM_TFC_TCAM_FREE": \ - "Unknown decode" )))))))))))))))))))))))) : \ + ((x) == 0x398 ? "HWRM_TFC_IF_TBL_SET": \ + ((x) == 0x399 ? "HWRM_TFC_IF_TBL_GET": \ + ((x) == 0x39a ? "HWRM_TFC_TBL_SCOPE_CONFIG_GET": \ + ((x) == 0x39b ? "HWRM_TFC_RESC_USAGE_QUERY": \ + ((x) == 0x39c ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS": \ + ((x) == 0x39d ? "HWRM_QUEUE_PFCWD_TIMEOUT_CFG": \ + ((x) == 0x39e ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCFG": \ + "Unknown decode" ))))))))))))))))))))))))))))))) : \ (((x) < 0x480) ? \ ((x) == 0x400 ? "HWRM_SV": \ "Unknown decode" ) : \ (((x) < 0xff80) ? \ + ((x) == 0xff0f ? "HWRM_DBG_LOG_BUFFER_FLUSH": \ ((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \ ((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \ ((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \ @@ -696,8 +738,10 @@ typedef struct hwrm_short_input { ((x) == 0xff29 ? "HWRM_DBG_USEQ_RUN": \ ((x) == 0xff2a ? "HWRM_DBG_USEQ_DELIVERY_REQ": \ ((x) == 0xff2b ? "HWRM_DBG_USEQ_RESP_HDR": \ - "Unknown decode" )))))))))))))))))))))))))))) : \ + "Unknown decode" ))))))))))))))))))))))))))))) : \ (((x) <= 0xffff) ? \ + ((x) == 0xffea ? "HWRM_NVM_GET_VPD_FIELD_INFO": \ + ((x) == 0xffeb ? "HWRM_NVM_SET_VPD_FIELD_INFO": \ ((x) == 0xffec ? "HWRM_NVM_DEFRAG": \ ((x) == 0xffed ? "HWRM_NVM_REQ_ARBITRATION": \ ((x) == 0xffee ? "HWRM_NVM_FACTORY_DEFAULTS": \ @@ -718,8 +762,8 @@ typedef struct hwrm_short_input { ((x) == 0xfffd ? "HWRM_NVM_READ": \ ((x) == 0xfffe ? "HWRM_NVM_WRITE": \ ((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \ - "Unknown decode" )))))))))))))))))))) : \ - "Unknown decode" )))))))))) + "Unknown decode" )))))))))))))))))))))) : \ + "Unknown decode" ))))))))))) /* @@ -800,7 +844,7 @@ typedef struct cmd_nums { #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34) #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35) #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36) - #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37) + #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37) #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38) #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39) #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a) @@ -848,6 +892,14 @@ typedef struct cmd_nums { #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85) #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86) #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG UINT32_C(0x88) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG UINT32_C(0x89) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG UINT32_C(0x8a) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG UINT32_C(0x8b) + #define HWRM_QUEUE_QCAPS UINT32_C(0x8c) + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG UINT32_C(0x8d) + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG UINT32_C(0x8e) + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG UINT32_C(0x8f) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -871,6 +923,7 @@ typedef struct cmd_nums { #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0) #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1) #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2) + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG UINT32_C(0xa3) #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf) #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0) #define HWRM_STAT_CTX_FREE UINT32_C(0xb1) @@ -926,6 +979,8 @@ typedef struct cmd_nums { #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb) #define HWRM_PORT_CFG UINT32_C(0xdc) #define HWRM_PORT_QCFG UINT32_C(0xdd) + /* Queries MAC capabilities for the specified port */ + #define HWRM_PORT_MAC_QCAPS UINT32_C(0xdf) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) @@ -1029,7 +1084,12 @@ typedef struct cmd_nums { #define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128) /* Experimental */ #define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129) - /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ + /* Release an AFM function for TF control */ + #define HWRM_CFA_RELEASE_AFM_FUNC UINT32_C(0x12a) + /* + * Engine CKV - Get the current allocation status of keys provisioned in + * the key vault. + */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) /* Engine CKV - Add a new CKEK used to encrypt keys. */ #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f) @@ -1089,7 +1149,10 @@ typedef struct cmd_nums { #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156) /* Engine - Query the statistics accumulator for an Engine. */ #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157) - /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */ + /* + * Engine - Query statistics counters for continuous errors from all CDDIP + * Engines. + */ #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158) /* Engine - Allocate an Engine RQ. */ #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e) @@ -1171,6 +1234,20 @@ typedef struct cmd_nums { #define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab) /* Queries SyncE configurations. */ #define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac) + /* The command is used to deallocate KTLS or QUIC key contexts. */ + #define HWRM_FUNC_KEY_CTX_FREE UINT32_C(0x1ad) + /* The command is used to configure link aggr group mode. */ + #define HWRM_FUNC_LAG_MODE_CFG UINT32_C(0x1ae) + /* The command is used to query link aggr group mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG UINT32_C(0x1af) + /* The command is used to create a link aggr group. */ + #define HWRM_FUNC_LAG_CREATE UINT32_C(0x1b0) + /* The command is used to update a link aggr group. */ + #define HWRM_FUNC_LAG_UPDATE UINT32_C(0x1b1) + /* The command is used to free a link aggr group. */ + #define HWRM_FUNC_LAG_FREE UINT32_C(0x1b2) + /* The command is used to query a link aggr group. */ + #define HWRM_FUNC_LAG_QCFG UINT32_C(0x1b3) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -1202,12 +1279,12 @@ typedef struct cmd_nums { #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c) /* Retrieves the SoC status and image provisioning information */ #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d) - /* Tells the fw to program the seeprom memory */ - #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e) - /* Tells the fw to read the seeprom memory */ - #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f) - /* Tells the fw to get the health of seeprom data */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210) + /* Tells the fw to finalize the critical data (store and lock it) */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE UINT32_C(0x20e) + /* Tells the fw to read the critical data */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_READ UINT32_C(0x20f) + /* Tells the fw to get the health of critical data */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH UINT32_C(0x210) /* * The command is used for certificate provisioning to export a * Certificate Signing Request (CSR) from the device. @@ -1242,6 +1319,37 @@ typedef struct cmd_nums { #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) /* Queries the generic stats */ #define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218) + /* + * The command is used for certificate provisioning to export a + * certificate chain from the device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CERT UINT32_C(0x219) + /* Query the statistics for doorbell drops due to various error conditions. */ + #define HWRM_STAT_DB_ERROR_QSTATS UINT32_C(0x21a) + /* + * This command returns the capabilities related to User Defined + * Congestion Control on a function. + */ + #define HWRM_UDCC_QCAPS UINT32_C(0x258) + /* This command configures User Defined Congestion Control on a function. */ + #define HWRM_UDCC_CFG UINT32_C(0x259) + /* + * This command queries the configuration of User Defined Congestion + * Control on a function. + */ + #define HWRM_UDCC_QCFG UINT32_C(0x25a) + /* This command configures an existing UDCC session. */ + #define HWRM_UDCC_SESSION_CFG UINT32_C(0x25b) + /* This command queries the configuration of a UDCC session. */ + #define HWRM_UDCC_SESSION_QCFG UINT32_C(0x25c) + /* This command queries the UDCC session. */ + #define HWRM_UDCC_SESSION_QUERY UINT32_C(0x25d) + /* This command configures the computation unit. */ + #define HWRM_UDCC_COMP_CFG UINT32_C(0x25e) + /* This command queries the configuration of the computation unit. */ + #define HWRM_UDCC_COMP_QCFG UINT32_C(0x25f) + /* This command queries the status and statistics of the computation unit. */ + #define HWRM_UDCC_COMP_QUERY UINT32_C(0x260) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -1249,8 +1357,6 @@ typedef struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6) /* Experimental */ - #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7) - /* Experimental */ #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8) /* Experimental */ #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9) @@ -1279,22 +1385,6 @@ typedef struct cmd_nums { /* Experimental */ #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc) /* Experimental */ - #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4) - /* Experimental */ - #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5) - /* Experimental */ - #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6) - /* Experimental */ - #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7) - /* Experimental */ - #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8) - /* Experimental */ - #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9) - /* Experimental */ #define HWRM_TF_EM_INSERT UINT32_C(0x2ea) /* Experimental */ #define HWRM_TF_EM_DELETE UINT32_C(0x2eb) @@ -1318,6 +1408,14 @@ typedef struct cmd_nums { #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe) /* Experimental */ #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff) + /* Experimental */ + #define HWRM_TF_RESC_USAGE_SET UINT32_C(0x300) + /* Experimental */ + #define HWRM_TF_RESC_USAGE_QUERY UINT32_C(0x301) + /* Truflow command to allocate a table */ + #define HWRM_TF_TBL_TYPE_ALLOC UINT32_C(0x302) + /* Truflow command to free a table */ + #define HWRM_TF_TBL_TYPE_FREE UINT32_C(0x303) /* TruFlow command to check firmware table scope capabilities. */ #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380) /* TruFlow command to allocate a table scope ID and create the pools. */ @@ -1330,9 +1428,9 @@ typedef struct cmd_nums { #define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384) /* TruFlow command to remove a FID from a table scope. */ #define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385) - /* TruFlow command to allocate a table scope pool. */ + /* DEPRECATED */ #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386) - /* TruFlow command to free a table scope pool. */ + /* DEPRECATED */ #define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387) /* Experimental */ #define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388) @@ -1366,8 +1464,30 @@ typedef struct cmd_nums { #define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396) /* TruFlow command to free a TCAM entry. */ #define HWRM_TFC_TCAM_FREE UINT32_C(0x397) + /* Truflow command to set an interface table entry */ + #define HWRM_TFC_IF_TBL_SET UINT32_C(0x398) + /* Truflow command to get an interface table entry */ + #define HWRM_TFC_IF_TBL_GET UINT32_C(0x399) + /* TruFlow command to get configured info about a table scope. */ + #define HWRM_TFC_TBL_SCOPE_CONFIG_GET UINT32_C(0x39a) + /* TruFlow command to query the resource usage state. */ + #define HWRM_TFC_RESC_USAGE_QUERY UINT32_C(0x39b) + /* + * This command is used to query the pfc watchdog max configurable + * timeout value. + */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS UINT32_C(0x39c) + /* This command is used to set the PFC watchdog timeout value. */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG UINT32_C(0x39d) + /* + * This command is used to query the current configured pfc watchdog + * timeout value. + */ + #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x39e) /* Experimental */ #define HWRM_SV UINT32_C(0x400) + /* Flush any trace buffer data that has not been sent to the host. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH UINT32_C(0xff0f) /* Experimental */ #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10) /* Experimental */ @@ -1423,6 +1543,8 @@ typedef struct cmd_nums { #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a) /* Experimental */ #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b) + #define HWRM_NVM_GET_VPD_FIELD_INFO UINT32_C(0xffea) + #define HWRM_NVM_SET_VPD_FIELD_INFO UINT32_C(0xffeb) #define HWRM_NVM_DEFRAG UINT32_C(0xffec) #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ @@ -1518,14 +1640,14 @@ typedef struct ret_codes { #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc) /* * This error code is only reported by firmware when the registered - * driver instances requested to offloaded a flow but was unable to because - * the requested key's hash collides with the installed keys. + * driver instances requested to offloaded a flow but was unable to + * because the requested key's hash collides with the installed keys. */ #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd) /* * This error code is only reported by firmware when the registered - * driver instances requested to offloaded a flow but was unable to because - * the same key has already been installed. + * driver instances requested to offloaded a flow but was unable to + * because the same key has already been installed. */ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe) /* @@ -1534,8 +1656,8 @@ typedef struct ret_codes { */ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf) /* - * Firmware is unable to service the request at the present time. Caller - * may try again later. + * Firmware is unable to service the request at the present time. + * Caller may try again later. */ #define HWRM_ERR_CODE_BUSY UINT32_C(0x10) /* @@ -1550,6 +1672,11 @@ typedef struct ret_codes { * async completion ring or associated forwarding buffers configured. */ #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12) + /* + * This error code is reported by Firmware when the specific entity + * requested by the host is not present or does not exist. + */ + #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT UINT32_C(0x13) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the @@ -1587,7 +1714,8 @@ typedef struct ret_codes { ((x) == 0x10 ? "BUSY": \ ((x) == 0x11 ? "RESOURCE_LOCKED": \ ((x) == 0x12 ? "PF_UNAVAILABLE": \ - "Unknown decode" ))))))))))))))))))) : \ + ((x) == 0x13 ? "ENTITY_NOT_PRESENT": \ + "Unknown decode" )))))))))))))))))))) : \ (((x) < 0x8080) ? \ ((x) == 0x8000 ? "TLV_ENCAPSULATED_RESPONSE": \ "Unknown decode" ) : \ @@ -1614,7 +1742,7 @@ typedef struct hwrm_err_output { /* This field provides original sequence number of the command. */ uint16_t seq_id; /* - * This field is the length of the response in bytes. The + * This field is the length of the response in bytes. The * last byte of the response is a valid flag that will read * as '1' when the command has been completely written to * memory. @@ -1631,9 +1759,9 @@ typedef struct hwrm_err_output { uint8_t cmd_err; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -1644,7 +1772,12 @@ typedef struct hwrm_err_output { * applicable (All F's). Need to cast it the size of the field if needed. */ #define HWRM_NA_SIGNATURE ((uint32_t)(-1)) -/* hwrm_func_buf_rgtr */ +/* + * This is reflecting the size of the PF mailbox and not the maximum + * command size for any of the HWRM command structures. To determine + * the maximum size of an HWRM command supported by the firmware, see + * the max_ext_req_len field in the response of the HWRM_VER_GET command. + */ #define HWRM_MAX_REQ_LEN 128 /* hwrm_cfa_flow_info */ #define HWRM_MAX_RESP_LEN 704 @@ -1668,10 +1801,10 @@ typedef struct hwrm_err_output { #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 2 +#define HWRM_VERSION_UPDATE 3 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 136 -#define HWRM_VERSION_STR "1.10.2.136" +#define HWRM_VERSION_RSVD 42 +#define HWRM_VERSION_STR "1.10.3.42" /**************** * hwrm_ver_get * @@ -1887,47 +2020,52 @@ typedef struct hwrm_ver_get_output { /* * If set to 1, then the KONG host mailbox channel is supported. * If set to 0, then the KONG host mailbox channel is not supported. - * By default, this flag should be 0 for older version of core firmware. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED UINT32_C(0x10) /* - * If set to 1, then the 64bit flow handle is supported in addition to the - * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not - * supported. By default, this flag should be 0 for older version of core firmware. + * If set to 1, then the 64bit flow handle is supported in addition + * to the legacy 16bit flow handle. If set to 0, then the 64bit flow + * handle is not supported. By default, this flag should be 0 for + * older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED UINT32_C(0x20) /* - * If set to 1, then filter type can be provided in filter_alloc or filter_cfg - * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic. - * If set to 0, then filter types not supported. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, then filter type can be provided in filter_alloc or + * filter_cfg filter types like L2 for l2 traffic and ROCE for roce & + * l2 traffic. If set to 0, then filter types not supported. By + * default, this flag should be 0 for older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED UINT32_C(0x40) /* - * If set to 1, firmware is capable to support virtio vSwitch offload model. - * If set to 0, firmware can't supported virtio vSwitch offload model. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, firmware is capable to support virtio vSwitch offload + * model. If set to 0, firmware can't supported virtio vSwitch + * offload model. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED UINT32_C(0x80) /* * If set to 1, firmware is capable to support trusted VF. * If set to 0, firmware is not capable to support trusted VF. - * By default, this flag should be 0 for older version of core firmware. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED UINT32_C(0x100) /* * If set to 1, firmware is capable to support flow aging. * If set to 0, firmware is not capable to support flow aging. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * By default, this flag should be 0 for older version of core + * firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED UINT32_C(0x200) /* - * If set to 1, firmware is capable to support advanced flow counters like, - * Meter drop counters and EEM counters. - * If set to 0, firmware is not capable to support advanced flow counters. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * If set to 1, firmware is capable to support advanced flow counters + * like, Meter drop counters and EEM counters. + * If set to 0, firmware is not capable to support advanced flow + * counters. By default, this flag should be 0 for older version of + * core firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED UINT32_C(0x400) /* @@ -1935,28 +2073,30 @@ typedef struct hwrm_ver_get_output { * Extended Exact Match(EEM) feature. * If set to 0, firmware is not capable to support the use of the * CFA EEM feature. - * By default, this flag should be 0 for older version of core firmware. - * (deprecated) + * By default, this flag should be 0 for older version of core + * firmware. (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED UINT32_C(0x800) /* - * If set to 1, the firmware is able to support advance CFA flow management - * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS. - * If set to 0, then the firmware doesn’t support the advance CFA flow management - * features. - * By default, this flag should be 0 for older version of core firmware. + * If set to 1, the firmware is able to support advance CFA flow + * management features reported in the HWRM_CFA_FLOW_MGNT_QCAPS. + * If set to 0, then the firmware doesn't support the advance CFA + * flow management features. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED UINT32_C(0x1000) /* * Deprecated and replaced with cfa_truflow_supported. * If set to 1, the firmware is able to support TFLIB features. - * If set to 0, then the firmware doesn’t support TFLIB features. - * By default, this flag should be 0 for older version of core firmware. + * If set to 0, then the firmware doesn't support TFLIB features. + * By default, this flag should be 0 for older version of core + * firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED UINT32_C(0x2000) /* * If set to 1, the firmware is able to support TruFlow features. - * If set to 0, then the firmware doesn’t support TruFlow features. + * If set to 0, then the firmware doesn't support TruFlow features. * By default, this flag should be 0 for older version of * core firmware. */ @@ -1966,6 +2106,13 @@ typedef struct hwrm_ver_get_output { * If set to 0, then firmware doesn't support secure boot. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE UINT32_C(0x8000) + /* + * If set to 1, then firmware is able to support the secure solution + * feature. + * If set to 0, then firmware does not support the secure solution + * feature. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_SOC_CAPABLE UINT32_C(0x10000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -2018,7 +2165,10 @@ typedef struct hwrm_ver_get_output { uint8_t chip_metal; /* This field returns the bond id of the chip. */ uint8_t chip_bond_id; - /* This value indicates the type of platform used for chip implementation. */ + /* + * This value indicates the type of platform used for chip + * implementation. + */ uint8_t chip_platform_type; /* ASIC */ #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0) @@ -2071,8 +2221,8 @@ typedef struct hwrm_ver_get_output { * host drivers that it has not completed resource initialization * required for data path operations. Host drivers should not send * any HWRM command that requires data path resources. Firmware will - * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry - * those commands once both the flags are cleared. + * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can + * retry those commands once both the flags are cleared. * If this flag and dev_not_rdy flag are set to 0, device is ready * to accept all HWRM commands. */ @@ -2232,9 +2382,9 @@ typedef struct hwrm_ver_get_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -2801,11 +2951,11 @@ typedef struct crypto_presync_bd_cmd { * Typically, presync BDs are used for packet retransmissions. Source * port sends all the packets in order over the network to destination * port and packets get dropped in the network. The destination port - * will request retranmission of dropped packets and source port driver - * will send presync BD to setup the transmitter appropriately. It will - * provide the start and end TCP sequence number of the data to be - * transmitted. HW keeps two sets of context variable, one for in order - * traffic and one for retransmission traffic. HW is designed to + * will request retransmission of dropped packets and source port + * driver will send presync BD to setup the transmitter appropriately. + * It will provide the start and end TCP sequence number of the data to + * be transmitted. HW keeps two sets of context variable, one for in + * order traffic and one for retransmission traffic. HW is designed to * transmit everything posted in the presync BD and return to in order * mode after that. No inorder context variables are updated in the * process. There is a special case where packets can be dropped @@ -2955,22 +3105,22 @@ typedef struct ce_bds_quic_add_data_msg { * exchanged as part of sessions setup between the two end * points for QUIC operations. */ - uint64_t quic_iv_lo; + uint8_t quic_iv_lo[8]; /* * Most-significant 32 bits (of 96) of additional IV that is * exchanged as part of sessions setup between the two end * points for QUIC operations. */ - uint32_t quic_iv_hi; + uint8_t quic_iv_hi[4]; uint32_t unused_1; /* * Key used for encrypting or decrypting records. The Key is exchanged * as part of sessions setup between the two end points through this * mid-path BD. */ - uint32_t session_key[8]; + uint8_t session_key[32]; /* Header protection key. */ - uint32_t hp_key[8]; + uint8_t hp_key[32]; /* Packet number associated with the QUIC connection. */ uint64_t pkt_number; } ce_bds_quic_add_data_msg_t, *pce_bds_quic_add_data_msg_t; @@ -3149,7 +3299,8 @@ typedef struct tx_bd_short { * * This value must be valid on all BDs of a packet. */ - uint64_t addr; + uint32_t addr_lo; + uint32_t addr_hi; } tx_bd_short_t, *ptx_bd_short_t; /* tx_bd_long (size:128b/16B) */ @@ -3359,7 +3510,7 @@ typedef struct tx_bd_long_hi { * 0xffff. * * If set to one when LSO is '1', then the IPID will be treated - * as a 15b number and will be wrapped if it exceeds a value 0f + * as a 15b number and will be wrapped if it exceeds a value of * 0x7fff. */ #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40) @@ -3418,7 +3569,7 @@ typedef struct tx_bd_long_hi { * will be the following behavior for all cases independent of * settings of inner LSO and checksum offload BD flags. * If outer UDP checksum is 0, then do not update it. - * If outer UDP checksum is non zero, then the hardware should + * If outer UDP checksum is non zero, then the hardware should * compute and update it. */ #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000) @@ -3554,7 +3705,7 @@ typedef struct tx_bd_long_hi { * - Wh+/SR - this option is not supported. * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta * is set in the Lookup Table. - * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if * en_bd_meta is set in the Lookup Table. */ #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28) @@ -3650,7 +3801,8 @@ typedef struct tx_bd_long_inline { * This field must be valid on the first BD of a packet. */ uint32_t opaque; - uint64_t unused1; + uint32_t unused1_lo; + uint32_t unused1_hi; /* * All bits in this field must be valid on the first BD of a packet. * Their value on other BDs of the packet is ignored. @@ -3859,7 +4011,7 @@ typedef struct tx_bd_long_inline { * - Wh+/SR - this option is not supported. * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta * is set in the Lookup Table. - * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if + * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if * en_bd_meta is set in the Lookup Table. */ #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28) @@ -3927,7 +4079,8 @@ typedef struct tx_bd_mp_cmd { * Tx mid-path command. */ uint32_t opaque; - uint64_t unused1; + uint32_t unused1_lo; + uint32_t unused1_hi; } tx_bd_mp_cmd_t, *ptx_bd_mp_cmd_t; /* tx_bd_presync_cmd (size:128b/16B) */ @@ -3987,6 +4140,96 @@ typedef struct tx_bd_presync_cmd { uint32_t unused_1; } tx_bd_presync_cmd_t, *ptx_bd_presync_cmd_t; +/* + * This structure is used to send additional information for transmitting + * packets using timed transmit scheduling. It must only to be applied as + * the second BD of a BD chain that represents a packet. Any subsequent + * BDs will follow the timed transmit BD. + */ +/* tx_bd_timedtx (size:128b/16B) */ + +typedef struct tx_bd_timedtx { + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_TIMEDTX_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_TIMEDTX_TYPE_SFT 0 + /* + * Indicates a timed transmit BD. This is a 16b BD that is inserted + * into a packet BD chain immediately after the first BD. It is used + * to control the flow in a timed transmit operation. + */ + #define TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX UINT32_C(0xa) + #define TX_BD_TIMEDTX_TYPE_LAST TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX + /* Unless otherwise stated, sub-fields of this field are always valid. */ + #define TX_BD_TIMEDTX_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_TIMEDTX_FLAGS_SFT 6 + /* + * This value identifies the kind of buffer timed transmit mode that + * is to be enabled for the packet. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_MASK UINT32_C(0x1c0) + #define TX_BD_TIMEDTX_FLAGS_KIND_SFT 6 + /* + * This timed transmit mode indicates that the packet will be + * scheduled and send immediately (or as soon as possible), once + * it is scheduled in the transmitter. + * Note: This mode is similar to regular (non-timed transmit) + * operation. Its main purpose is to cancel pace mode timed + * transmit. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_ASAP (UINT32_C(0x0) << 6) + /* + * This timed transmit mode is used to schedule transmission of + * the packet no earlier than the time given in the tx_time + * field of the BD. + * Note: In case subsequent packets don't include a timed transmit + * BD, they will be scheduled subsequently for transmission + * without any timed transmit constraint. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_SO_TXTIME (UINT32_C(0x1) << 6) + /* + * This timed transmit mode is used to enable rate control for the + * flow (QP) at a rate as defined by the rate field of this BD. + * Note: In case subsequent, adjacent packets on the same flow + * don't include a timed transmit BD, they will continue to be + * paced by the transmitter at the same rate as given in this BD. + */ + #define TX_BD_TIMEDTX_FLAGS_KIND_PACE (UINT32_C(0x2) << 6) + #define TX_BD_TIMEDTX_FLAGS_KIND_LAST TX_BD_TIMEDTX_FLAGS_KIND_PACE + /* + * This field exists in all Tx BDs. It doesn't apply to this particular + * BD type since the BD never represents an SGL or inline data; i.e. it + * is only a command. This field must be zero. + */ + /* + * Note that if this field is not zero, a fatal length error will be + * generated as it will be included in the aggregate of SGE lengths for + * the packet. + */ + uint16_t len; + /* + * This field represents the rate of the flow (QP) in terms of KB/s. + * This applies to pace mode timed transmit. + */ + uint32_t rate; + /* + * Applying this rate to a QP will result in this and all subsequent + * packets of the flow being paced at the given rate, until such time + * that the timed transmit mode is either changed or the rate is + * updated in a future packet on the flow. + * This field is applicable only if flags.kind is pace. + */ + #define TX_BD_TIMEDTX_RATE_VAL_MASK UINT32_C(0x1ffffff) + #define TX_BD_TIMEDTX_RATE_VAL_SFT 0 + /* + * This field represents the nano-second time to transmit the + * corresponding packet using SO_TXTIME mode of timed transmit. + * This field is applicable only if flags.kind is so_txtime. + */ + uint32_t tx_time_lo; + uint32_t tx_time_hi; +} tx_bd_timedtx_t, *ptx_bd_timedtx_t; + /* rx_prod_pkt_bd (size:128b/16B) */ typedef struct rx_prod_pkt_bd { @@ -4101,7 +4344,8 @@ typedef struct rx_prod_bfr_bd { * While this is a Byte resolution value, it is often advantageous * to ensure that the buffers provide start on a host cache line. */ - uint64_t addr; + uint32_t addr_lo; + uint32_t addr_hi; } rx_prod_bfr_bd_t, *prx_prod_bfr_bd_t; /* rx_prod_agg_bd (size:128b/16B) */ @@ -4153,7 +4397,8 @@ typedef struct rx_prod_agg_bd { * While this is a Byte resolution value, it is often advantageous * to ensure that the buffers provide start on a host cache line. */ - uint64_t addr; + uint32_t addr_lo; + uint32_t addr_hi; } rx_prod_agg_bd_t, *prx_prod_agg_bd_t; /* cfa_cmpls_cmp_data_msg (size:128b/16B) */ @@ -6349,7 +6594,19 @@ typedef struct rx_pkt_v3_cmpl { * is not applicable. */ #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (UINT32_C(0xb) << 7) - #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 + /* The RSS hash was computed over tunnel context and tunnel ID field. */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_12 (UINT32_C(0xc) << 7) + /* + * The RSS hash was computed over tunnel source IP address, tunnel + * destination IP address, and tunnel ID field. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_13 (UINT32_C(0xd) << 7) + /* + * The RSS hash was computed over tunnel source IP address, tunnel + * destination IP address, tunnel context, and tunnel ID field. + */ + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 (UINT32_C(0xe) << 7) + #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_LAST RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 uint16_t metadata1_payload_offset; /* * If truncation placement is not used, this value indicates the offset @@ -6619,16 +6876,12 @@ typedef struct rx_pkt_v3_cmpl_hi { */ #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9) /* - * Indicates that the IP checksum failed its check in the tunnel + * Indicates that the physical packet is shorter than that claimed + * by the tunnel header length. Valid for GTPv1-U packets. * header. */ - #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR (UINT32_C(0x6) << 9) - /* - * Indicates that the L4 checksum failed its check in the tunnel - * header. - */ - #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR (UINT32_C(0x7) << 9) - #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (UINT32_C(0x6) << 9) + #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR /* * This indicates that there was an error in the inner * portion of the packet when this @@ -6683,17 +6936,7 @@ typedef struct rx_pkt_v3_cmpl_hi { * for TCP. */ #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) - /* - * Indicates that the IP checksum failed its check in the - * inner header. - */ - #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR (UINT32_C(0x9) << 12) - /* - * Indicates that the L4 checksum failed its check in the - * inner header. - */ - #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR (UINT32_C(0xa) << 12) - #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR + #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_LAST RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN /* * This is data from the CFA block as indicated by the meta_format * field. @@ -7623,7 +7866,7 @@ typedef struct rx_tpa_start_v2_cmpl_hi { #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) /* * This indicates that the complete 1's complement checksum was - * calculated for the packet in the affregation. + * calculated for the packet in the aggregation. */ #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200) /* @@ -8602,7 +8845,7 @@ typedef struct rx_tpa_v2_start_cmpl_hi { /* This value indicates what format the metadata field is. */ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ + /* No metadata information. Value is zero. */ #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) /* * The metadata field contains the VLAN tag and TPID value. @@ -8619,7 +8862,7 @@ typedef struct rx_tpa_v2_start_cmpl_hi { * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - GRE = KEY[31:0] -> key field with bit mask. Zero if K = 0 * - IPV4 = 0 (not populated) * - IPV6 = Flow Label[19:0] * - PPPoE = sessionID[15:0] @@ -9511,7 +9754,7 @@ typedef struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD UINT32_C(0x46) /* - * An event from firmware indicating that the RSS capabilites have + * An event from firmware indicating that the RSS capabilities have * changed. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE UINT32_C(0x47) @@ -9529,8 +9772,27 @@ typedef struct hwrm_async_event_cmpl { * doorbell copy region. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR UINT32_C(0x49) + /* + * An event from firmware indicating that the XID partition was not + * allocated/freed by the FW successfully for the request that is + * encapsulated in the HWRM_EXEC_FWD_RESP by the PF driver for VF. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR UINT32_C(0x4a) + /* + * A UDCC session has been modified in the FW. The session_id can be + * used by the driver to retrieve information related to the UDCC + * session. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b) + /* + * Used to notify the host that the firmware has DMA-ed additional + * debug data to the host buffer. This is effectively a producer index + * update. The host driver can utilize this information to determine + * how much of its host buffer has been populated by the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c) /* Maximum Registrable event id. */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x4a) + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x4d) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -9604,8 +9866,11 @@ typedef struct hwrm_async_event_cmpl { ((x) == 0x47 ? "RSS_CHANGE": \ ((x) == 0x48 ? "DOORBELL_PACING_NQ_UPDATE": \ ((x) == 0x49 ? "HW_DOORBELL_RECOVERY_READ_ERROR": \ - ((x) == 0x4a ? "MAX_RGTR_EVENT_ID": \ - "Unknown decode" ))))))))))))))))))))))))))))))))))))))))))) : \ + ((x) == 0x4a ? "CTX_ERROR": \ + ((x) == 0x4b ? "UDCC_SESSION_CHANGE": \ + ((x) == 0x4c ? "DBG_BUF_PRODUCER": \ + ((x) == 0x4d ? "MAX_RGTR_EVENT_ID": \ + "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))) : \ (((x) < 0x100) ? \ ((x) == 0xfe ? "FW_TRACE_MSG": \ ((x) == 0xff ? "HWRM_ERROR": \ @@ -10136,7 +10401,7 @@ typedef struct hwrm_async_event_cmpl_reset_notify { * 16-lsb timestamp (100-msec resolution) * The Maximum Firmware Reset bail out value in the order of 100 * milliseconds. The driver instances will use this value to reinitiate - * the registration process again if the core firmware didn’t set the + * the registration process again if the core firmware didn't set the * state bit. */ uint16_t timestamp_hi; @@ -10748,6 +11013,13 @@ typedef struct hwrm_async_event_cmpl_vf_cfg_change { * If set to 0, then this bit should be ignored. */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE UINT32_C(0x10) + /* + * If this bit is set to 1, then the control of VF was relinquished + * back to the firmware flow manager following the function takeover + * by TruFlow. + * If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE UINT32_C(0x20) } hwrm_async_event_cmpl_vf_cfg_change_t, *phwrm_async_event_cmpl_vf_cfg_change_t; /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ @@ -11241,8 +11513,8 @@ typedef struct hwrm_async_event_cmpl_quiesce_done { #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT 8 /* * Additional information about internal hardware state related to - * idle/quiesce state. QUIESCE may succeed per quiesce_status - * regardless of idle_state_flags. If QUIESCE fails, the host may + * idle/quiesce state. QUIESCE may succeed per quiesce_status + * regardless of idle_state_flags. If QUIESCE fails, the host may * inspect idle_state_flags to determine whether a retry is warranted. */ #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK UINT32_C(0xff0000) @@ -11854,6 +12126,197 @@ typedef struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error { #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR UINT32_C(0x8) } hwrm_async_event_cmpl_hw_doorbell_recovery_read_error_t, *phwrm_async_event_cmpl_hw_doorbell_recovery_read_error_t; +/* hwrm_async_event_cmpl_ctx_error (size:128b/16B) */ + +typedef struct hwrm_async_event_cmpl_ctx_error { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the PF driver + * that firmware fails to allocate/free the contexts requested. This + * message is only valid in the XID partition scheme. Given the start + * xid and the number of contexts in error, the PF driver will figure + * out the corresponding XID partition(s) in error. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR UINT32_C(0x4a) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR + /* Event specific data */ + uint32_t event_data2; + /* Context operation code */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE UINT32_C(0x1) + /* Context alloc failure */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_ALLOC UINT32_C(0x0) + /* Context free failure */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_LAST HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE + /* Number of contexts in error */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_MASK UINT32_C(0xfffe) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_SFT 1 + /* Function ID which the XID partitions are associated with */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_MASK UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_SFT 16 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Starting XID that has error */ + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_MASK UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_SFT 0 +} hwrm_async_event_cmpl_ctx_error_t, *phwrm_async_event_cmpl_ctx_error_t; + +/* hwrm_async_event_udcc_session_change (size:128b/16B) */ + +typedef struct hwrm_async_event_udcc_session_change { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_LAST HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the PF driver + * that firmware has modified a UDCC session. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_LAST HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE + /* Event specific data */ + uint32_t event_data2; + /* UDCC Session id operation code */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_SFT 0 + /* session_id has been created */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_CREATED UINT32_C(0x0) + /* session_id has been freed */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED UINT32_C(0x1) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_LAST HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* UDCC session id which was modified */ + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_SFT 0 +} hwrm_async_event_udcc_session_change_t, *phwrm_async_event_udcc_session_change_t; + +/* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */ + +typedef struct hwrm_async_event_cmpl_dbg_buf_producer { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * Used to notify the host that the firmware has DMA-ed additional + * debug data to the host buffer. This is effectively a producer index + * update. The host driver can utilize this information to determine + * how much of its host buffer has been populated by the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER + /* Event specific data */ + uint32_t event_data2; + /* + * Specifies the current host buffer offset. Data up to this offset + * has been populated by the firmware. For example, if the firmware + * has DMA-ed 8192 bytes to the host buffer, then this field has a + * value of 8192. This field rolls over to zero once the firmware + * writes the last page of the host buffer + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_MASK UINT32_C(0xffffffff) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_SFT 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Type of trace buffer that has been updated. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0 + /* SRT trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE UINT32_C(0x0) + /* SRT2 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE UINT32_C(0x1) + /* CRT trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE UINT32_C(0x2) + /* CRT2 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE UINT32_C(0x3) + /* RIGP0 trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE UINT32_C(0x4) + /* L2 HWRM trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE UINT32_C(0x5) + /* RoCE HWRM trace. */ + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE +} hwrm_async_event_cmpl_dbg_buf_producer_t, *phwrm_async_event_cmpl_dbg_buf_producer_t; + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ typedef struct hwrm_async_event_cmpl_fw_trace_msg { @@ -12036,10 +12499,10 @@ typedef struct hwrm_async_event_cmpl_error_report_base { /* Event specific data */ uint32_t event_data1; /* Indicates the type of error being reported. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 /* Reserved */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED UINT32_C(0x0) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED UINT32_C(0x0) /* * The NIC was subjected to an extended pause storm which caused it * to disable flow control in order to avoid stalling the Tx path. @@ -12052,7 +12515,7 @@ typedef struct hwrm_async_event_cmpl_error_report_base { * it. The pin number on which this signal was received is stored * in event_data2 as pin_id. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL UINT32_C(0x2) /* * There was a low level error with an NVM write or erase. * See nvm_err_type for more details. @@ -12063,12 +12526,12 @@ typedef struct hwrm_async_event_cmpl_error_report_base { * threshold is crossed, it indicates one or more doorbells for * the function were dropped by hardware. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD UINT32_C(0x4) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD UINT32_C(0x4) /* * Indicates the NIC's temperature has crossed one of the thermal * thresholds. */ - #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD UINT32_C(0x5) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD UINT32_C(0x5) /* * Speed change not supported with dual rate transceivers * on this board. @@ -12085,7 +12548,8 @@ typedef struct hwrm_async_event_cmpl_error_report_base { ((x) == 0x3 ? "NVM": \ ((x) == 0x4 ? "DOORBELL_DROP_THRESHOLD": \ ((x) == 0x5 ? "THERMAL_THRESHOLD": \ - "Unknown decode" )))))) : \ + ((x) == 0x6 ? "DUAL_DATA_RATE_NOT_SUPPORTED": \ + "Unknown decode" ))))))) : \ "Unknown decode" ) @@ -12364,7 +12828,7 @@ typedef struct hwrm_async_event_cmpl_error_report_thermal { #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT /* Event specific data. */ uint32_t event_data2; - /* Current temperature. In Celsius */ + /* Current temperature. In Celsius */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK UINT32_C(0xff) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0 /* @@ -12430,6 +12894,60 @@ typedef struct hwrm_async_event_cmpl_error_report_thermal { #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING } hwrm_async_event_cmpl_error_report_thermal_t, *phwrm_async_event_cmpl_error_report_thermal_t; +/* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ + +typedef struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform + * the driver that an error has occurred which may need + * the attention of the administrator. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT UINT32_C(0x45) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Indicates the type of error being reported. */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0 + /* + * Speed change not supported with dual rate transceivers + * on this board. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED UINT32_C(0x6) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED +} hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported_t, *phwrm_async_event_cmpl_error_report_dual_data_rate_not_supported_t; + /* metadata_base_msg (size:64b/8B) */ typedef struct metadata_base_msg { @@ -12884,7 +13402,7 @@ typedef struct tx_doorbell { uint32_t key_idx; /* * BD Index of next BD that will be used to transmit data - * on the TX ring mapped to this door bell. NIC may + * on the TX ring mapped to this door bell. NIC may * read and process all BDs up to, but not including this * index. */ @@ -12892,7 +13410,7 @@ typedef struct tx_doorbell { #define TX_DOORBELL_IDX_SFT 0 /* * This value indicates the type of door bell operation - * that is begin requested. This value is '0' for TX + * that is begin requested. This value is '0' for TX * door bell operations. */ #define TX_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -12908,7 +13426,7 @@ typedef struct rx_doorbell { uint32_t key_idx; /* * BD Index of next BD that will be used for an empty receive - * buffer on the RX ring mapped to this door bell. NIC may + * buffer on the RX ring mapped to this door bell. NIC may * read and process all BDs up to, but not including this * index. */ @@ -12916,7 +13434,7 @@ typedef struct rx_doorbell { #define RX_DOORBELL_IDX_SFT 0 /* * This value indicates the type of door bell operation - * that is begin requested. This value is '1' for RX + * that is begin requested. This value is '1' for RX * door bell operations. */ #define RX_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -12940,20 +13458,20 @@ typedef struct cmpl_doorbell { #define CMPL_DOORBELL_IDX_SFT 0 /* * This indicates if the BDIDX value is valid for this - * update when it is '1'. When it is '0', the BDIDX + * update when it is '1'. When it is '0', the BDIDX * value should be ignored. */ #define CMPL_DOORBELL_IDX_VALID UINT32_C(0x4000000) /* * This bit indicates the new interrupt mask state for the - * interrupt associated with the BDIDX. A '1', means the - * interrupt is to be masked. A '0' indicates the interrupt + * interrupt associated with the BDIDX. A '1', means the + * interrupt is to be masked. A '0' indicates the interrupt * is to be unmasked. */ #define CMPL_DOORBELL_MASK UINT32_C(0x8000000) /* * This value indicates the type of door bell operation - * that is begin requested. This value is '2' for CMP + * that is begin requested. This value is '2' for CMP * door bell operations. */ #define CMPL_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -12980,7 +13498,7 @@ typedef struct status_doorbell { #define STATUS_DOORBELL_IDX_SFT 0 /* * This value indicates the type of door bell operation - * that is begin requested. This value is '3' for Status + * that is begin requested. This value is '3' for Status * door bell operations. */ #define STATUS_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -13007,14 +13525,14 @@ typedef struct push32_doorbell { * A value of 1 is invalid since backup must start with a * long 32B BE. * A value of 2 indicates just the first 32B BE. - * A value of 3 indicates 32B+16B BD. etc. + * A value of 3 indicates 32B+16B BD. etc. * A value of 0 indicates 16x16B BD spaces are consumed. */ #define PUSH32_DOORBELL_SZ_MASK UINT32_C(0xf000000) #define PUSH32_DOORBELL_SZ_SFT 24 /* * This value indicates the type of door bell operation - * that is begin requested. This value is 4 for push + * that is begin requested. This value is 4 for push * door bell operations. */ #define PUSH32_DOORBELL_KEY_MASK UINT32_C(0xf0000000) @@ -13041,7 +13559,7 @@ typedef struct push32_doorbell { #define PUSH32_DOORBELL_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. * * This bit must be set on all push doorbells. @@ -13142,9 +13660,9 @@ typedef struct push32_doorbell { * * This bit must be valid on the first BD of a packet. * - * Packet must be 64B or longer when this flag is set. It is not + * Packet must be 64B or longer when this flag is set. It is not * useful to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already + * CSO or LSO. The intent is that the packet from the host already * has a valid Ethernet CRC on the packet. */ #define PUSH32_DOORBELL_LFLAGS_NOCRC UINT32_C(0x4) @@ -13161,21 +13679,21 @@ typedef struct push32_doorbell { * of the packet associated with this descriptor. * * For outer UDP checksum, global outer UDP checksum TE_NIC register - * needs to be enabled. If the global outer UDP checksum TE_NIC register - * bit is set, outer UDP checksum will be calculated for the following - * cases: - * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner - * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for - * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP - * checksum will not be calculated. - * 2. Packets with lso flag set which implies inner TCP checksum calculation - * as part of LSO operation. + * needs to be enabled. If the global outer UDP checksum TE_NIC + * register bit is set, outer UDP checksum will be calculated for the + * following cases: + * 1. Packets with tcp_udp_chksum flag set to offload checksum for + * inner packet AND the inner packet is TCP/UDP. If the inner packet is + * ICMP for example (non-TCP/UDP), even if the tcp_udp_chksum is set, + * the outer UDP checksum will not be calculated. + * 2. Packets with lso flag set which implies inner TCP checksum + * calculation as part of LSO operation. */ #define PUSH32_DOORBELL_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* * If set to 1, the device will treat this packet with LSO(Large * Send Offload) processing for both normal or encapsulated - * packets, which is a form of TCP segmentation. When this bit + * packets, which is a form of TCP segmentation. When this bit * is 1, the hdr_size and mss fields must be valid. The driver * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum * flags since the controller will replace the appropriate @@ -13190,7 +13708,7 @@ typedef struct push32_doorbell { * 0xffff. * * If set to one when LSO is '1', then the IPID will be treated - * as a 15b number and will be wrapped if it exceeds a value 0f + * as a 15b number and will be wrapped if it exceeds a value of * 0x7fff. */ #define PUSH32_DOORBELL_LFLAGS_IPID_FMT UINT32_C(0x40) @@ -13208,12 +13726,12 @@ typedef struct push32_doorbell { #define PUSH32_DOORBELL_LFLAGS_T_IPID UINT32_C(0x80) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define PUSH32_DOORBELL_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define PUSH32_DOORBELL_LFLAGS_FCOE_CRC UINT32_C(0x200) uint16_t hdr_size; @@ -13296,7 +13814,7 @@ typedef struct push32_doorbell { #define PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) #define PUSH32_DOORBELL_CFA_META_KEY_LAST PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG /* - * This is the data for the push packet. If the packet + * This is the data for the push packet. If the packet * data does not fit in the first pass, data writing * can continue at offset 4 of the doorbell for up to 4 additional * passes for a total data size of 512B maximum. @@ -13350,8 +13868,8 @@ typedef struct hwrm_func_reset_input { * The ID of the VF that this PF is trying to reset. * Only the parent PF shall be allowed to reset a child VF. * - * A parent PF driver shall use this field only when a specific child VF - * is requested to be reset. + * A parent PF driver shall use this field only when a specific child + * VF is requested to be reset. */ uint16_t vf_id; /* This value indicates the level of a function reset. */ @@ -13397,9 +13915,9 @@ typedef struct hwrm_func_reset_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13469,16 +13987,16 @@ typedef struct hwrm_func_getfid_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13551,9 +14069,9 @@ typedef struct hwrm_func_vf_alloc_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13627,9 +14145,9 @@ typedef struct hwrm_func_vf_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13640,7 +14158,7 @@ typedef struct hwrm_func_vf_free_output { ********************/ -/* hwrm_func_vf_cfg_input (size:512b/64B) */ +/* hwrm_func_vf_cfg_input (size:576b/72B) */ typedef struct hwrm_func_vf_cfg_input { /* The HWRM command request type. */ @@ -13676,12 +14194,12 @@ typedef struct hwrm_func_vf_cfg_input { * This bit must be '1' for the mtu field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU UINT32_C(0x1) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU UINT32_C(0x1) /* * This bit must be '1' for the guest_vlan field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN UINT32_C(0x2) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN UINT32_C(0x2) /* * This bit must be '1' for the async_event_cr field to be * configured. @@ -13691,7 +14209,7 @@ typedef struct hwrm_func_vf_cfg_input { * This bit must be '1' for the dflt_mac_addr field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x8) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x8) /* * This bit must be '1' for the num_rsscos_ctxs field to be * configured. @@ -13706,17 +14224,17 @@ typedef struct hwrm_func_vf_cfg_input { * This bit must be '1' for the num_tx_rings field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x40) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x40) /* * This bit must be '1' for the num_rx_rings field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x80) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x80) /* * This bit must be '1' for the num_l2_ctxs field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x100) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x100) /* * This bit must be '1' for the num_vnics field to be * configured. @@ -13726,22 +14244,32 @@ typedef struct hwrm_func_vf_cfg_input { * This bit must be '1' for the num_stat_ctxs field to be * configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x400) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x400) /* * This bit must be '1' for the num_hw_ring_grps field to be * configured. */ #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS UINT32_C(0x800) /* - * This bit must be '1' for the num_tx_key_ctxs field to be - * configured. + * This bit must be '1' for the num_ktls_tx_key_ctxs field to + * be configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_KEY_CTXS UINT32_C(0x1000) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_TX_KEY_CTXS UINT32_C(0x1000) /* - * This bit must be '1' for the num_rx_key_ctxs field to be - * configured. + * This bit must be '1' for the num_ktls_rx_key_ctxs field to + * be configured. */ - #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_KEY_CTXS UINT32_C(0x2000) + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_RX_KEY_CTXS UINT32_C(0x2000) + /* + * This bit must be '1' for the num_quic_tx_key_ctxs field to + * be configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_TX_KEY_CTXS UINT32_C(0x4000) + /* + * This bit must be '1' for the num_quic_rx_key_ctxs field to + * be configured. + */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_RX_KEY_CTXS UINT32_C(0x8000) /* * The maximum transmission unit requested on the function. * The HWRM should make sure that the mtu of @@ -13804,10 +14332,10 @@ typedef struct hwrm_func_vf_cfg_input { #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST UINT32_C(0x2) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of CMPL rings) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST UINT32_C(0x4) /* @@ -13820,10 +14348,10 @@ typedef struct hwrm_func_vf_cfg_input { #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST UINT32_C(0x8) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of ring groups) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST UINT32_C(0x10) /* @@ -13881,11 +14409,17 @@ typedef struct hwrm_func_vf_cfg_input { uint16_t num_stat_ctxs; /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; - /* Number of Tx Key Contexts requested. */ - uint32_t num_tx_key_ctxs; - /* Number of Rx Key Contexts requested. */ - uint32_t num_rx_key_ctxs; - uint8_t unused[4]; + /* Number of KTLS Tx Key Contexts requested. */ + uint32_t num_ktls_tx_key_ctxs; + /* Number of KTLS Rx Key Contexts requested. */ + uint32_t num_ktls_rx_key_ctxs; + /* The number of MSI-X vectors requested for the VF. */ + uint16_t num_msix; + uint8_t unused[2]; + /* Number of QUIC Tx Key Contexts requested. */ + uint32_t num_quic_tx_key_ctxs; + /* Number of QUIC Rx Key Contexts requested. */ + uint32_t num_quic_rx_key_ctxs; } hwrm_func_vf_cfg_input_t, *phwrm_func_vf_cfg_input_t; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -13902,9 +14436,9 @@ typedef struct hwrm_func_vf_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -13957,7 +14491,7 @@ typedef struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } hwrm_func_qcaps_input_t, *phwrm_func_qcaps_input_t; -/* hwrm_func_qcaps_output (size:768b/96B) */ +/* hwrm_func_qcaps_output (size:1088b/136B) */ typedef struct hwrm_func_qcaps_output { /* The specific error status for the command. */ @@ -13969,7 +14503,7 @@ typedef struct hwrm_func_qcaps_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; @@ -14100,7 +14634,8 @@ typedef struct hwrm_func_qcaps_output { /* * If the query is for a VF, then this flag shall be ignored, * If this query is for a PF and this flag is set to 1, - * then the PF has the administrative privilege to configure another PF + * then the PF has the administrative privilege to configure another + * PF. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED UINT32_C(0x40000) /* @@ -14512,7 +15047,7 @@ typedef struct hwrm_func_qcaps_output { #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED UINT32_C(0x2) /* * When this bit is '1', it indicates that KDNet mode is - * supported on the port for this function. This bit is + * supported on the port for this function. This bit is * never set for a VF. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED UINT32_C(0x4) @@ -14567,12 +15102,114 @@ typedef struct hwrm_func_qcaps_output { /* * When this bit is '1', it indicates that the hardware based * link aggregation group (L2 and RoCE) feature is supported. + * This LAG feature is only supported on the THOR2 or newer NIC + * with multiple ports. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED UINT32_C(0x400) - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED UINT32_C(0x800) - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_STEERING_TAG_SUPPORTED UINT32_C(0x1000) - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED UINT32_C(0x2000) - #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED UINT32_C(0x4000) + /* + * When this bit is '1', it indicates all contexts can be stored + * on chip instead of using host based backing store memory. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED UINT32_C(0x800) + /* + * When this bit is '1', it indicates that the HW supports + * using a steering tag in the memory transactions targeting + * L2 or RoCE ring resources. + * Steering Tags are system-specific values that must follow the + * encoding requirements of the hardware platform. On devices that + * support steering to multiple address domains, a value of 0 in + * bit 0 of the steering tag specifies the address is associated + * with the SOC address space, and a value of 1 indicates the + * address is associated with the host address space. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_STEERING_TAG_SUPPORTED UINT32_C(0x1000) + /* + * When this bit is '1', it indicates that driver can enable + * support for an enhanced VF scale. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED UINT32_C(0x2000) + /* + * When this bit is '1', it indicates that FW is capable of + * supporting partition based XID management for KTLS/QUIC + * Tx/Rx Key Context types. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED UINT32_C(0x4000) + /* + * This bit is only valid on the condition that both + * 'ktls_supported' and 'quic_supported' flags are set. When this + * bit is valid, it conveys information below: + * 1. If it is set to '1', it indicates that the firmware allows the + * driver to run KTLS and QUIC concurrently; + * 2. If it is cleared to '0', it indicates that the driver has to + * make sure all crypto connections on all functions are of the + * same type, i.e., either KTLS or QUIC. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED UINT32_C(0x8000) + /* + * When this bit is '1', it indicates that the device supports + * setting a cross TC cap on a scheduler queue. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED UINT32_C(0x10000) + /* + * When this bit is '1', it indicates that the device supports + * setting a per TC cap on a scheduler queue. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED UINT32_C(0x20000) + /* + * When this bit is '1', it indicates that the device supports + * setting a per TC reservation on a scheduler queues. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED UINT32_C(0x40000) + /* + * When this bit is '1', it indicates that firmware supports query + * for statistics related to invalid doorbell errors and drops. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED UINT32_C(0x80000) + /* + * When this bit is '1', it indicates that the device supports + * VF RoCE resource management. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED UINT32_C(0x100000) + /* + * When this bit is '1', it indicates that the device supports + * UDCC management. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDCC_SUPPORTED UINT32_C(0x200000) + /* + * When this bit is '1', it indicates that the device supports Timed + * Transmit TxTime scheduling; this is applicable to L2 flows only. + * It is expected that host software assigns each packet a transmit + * time and posts packets for transmit in time order. NIC hardware + * transmits the packet at time assigned by software. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED UINT32_C(0x400000) + /* + * This bit indicates the method used for the advertisement of the + * max resource limit for the PF and its VFs. + * When this bit is '1', it indicates that the maximum resource + * limits for both RoCE and L2 are software defined. These limits + * are queried using the HWRM backing store qcaps v1 + * and v2(max_num_entries). For RoCE, the resource limits are + * derived from nvm options. For L2, the resources will continue + * to use FW enforced SW limits based on chip config and per PF + * function NVM resource parameters. + * If this bit is '0', the FW will use to legacy behavior. + * For RoCE, the maximum resource values supported by the chip will + * be returned. For L2, the maximum resource values returned will + * be the FW enforced SW limits based on chip config and per PF + * function NVM resource parameters. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED UINT32_C(0x800000) + /* + * When this bit is '1', it indicates that the device supports + * migrating ingress NIC flows to Truflow. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED UINT32_C(0x1000000) + /* + * When this bit is '1', it indicates that the Firmware supports + * query and clear of the port loopback statistics. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_LPBK_STATS_SUPPORTED UINT32_C(0x2000000) uint16_t tunnel_disable_flag; /* * When this bit is '1', it indicates that the VXLAN parsing @@ -14614,10 +15251,79 @@ typedef struct hwrm_func_qcaps_output { * is disabled in hardware */ #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE UINT32_C(0x80) - uint8_t unused_1; + uint16_t xid_partition_cap; + /* + * When this bit is '1', it indicates that FW is capable of + * supporting partition based XID management for Tx crypto + * key contexts. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_TX_CK UINT32_C(0x1) + /* + * When this bit is '1', it indicates that FW is capable of + * supporting partition based XID management for Rx crypto + * key contexts. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_RX_CK UINT32_C(0x2) + /* + * This value uniquely identifies the hardware NIC used by the + * function. The value returned will be the same for all functions. + * A value of 00-00-00-00-00-00-00-00 indicates no device serial number + * is currently configured. This is the same value that is returned by + * PCIe Capability Device Serial Number. + */ + uint8_t device_serial_number[8]; + /* + * This field is only valid in the XID partition mode. It indicates + * the number contexts per partition. + */ + uint16_t ctxs_per_partition; + uint8_t unused_2[2]; + /* + * The maximum number of address vectors that may be allocated across + * all VFs for the function. This is valid only on the PF with VF RoCE + * (SR-IOV) enabled. Returns zero if this command is called on a PF + * with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_av; + /* + * The maximum number of completion queues that may be allocated across + * all VFs for the function. This is valid only on the PF with VF RoCE + * (SR-IOV) enabled. Returns zero if this command is called on a PF + * with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_cq; + /* + * The maximum number of memory regions plus memory windows that may be + * allocated across all VFs for the function. This is valid only on the + * PF with VF RoCE (SR-IOV) enabled. Returns zero if this command is + * called on a PF with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_mrw; + /* + * The maximum number of queue pairs that may be allocated across + * all VFs for the function. This is valid only on the PF with VF RoCE + * (SR-IOV) enabled. Returns zero if this command is called on a PF + * with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_qp; + /* + * The maximum number of shared receive queues that may be allocated + * across all VFs for the function. This is valid only on the PF with + * VF RoCE (SR-IOV) enabled. Returns zero if this command is called on + * a PF with VF RoCE (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_srq; + /* + * The maximum number of GIDs that may be allocated across all VFs for + * the function. This is valid only on the PF with VF RoCE (SR-IOV) + * enabled. Returns zero if this command is called on a PF with VF RoCE + * (SR-IOV) disabled or on a VF. + */ + uint32_t roce_vf_max_gid; + uint8_t unused_3[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -14673,7 +15379,7 @@ typedef struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } hwrm_func_qcfg_input_t, *phwrm_func_qcfg_input_t; -/* hwrm_func_qcfg_output (size:1024b/128B) */ +/* hwrm_func_qcfg_output (size:1280b/160B) */ typedef struct hwrm_func_qcfg_output { /* The specific error status for the command. */ @@ -14685,7 +15391,7 @@ typedef struct hwrm_func_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; @@ -14752,14 +15458,14 @@ typedef struct hwrm_func_qcfg_output { * If the function that is being queried is a PF, then the HWRM shall * set this field to 0 and the HWRM client shall ignore this field. * If the function that is being queried is a VF, then the HWRM shall - * set this field to 1 if the queried VF is trusted, otherwise the HWRM - * shall set this field to 0. + * set this field to 1 if the queried VF is trusted, otherwise the + * HWRM shall set this field to 0. */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF UINT32_C(0x40) /* - * If set to 1, then secure mode is enabled for this function or device. - * If set to 0, then secure mode is disabled (or normal mode) for this - * function or device. + * If set to 1, then secure mode is enabled for this function or + * device. If set to 0, then secure mode is disabled (or normal mode) + * for this function or device. */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED UINT32_C(0x80) /* @@ -14813,6 +15519,12 @@ typedef struct hwrm_func_qcfg_output { * If set to 0, RoCE is disabled on all child VFs. */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV UINT32_C(0x4000) + /* + * When set to 1, indicates the field roce_vnic_id in the structure + * is valid. If this bit is 0, the driver should not use the + * 'roce_vnic_id' field. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ROCE_VNIC_ID_VALID UINT32_C(0x8000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -14894,10 +15606,10 @@ typedef struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff) #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN /* - * This field will indicate number of physical functions on this port_partition. - * HWRM shall return unavail (i.e. value of 0) for this field - * when this command is used to query VF's configuration or - * from older firmware that doesn't support this field. + * This field will indicate number of physical functions on this + * port_partition. HWRM shall return unavail (i.e. value of 0) for this + * field when this command is used to query VF's configuration or from + * older firmware that doesn't support this field. */ uint8_t port_pf_cnt; /* number of PFs is not available */ @@ -15005,7 +15717,10 @@ typedef struct hwrm_func_qcfg_output { #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (UINT32_C(0x0) << 2) /* Admin link state is in forced up mode. */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (UINT32_C(0x1) << 2) - /* Admin link state is in auto mode - follows the physical link state. */ + /* + * Admin link state is in auto mode - follows the physical link + * state. + */ #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO (UINT32_C(0x2) << 2) #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO /* Reserved for future. */ @@ -15047,7 +15762,7 @@ typedef struct hwrm_func_qcfg_output { */ uint16_t alloc_msix; /* - * The number of registered VF’s associated with the PF. This field + * The number of registered VF's associated with the PF. This field * should be ignored when the request received on the VF interface. * This field will be updated on the PF interface to initiate * the unregister request on PF in the HOT Reset Process. @@ -15055,14 +15770,22 @@ typedef struct hwrm_func_qcfg_output { uint16_t registered_vfs; /* * The size of the doorbell BAR in KBytes reserved for L2 including - * any area that is shared between L2 and RoCE. The L2 driver - * should only map the L2 portion of the doorbell BAR. Any rounding + * any area that is shared between L2 and RoCE. The L2 driver + * should only map the L2 portion of the doorbell BAR. Any rounding * of the BAR size to the native CPU page size should be performed - * by the driver. If the value is zero, no special partitioning + * by the driver. If the value is zero, no special partitioning * of the doorbell BAR between L2 and RoCE is required. */ uint16_t l2_doorbell_bar_size_kb; - uint8_t unused_1; + /* + * A bitmask indicating the active endpoints. Each bit represents a + * specific endpoint, with bit 0 indicating EP 0 and bit 3 indicating + * EP 3. For example: + * - a single root system would return 0x1 + * - a 2x8 system (where EPs 0 and 2 are active) would return 0x5 + * - a 4x4 system (where EPs 0-3 are active) would return 0xF + */ + uint8_t active_endpoints; /* * For backward compatibility this field must be set to 1. * Older drivers might look for this field to be 1 before @@ -15070,21 +15793,22 @@ typedef struct hwrm_func_qcfg_output { */ uint8_t always_1; /* - * This GRC address location is used by the Host driver interfaces to poll - * the adapter ready state to re-initiate the registration process again - * after receiving the RESET Notify event. + * This GRC address location is used by the Host driver interfaces to + * poll the adapter ready state to re-initiate the registration process + * again after receiving the RESET Notify event. */ uint32_t reset_addr_poll; /* - * This field specifies legacy L2 doorbell size in KBytes. Drivers should use - * this value to find out the doorbell page offset from the BAR. + * This field specifies legacy L2 doorbell size in KBytes. Drivers + * should use this value to find out the doorbell page offset from the + * BAR. */ uint16_t legacy_l2_db_size_kb; uint16_t svif_info; /* - * This field specifies the source virtual interface of the function being - * queried. Drivers can use this to program svif field in the L2 context - * table + * This field specifies the source virtual interface of the function + * being queried. Drivers can use this to program svif field in the + * L2 context table */ #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 @@ -15146,7 +15870,11 @@ typedef struct hwrm_func_qcfg_output { /* DB page size is 4MB. */ #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_LAST HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB - uint8_t unused_2[2]; + /* + * RoCE VNIC ID for the function. If the function does not have a valid + * RoCE vnic id, then the roce_vnic_id_valid bit in flags is set to 0. + */ + uint16_t roce_vnic_id; /* * Minimum guaranteed bandwidth for the network partition made up * of the caller physical function and all its child virtual @@ -15216,7 +15944,7 @@ typedef struct hwrm_func_qcfg_output { uint8_t unused_3[2]; uint8_t unused_4[2]; /* - * KDNet mode for the port for this function. If a VF, KDNet + * KDNet mode for the port for this function. If a VF, KDNet * mode is always disabled. */ uint8_t port_kdnet_mode; @@ -15231,22 +15959,92 @@ typedef struct hwrm_func_qcfg_output { */ uint8_t kdnet_pcie_function; /* - * Function ID of the KDNET function on this port. If the + * Function ID of the KDNET function on this port. If the * KDNET partition does not exist and the FW supports this * feature, 0xffff will be returned. */ uint16_t port_kdnet_fid; uint8_t unused_5[2]; - /* Number of Tx Key Contexts allocated. */ - uint32_t alloc_tx_key_ctxs; - /* Number of Rx Key Contexts allocated. */ - uint32_t alloc_rx_key_ctxs; - uint8_t unused_6[7]; + /* Number of KTLS Tx Key Contexts allocated. */ + uint32_t num_ktls_tx_key_ctxs; + /* Number of KTLS Rx Key Contexts allocated. */ + uint32_t num_ktls_rx_key_ctxs; + /* + * The LAG idx of this function. The lag_id is per port and the + * valid lag_id is from 0 to 7, if there is no valid lag_id, + * 0xff will be returned. + * This HW lag id is used for Truflow programming only. + */ + uint8_t lag_id; + /* Partition interface for this function. */ + uint8_t parif; + /* + * The LAG ID of a hardware link aggregation group (LAG) whose + * member ports include the port of this function. The LAG was + * previously created using HWRM_FUNC_LAG_CREATE. If the port of this + * function is not a member of any LAG, the fw_lag_id will be 0xff. + */ + uint8_t fw_lag_id; + uint8_t unused_6; + /* Number of QUIC Tx Key Contexts allocated. */ + uint32_t num_quic_tx_key_ctxs; + /* Number of QUIC Rx Key Contexts allocated. */ + uint32_t num_quic_rx_key_ctxs; + /* + * Number of AVs per VF. Only valid for PF. This field is ignored + * when the flag, l2_vf_resource_mgmt, is not set in RoCE + * initialize_fw. + */ + uint32_t roce_max_av_per_vf; + /* + * Number of CQs per VF. Only valid for PF. This field is ignored when + * the flag, l2_vf_resource_mgmt, is not set in RoCE initialize_fw. + */ + uint32_t roce_max_cq_per_vf; + /* + * Number of MR/MWs per VF. Only valid for PF. This field is ignored + * when the flag, l2_vf_resource_mgmt, is not set in RoCE + * initialize_fw. + */ + uint32_t roce_max_mrw_per_vf; + /* + * Number of QPs per VF. Only valid for PF. This field is ignored when + * the flag, l2_vf_resource_mgmt, is not set in RoCE initialize_fw. + */ + uint32_t roce_max_qp_per_vf; + /* + * Number of SRQs per VF. Only valid for PF. This field is ignored + * when the flag, l2_vf_resource_mgmt, is not set in RoCE + * initialize_fw. + */ + uint32_t roce_max_srq_per_vf; + /* + * Number of GIDs per VF. Only valid for PF. This field is ignored + * when the flag, l2_vf_resource_mgmt, is not set in RoCE + * initialize_fw. + */ + uint32_t roce_max_gid_per_vf; + /* + * Bitmap of context types that have XID partition enabled. + * Only valid for PF. + */ + uint16_t xid_partition_cfg; + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Tx crypto key contexts. + */ + #define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1) + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Rx crypto key contexts. + */ + #define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2) + uint8_t unused_7; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -15257,7 +16055,7 @@ typedef struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:1024b/128B) */ +/* hwrm_func_cfg_input (size:1280b/160B) */ typedef struct hwrm_func_cfg_input { /* The HWRM command request type. */ @@ -15350,9 +16148,10 @@ typedef struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST UINT32_C(0x800) /* * This bit only applies to the VF. If this bit is set, the statistic - * context counters will not be cleared when the statistic context is freed - * or a function reset is called on VF. This bit will be cleared when the PF - * is unloaded or a function reset is called on the PF. + * context counters will not be cleared when the statistic context is + * freed or a function reset is called on VF. This bit will be + * cleared when the PF is unloaded or a function reset is called on + * the PF. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC UINT32_C(0x1000) /* @@ -15373,10 +16172,10 @@ typedef struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST UINT32_C(0x4000) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of CMPL rings) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of CMPL rings) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST UINT32_C(0x8000) /* @@ -15389,10 +16188,10 @@ typedef struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST UINT32_C(0x10000) /* * This bit requests that the firmware test to see if all the assets - * requested in this command (i.e. number of ring groups) are available. - * The firmware will return an error if the requested assets are - * not available. The firmware will NOT reserve the assets if they - * are available. + * requested in this command (i.e. number of ring groups) are + * available. The firmware will return an error if the requested + * assets are not available. The firmware will NOT reserve the assets + * if they are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST UINT32_C(0x20000) /* @@ -15497,14 +16296,6 @@ typedef struct hwrm_func_cfg_input { * on this request if the TX_METADATA is enabled for this function. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE UINT32_C(0x40000000) - /* - * If this bit is set to 1, the driver is requesting FW to see if - * all the assets requested in this command (i.e. number of KTLS/ - * QUIC key contexts) are available. The firmware will return an - * error if the requested assets are not available. The firmware - * will NOT reserve the assets if they are available. - */ - #define HWRM_FUNC_CFG_INPUT_FLAGS_KEY_CTX_ASSETS_TEST UINT32_C(0x80000000) uint32_t enables; /* * This bit must be '1' for the admin_mtu field to be @@ -15658,15 +16449,15 @@ typedef struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU UINT32_C(0x20000000) /* - * This bit must be '1' for the number of Tx Key Contexts - * field to be configured. + * This bit must be '1' for the num_ktls_tx_key_ctxs field to be + * configured. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_TX_KEY_CTXS UINT32_C(0x40000000) + #define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_TX_KEY_CTXS UINT32_C(0x40000000) /* - * This bit must be '1' for the number of Rx Key Contexts - * field to be configured. + * This bit must be '1' for the num_ktls_rx_key_ctxs field to be + * configured. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES_RX_KEY_CTXS UINT32_C(0x80000000) + #define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_RX_KEY_CTXS UINT32_C(0x80000000) /* * This field can be used by the admin PF to configure * mtu of foster PFs. @@ -15858,7 +16649,7 @@ typedef struct hwrm_func_cfg_input { * to configure the EVB mode, it sets the evb_mode_cfg_not_supported * flag in HWRM_FUNC_QCAPS command response for the function. * The HWRM takes into account the switching of EVB mode from one to - * another and reconfigure hardware resources as reqiured. The + * another and reconfigure hardware resources as required. The * switching from VEB to VEPA mode requires the disabling of the * loopback traffic. Additionally, source knockouts are handled * differently in VEB and VEPA modes. @@ -15891,7 +16682,10 @@ typedef struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (UINT32_C(0x0) << 2) /* Admin state is forced up. */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (UINT32_C(0x1) << 2) - /* Admin state is in auto mode - is to follow the physical link state. */ + /* + * Admin state is in auto mode - is to follow the physical link + * state. + */ #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO (UINT32_C(0x2) << 2) #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO /* Reserved for future. */ @@ -15908,61 +16702,61 @@ typedef struct hwrm_func_cfg_input { /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the TX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the RX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX crypto engine block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE UINT32_C(0x10) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the TX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE UINT32_C(0x20) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE UINT32_C(0x40) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the RX configurable flow processing - * block. When this bit is ‘0’, this flag has no effect. + * block. When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE UINT32_C(0x80) /* * When this bit is '1', the caller requests to enable a MPC * channel with destination to the primate processor block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE UINT32_C(0x100) /* * When this bit is '1', the caller requests to disable a MPC * channel with destination to the primate processor block. - * When this bit is ‘0’, this flag has no effect. + * When this bit is '0', this flag has no effect. */ #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE UINT32_C(0x200) /* @@ -16050,7 +16844,23 @@ typedef struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; - uint8_t unused_0[4]; + uint32_t flags2; + /* + * If this bit is set to 1, the driver is requesting the firmware + * to see if the assets (i.e., the number of KTLS key contexts) + * requested in this command are available. The firmware will return + * an error if the requested assets are not available. The firmware + * will NOT reserve the assets if they are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST UINT32_C(0x1) + /* + * If this bit is set to 1, the driver is requesting the firmware + * to see if the assets (i.e., the number of QUIC key contexts) + * requested in this command are available. The firmware will return + * an error if the requested assets are not available. The firmware + * will NOT reserve the assets if they are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST UINT32_C(0x2) uint32_t enables2; /* * This bit must be '1' for the kdnet_mode field to be @@ -16062,10 +16872,55 @@ typedef struct hwrm_func_cfg_input { * configured. Legacy controller core FW may silently ignore * the db_page_size programming request through this command. */ - #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2) + #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2) /* - * KDNet mode for the port for this function. If NPAR is - * also configured on this port, it takes precedence. KDNet + * This bit must be '1' for the num_quic_tx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_TX_KEY_CTXS UINT32_C(0x4) + /* + * This bit must be '1' for the num_quic_rx_key_ctxs field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_RX_KEY_CTXS UINT32_C(0x8) + /* + * This bit must be '1' for the roce_max_av_per_vf field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_AV_PER_VF UINT32_C(0x10) + /* + * This bit must be '1' for the roce_max_cq_per_vf field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_CQ_PER_VF UINT32_C(0x20) + /* + * This bit must be '1' for the roce_max_mrw_per_vf field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_MRW_PER_VF UINT32_C(0x40) + /* + * This bit must be '1' for the roce_max_qp_per_vf field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_QP_PER_VF UINT32_C(0x80) + /* + * This bit must be '1' for the roce_max_srq_per_vf field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_SRQ_PER_VF UINT32_C(0x100) + /* + * This bit must be '1' for the roce_max_gid_per_vf field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_GID_PER_VF UINT32_C(0x200) + /* + * This bit must be '1' for the xid_partition_cfg field to be + * configured. Only valid for PF. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_XID_PARTITION_CFG UINT32_C(0x400) + /* + * KDNet mode for the port for this function. If NPAR is + * also configured on this port, it takes precedence. KDNet * mode is ignored for a VF. */ uint8_t port_kdnet_mode; @@ -16108,11 +16963,42 @@ typedef struct hwrm_func_cfg_input { #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_LAST HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB uint8_t unused_1[2]; - /* Number of Tx Key Contexts requested. */ - uint32_t num_tx_key_ctxs; - /* Number of Rx Key Contexts requested. */ - uint32_t num_rx_key_ctxs; - uint8_t unused_2[4]; + /* Number of KTLS Tx Key Contexts requested. */ + uint32_t num_ktls_tx_key_ctxs; + /* Number of KTLS Rx Key Contexts requested. */ + uint32_t num_ktls_rx_key_ctxs; + /* Number of QUIC Tx Key Contexts requested. */ + uint32_t num_quic_tx_key_ctxs; + /* Number of QUIC Rx Key Contexts requested. */ + uint32_t num_quic_rx_key_ctxs; + /* Number of AVs per VF. Only valid for PF. */ + uint32_t roce_max_av_per_vf; + /* Number of CQs per VF. Only valid for PF. */ + uint32_t roce_max_cq_per_vf; + /* Number of MR/MWs per VF. Only valid for PF. */ + uint32_t roce_max_mrw_per_vf; + /* Number of QPs per VF. Only valid for PF. */ + uint32_t roce_max_qp_per_vf; + /* Number of SRQs per VF. Only valid for PF. */ + uint32_t roce_max_srq_per_vf; + /* Number of GIDs per VF. Only valid for PF. */ + uint32_t roce_max_gid_per_vf; + /* + * Bitmap of context types that have XID partition enabled. + * Only valid for PF. + */ + uint16_t xid_partition_cfg; + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Tx crypto key contexts. + */ + #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1) + /* + * When this bit is '1', it indicates that driver enables XID + * partition on Rx crypto key contexts. + */ + #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2) + uint16_t unused_2; } hwrm_func_cfg_input_t, *phwrm_func_cfg_input_t; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -16129,9 +17015,9 @@ typedef struct hwrm_func_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16245,7 +17131,7 @@ typedef struct hwrm_func_qstats_output { uint64_t tx_bcast_pkts; /* * Number of transmitted packets that were discarded due to - * internal NIC resource problems. For transmit, this + * internal NIC resource problems. For transmit, this * can only happen if TMP is configured to allow dropping * in HOL blocking conditions, which is not a normal * configuration. @@ -16272,7 +17158,7 @@ typedef struct hwrm_func_qstats_output { uint64_t rx_bcast_pkts; /* * Number of received packets that were discarded on the function - * due to resource limitations. This can happen for 3 reasons. + * due to resource limitations. This can happen for 3 reasons. * # The BD used for the packet has a bad format. * # There were no BDs available in the ring for the packet. * # There were no BDs available on-chip for the packet. @@ -16303,7 +17189,7 @@ typedef struct hwrm_func_qstats_output { * cleared. Firmware starts the sequence from zero. It increments * the sequence number every time the statistics of the function * are cleared, which can be triggered by a clear statistics request - * or by freeing all statistics contexts of the function. If an user + * or by freeing all statistics contexts of the function. If a user * is interested in knowing if the statistics have been cleared * since the last query, it can keep track of this sequence number * between queries. @@ -16312,9 +17198,9 @@ typedef struct hwrm_func_qstats_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16453,9 +17339,9 @@ typedef struct hwrm_func_qstats_ext_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16520,9 +17406,9 @@ typedef struct hwrm_func_clr_stats_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16586,9 +17472,9 @@ typedef struct hwrm_func_vf_resc_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16660,14 +17546,15 @@ typedef struct hwrm_func_drv_rgtr_input { #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4) /* * When this bit is '1', the function is indicating support of - * 64bit flow handle. The firmware that only supports 64bit flow + * 64bit flow handle. The firmware that only supports 64bit flow * handle should check this bit before allowing processing of - * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware - * with 64bit flow handle support can only be compatible with drivers - * that support 64bit flow handle. The legacy drivers that don't support - * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when - * running with new firmware that only supports 64bit flow handle. The new - * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED + * HWRM_CFA_FLOW_XXX commands from the requesting function as + * firmware with 64bit flow handle support can only be compatible + * with drivers that support 64bit flow handle. The legacy drivers + * that don't support 64bit flow handle won't be able to use + * HWRM_CFA_FLOW_XXX commands when running with new firmware that + * only supports 64bit flow handle. The new firmware support 64bit + * flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED * status to the legacy driver when encounters these commands. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE UINT32_C(0x8) @@ -16695,11 +17582,12 @@ typedef struct hwrm_func_drv_rgtr_input { #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT UINT32_C(0x20) /* * When this bit is 1, the function is indicating the support of the - * Master capability. The Firmware will use this capability to select the - * Master function. The master function will be used to initiate - * designated functionality like error recovery etc… If none of the - * registered PF’s or trusted VF’s indicate this support, then - * firmware will select the 1st registered PF as Master capable instance. + * Master capability. The Firmware will use this capability to select + * the Master function. The master function will be used to initiate + * designated functionality like error recovery etc. If none of the + * registered PF's or trusted VF's indicate this support, then + * firmware will select the 1st registered PF as Master capable + * instance. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT UINT32_C(0x40) /* @@ -16735,6 +17623,14 @@ typedef struct hwrm_func_drv_rgtr_input { * corresponding queue configuration on the RX side */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT UINT32_C(0x400) + /* + * When this bit is 1, the function's driver is indicating to the + * firmware that the Ingress NIC flows will be programmed by the + * TruFlow application and the firmware flow manager should reject + * flow-create commands that programs ingress lookup flows for this + * function. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_INGRESS_NIC_FLOW_MODE UINT32_C(0x800) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -16761,7 +17657,10 @@ typedef struct hwrm_func_drv_rgtr_input { * configured. */ #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD UINT32_C(0x10) - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + /* + * This value indicates the type of OS. The values are based on + * CIM_OperatingSystem.mof file as published by the DMTF. + */ uint16_t os_type; /* Unknown */ #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) @@ -16859,9 +17758,9 @@ typedef struct hwrm_func_drv_rgtr_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -16926,9 +17825,9 @@ typedef struct hwrm_func_drv_unrgtr_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17062,9 +17961,9 @@ typedef struct hwrm_func_buf_rgtr_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17134,9 +18033,9 @@ typedef struct hwrm_func_buf_unrgtr_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17186,7 +18085,17 @@ typedef struct hwrm_func_drv_qver_input { * function. */ uint16_t fid; - uint8_t unused_0[2]; + /* + * This field is used to indicate the driver type. + * L2 or RoCE + */ + uint8_t driver_type; + /* L2 driver version */ + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_L2 UINT32_C(0x0) + /* RoCE driver version */ + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE UINT32_C(0x1) + #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_LAST HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE + uint8_t unused_0; } hwrm_func_drv_qver_input_t, *phwrm_func_drv_qver_input_t; /* hwrm_func_drv_qver_output (size:256b/32B) */ @@ -17200,7 +18109,10 @@ typedef struct hwrm_func_drv_qver_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */ + /* + * This value indicates the type of OS. The values are based on + * CIM_OperatingSystem.mof file as published by the DMTF. + */ uint16_t os_type; /* Unknown */ #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) @@ -17243,9 +18155,9 @@ typedef struct hwrm_func_drv_qver_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17296,7 +18208,7 @@ typedef struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } hwrm_func_resource_qcaps_input_t, *phwrm_func_resource_qcaps_input_t; -/* hwrm_func_resource_qcaps_output (size:576b/72B) */ +/* hwrm_func_resource_qcaps_output (size:704b/88B) */ typedef struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ @@ -17307,13 +18219,22 @@ typedef struct hwrm_func_resource_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */ + /* + * Maximum guaranteed number of VFs supported by PF. Not applicable for + * VFs. + */ uint16_t max_vfs; - /* Maximum guaranteed number of MSI-X vectors supported by function */ + /* Maximum guaranteed number of MSI-X vectors supported by function. */ uint16_t max_msix; - /* Hint of strategy to be used by PF driver to reserve resources for its VF */ + /* + * Hint of strategy to be used by PF driver to reserve resources for + * its VF. + */ uint16_t vf_reservation_strategy; - /* The PF driver should evenly divide its remaining resources among all VFs. */ + /* + * The PF driver should evenly divide its remaining resources among + * all VFs. + */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL UINT32_C(0x0) /* The PF driver should only reserve minimal resources for each VF. */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL UINT32_C(0x1) @@ -17323,7 +18244,7 @@ typedef struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC UINT32_C(0x2) #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC - /* Minimum guaranteed number of RSS/COS contexts */ + /* Minimum guaranteed number of RSS/COS contexts. */ uint16_t min_rsscos_ctx; /* Maximum non-guaranteed number of RSS/COS contexts */ uint16_t max_rsscos_ctx; @@ -17356,32 +18277,42 @@ typedef struct hwrm_func_resource_qcaps_output { /* Maximum non-guaranteed number of ring groups */ uint16_t max_hw_ring_grps; /* - * Maximum number of inputs into the transmit scheduler for this function. - * The number of TX rings assigned to the function cannot exceed this value. + * Maximum number of inputs into the transmit scheduler for this + * function. The number of TX rings assigned to the function cannot + * exceed this value. */ uint16_t max_tx_scheduler_inputs; uint16_t flags; /* * When this bit is '1', it indicates that VF_RESOURCE_CFG supports - * feature to reserve all minimum resources when minimum >= 1, otherwise - * returns an error. + * feature to reserve all minimum resources when minimum >= 1, + * otherwise returns an error. */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED UINT32_C(0x1) - uint8_t unused_0[2]; - /* Minimum guaranteed number of Tx Key Contexts */ - uint32_t min_tx_key_ctxs; - /* Maximum non-guaranteed number of Tx Key Contexts */ - uint32_t max_tx_key_ctxs; - /* Minimum guaranteed number of Rx Key Contexts */ - uint32_t min_rx_key_ctxs; - /* Maximum non-guaranteed number of Rx Key Contexts */ - uint32_t max_rx_key_ctxs; - uint8_t unused_1[3]; + /* Minimum guaranteed number of MSI-X vectors supported by function */ + uint16_t min_msix; + /* Minimum guaranteed number of KTLS Tx Key Contexts */ + uint32_t min_ktls_tx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Tx Key Contexts */ + uint32_t max_ktls_tx_key_ctxs; + /* Minimum guaranteed number of KTLS Rx Key Contexts */ + uint32_t min_ktls_rx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Rx Key Contexts */ + uint32_t max_ktls_rx_key_ctxs; + /* Minimum guaranteed number of QUIC Tx Key Contexts */ + uint32_t min_quic_tx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Tx Key Contexts */ + uint32_t max_quic_tx_key_ctxs; + /* Minimum guaranteed number of QUIC Rx Key Contexts */ + uint32_t min_quic_rx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Rx Key Contexts */ + uint32_t max_quic_rx_key_ctxs; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17392,7 +18323,7 @@ typedef struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:576b/72B) */ +/* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ typedef struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ @@ -17466,18 +18397,27 @@ typedef struct hwrm_func_vf_resource_cfg_input { * error, keep all existing reservations before the call. */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED UINT32_C(0x1) - uint8_t unused_0[2]; - /* Minimum guaranteed number of Tx Key Contexts */ - uint32_t min_tx_key_ctxs; - /* Maximum non-guaranteed number of Tx Key Contexts */ - uint32_t max_tx_key_ctxs; - /* Minimum guaranteed number of Rx Key Contexts */ - uint32_t min_rx_key_ctxs; - /* Maximum non-guaranteed number of Rx Key Contexts */ - uint32_t max_rx_key_ctxs; + /* Minimum guaranteed number of MSI-X vectors for the function */ + uint16_t min_msix; + /* Minimum guaranteed number of KTLS Tx Key Contexts */ + uint32_t min_ktls_tx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Tx Key Contexts */ + uint32_t max_ktls_tx_key_ctxs; + /* Minimum guaranteed number of KTLS Rx Key Contexts */ + uint32_t min_ktls_rx_key_ctxs; + /* Maximum non-guaranteed number of KTLS Rx Key Contexts */ + uint32_t max_ktls_rx_key_ctxs; + /* Minimum guaranteed number of QUIC Tx Key Contexts */ + uint32_t min_quic_tx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Tx Key Contexts */ + uint32_t max_quic_tx_key_ctxs; + /* Minimum guaranteed number of QUIC Rx Key Contexts */ + uint32_t min_quic_rx_key_ctxs; + /* Maximum non-guaranteed number of QUIC Rx Key Contexts */ + uint32_t max_quic_rx_key_ctxs; } hwrm_func_vf_resource_cfg_input_t, *phwrm_func_vf_resource_cfg_input_t; -/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */ +/* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ typedef struct hwrm_func_vf_resource_cfg_output { /* The specific error status for the command. */ @@ -17504,16 +18444,20 @@ typedef struct hwrm_func_vf_resource_cfg_output { uint16_t reserved_stat_ctx; /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; - /* Actual number of Tx Key Contexts reserved */ - uint32_t reserved_tx_key_ctxs; - /* Actual number of Rx Key Contexts reserved */ - uint32_t reserved_rx_key_ctxs; + /* Actual number of KTLS Tx Key Contexts reserved */ + uint32_t reserved_ktls_tx_key_ctxs; + /* Actual number of KTLS Rx Key Contexts reserved */ + uint32_t reserved_ktls_rx_key_ctxs; + /* Actual number of QUIC Tx Key Contexts reserved */ + uint32_t reserved_quic_tx_key_ctxs; + /* Actual number of QUIC Rx Key Contexts reserved */ + uint32_t reserved_quic_rx_key_ctxs; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17597,11 +18541,17 @@ typedef struct hwrm_func_backing_store_qcaps_output { uint16_t cq_entry_size; /* Maximum number of VNIC context entries supported for this function. */ uint16_t vnic_max_vnic_entries; - /* Maximum number of Ring table context entries supported for this function. */ + /* + * Maximum number of Ring table context entries supported for this + * function. + */ uint16_t vnic_max_ring_table_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t vnic_entry_size; - /* Maximum number of statistic context entries supported for this function. */ + /* + * Maximum number of statistic context entries supported for this + * function. + */ uint32_t stat_max_entries; /* Number of bytes that must be allocated for each context entry. */ uint16_t stat_entry_size; @@ -17623,7 +18573,8 @@ typedef struct hwrm_func_backing_store_qcaps_output { * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store + * num_vnics is the number of VNICs allocated in the VNIC backing + * store * num_l2_tx_rings is the number of L2 rings in the QP backing store * num_roce_qps is the number of RoCE QPs in the QP backing store * tqm_min_size is tqm_min_entries_per_ring reported by @@ -17788,13 +18739,18 @@ typedef struct hwrm_func_backing_store_qcaps_output { * function. */ uint32_t rkc_max_entries; + /* + * Additional number of RoCE QP context entries required for this + * function to support fast QP destroy feature. + */ + uint16_t fast_qpmd_qp_num_entries; /* Reserved for future. */ - uint8_t rsvd1[7]; + uint8_t rsvd1[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -17910,12 +18866,12 @@ typedef struct hwrm_func_backing_store_cfg_input { * This bit must be '1' for the vnic fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC UINT32_C(0x8) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC UINT32_C(0x8) /* * This bit must be '1' for the stat fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT UINT32_C(0x10) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT UINT32_C(0x10) /* * This bit must be '1' for the tqm_sp fields to be * configured. @@ -17965,7 +18921,7 @@ typedef struct hwrm_func_backing_store_cfg_input { * This bit must be '1' for the mrav fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV UINT32_C(0x4000) + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV UINT32_C(0x4000) /* * This bit must be '1' for the tim fields to be * configured. @@ -17996,6 +18952,11 @@ typedef struct hwrm_func_backing_store_cfg_input { * fields to be configured. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC UINT32_C(0x100000) + /* + * This bit must be '1' for the number of QPs reserved for fast + * qp modify destroy feature to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP_FAST_QPMD UINT32_C(0x200000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -18005,7 +18966,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 /* QPC page size. */ @@ -18033,7 +18997,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 /* SRQ page size. */ @@ -18061,7 +19028,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 /* CQ page size. */ @@ -18089,7 +19059,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 /* VNIC page size. */ @@ -18117,7 +19090,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 /* Stat page size. */ @@ -18145,7 +19121,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 /* TQM slow path page size. */ @@ -18173,7 +19152,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 /* TQM ring 0 page size. */ @@ -18201,7 +19183,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 /* TQM ring 1 page size. */ @@ -18229,7 +19214,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 /* TQM ring 2 page size. */ @@ -18257,7 +19245,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 /* TQM ring 3 page size. */ @@ -18285,7 +19276,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 /* TQM ring 4 page size. */ @@ -18313,7 +19307,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 /* TQM ring 5 page size. */ @@ -18341,7 +19338,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 /* TQM ring 6 page size. */ @@ -18369,7 +19369,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 /* TQM ring 7 page size. */ @@ -18397,7 +19400,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 /* MR/AV page size. */ @@ -18425,7 +19431,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 /* Timer page size. */ @@ -18492,11 +19501,11 @@ typedef struct hwrm_func_backing_store_cfg_input { * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: - * num_vnics is the number of VNICs allocated in the VNIC backing store - * num_l2_tx_rings is the number of L2 rings in the QP backing store - * num_roce_qps is the number of RoCE QPs in the QP backing store - * tqm_min_size is tqm_min_entries_per_ring reported by - * HWRM_FUNC_BACKING_STORE_QCAPS + * num_vnics is the number of VNICs allocated in the VNIC backing + * store num_l2_tx_rings is the number of L2 rings in the QP backing + * store num_roce_qps is the number of RoCE QPs in the QP backing + * store tqm_min_size is tqm_min_entries_per_ring reported by + * HWRM_FUNC_BACKING_STORE_QCAPS * * Note that TQM ring sizes cannot be extended while the system is * operational. If a PF driver needs to extend a TQM ring, it needs @@ -18782,7 +19791,10 @@ typedef struct hwrm_func_backing_store_cfg_input { #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 /* Tx KTLS context page size. */ @@ -18832,8 +19844,11 @@ typedef struct hwrm_func_backing_store_cfg_input { /* 1GB. */ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_LAST HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G - /* Reserved for future. */ - uint8_t rsvd[2]; + /* + * Number of RoCE QP context entries reserved for this + * function to support fast QP modify destroy feature. + */ + uint16_t qp_num_fast_qpmd_entries; } hwrm_func_backing_store_cfg_input_t, *phwrm_func_backing_store_cfg_input_t; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ @@ -18850,9 +19865,9 @@ typedef struct hwrm_func_backing_store_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -18940,12 +19955,12 @@ typedef struct hwrm_func_backing_store_qcfg_output { * This bit must be '1' for the vnic fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC UINT32_C(0x8) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC UINT32_C(0x8) /* * This bit must be '1' for the stat fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT UINT32_C(0x10) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT UINT32_C(0x10) /* * This bit must be '1' for the tqm_sp fields to be * configured. @@ -18995,7 +20010,7 @@ typedef struct hwrm_func_backing_store_qcfg_output { * This bit must be '1' for the mrav fields to be * configured. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV UINT32_C(0x4000) + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV UINT32_C(0x4000) /* * This bit must be '1' for the tim fields to be * configured. @@ -19026,6 +20041,11 @@ typedef struct hwrm_func_backing_store_qcfg_output { * fields to be configured. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC UINT32_C(0x100000) + /* + * This bit must be '1' for the number of QPs reserved for fast + * qp modify destroy feature to be configured. + */ + #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP_FAST_QPMD UINT32_C(0x200000) /* QPC page size and level. */ uint8_t qpc_pg_size_qpc_lvl; /* QPC PBL indirect levels. */ @@ -19035,7 +20055,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 /* QPC page size. */ @@ -19063,7 +20086,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 /* SRQ page size. */ @@ -19091,7 +20117,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 /* CQ page size. */ @@ -19119,7 +20148,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 /* VNIC page size. */ @@ -19147,7 +20179,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 /* Stat page size. */ @@ -19175,7 +20210,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 /* TQM slow path page size. */ @@ -19203,7 +20241,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 /* TQM ring 0 page size. */ @@ -19231,7 +20272,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 /* TQM ring 1 page size. */ @@ -19259,7 +20303,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 /* TQM ring 2 page size. */ @@ -19287,7 +20334,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 /* TQM ring 3 page size. */ @@ -19315,7 +20365,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 /* TQM ring 4 page size. */ @@ -19343,7 +20396,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 /* TQM ring 5 page size. */ @@ -19371,7 +20427,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 /* TQM ring 6 page size. */ @@ -19399,7 +20458,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 /* TQM ring 7 page size. */ @@ -19427,7 +20489,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 /* MR/AV page size. */ @@ -19455,7 +20520,10 @@ typedef struct hwrm_func_backing_store_qcfg_output { #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 UINT32_C(0x2) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 /* Timer page size. */ @@ -19739,10 +20807,15 @@ typedef struct hwrm_func_backing_store_qcfg_output { /* 1GB. */ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_LAST HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G - uint8_t unused_1[5]; + /* + * Number of RoCE QP context entries required for this + * function to support fast QP modify destroy feature. + */ + uint16_t qp_num_fast_qpmd_entries; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as 1 + * is completely written to RAM. This field should be read as 1 * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field @@ -20106,7 +21179,7 @@ typedef struct hwrm_error_recovery_qcfg_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field @@ -20169,9 +21242,9 @@ typedef struct hwrm_func_echo_response_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20317,9 +21390,9 @@ typedef struct hwrm_func_ptp_pin_qcfg_output { uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20507,9 +21580,9 @@ typedef struct hwrm_func_ptp_pin_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20637,7 +21710,9 @@ typedef struct hwrm_func_ptp_cfg_input { #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K UINT32_C(0x2) /* 10Mhz sync in frequency. */ #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M UINT32_C(0x3) - #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M + /* 25Mhz sync in frequency. */ + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M UINT32_C(0x4) + #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_LAST HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M uint8_t unused_0[3]; /* * Period in nanoseconds (ns) for external signal @@ -20689,9 +21764,9 @@ typedef struct hwrm_func_ptp_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20776,9 +21851,9 @@ typedef struct hwrm_func_ptp_ts_query_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -20920,9 +21995,9 @@ typedef struct hwrm_func_ptp_ext_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -21017,9 +22092,9 @@ typedef struct hwrm_func_ptp_ext_qcfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -21030,7 +22105,7 @@ typedef struct hwrm_func_ptp_ext_qcfg_output { ***************************/ -/* hwrm_func_key_ctx_alloc_input (size:320b/40B) */ +/* hwrm_func_key_ctx_alloc_input (size:384b/48B) */ typedef struct hwrm_func_key_ctx_alloc_input { /* The HWRM command request type. */ @@ -21063,9 +22138,26 @@ typedef struct hwrm_func_key_ctx_alloc_input { uint64_t resp_addr; /* Function ID. */ uint16_t fid; - /* Number of Key Contexts to be allocated. */ + /* + * Number of Key Contexts to be allocated. + * When running in the XID partition mode, if the call is made by + * a VF driver, this field specifies the number of XIDs requested + * by the VF driver. The XID partitions are managed by the PF + * driver in XID partition mode and the VF command will be + * redirected to the PF driver. The PF driver may reduce this + * number if it cannot allocate a big enough block of XID + * partitions to satisfy the request. + * This field must not exceed the maximum batch size specified in + * the max_key_ctxs_alloc field of the HWRM_FUNC_QCAPS response, + * must not be zero, and must be integer multiples of the + * partition size specified in the ctxs_per_partition field of + * the HWRM_FUNC_QCAPS response. + */ uint16_t num_key_ctxs; - /* DMA buffer size in bytes. */ + /* + * DMA buffer size in bytes. This field in invalid in the XID + * partition mode. + */ uint32_t dma_bufr_size_bytes; /* Key Context type. */ uint8_t key_ctx_type; @@ -21079,11 +22171,24 @@ typedef struct hwrm_func_key_ctx_alloc_input { #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3) #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_LAST HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX uint8_t unused_0[7]; - /* Host DMA address to send back KTLS context IDs. */ + /* + * Host DMA address to send back KTLS context IDs. This field is + * invalid in the XID partition mode. + */ uint64_t host_dma_addr; + /* + * This field is only used by the PF driver that manages the XID + * partitions. This field specifies the starting XID of one or + * more contiguous XID partitions allocated by the PF driver. + * This field is not used by the VF driver. + * If the call is successful, this starting XID value will be + * returned in the partition_start_xid field of the response. + */ + uint32_t partition_start_xid; + uint8_t unused_1[4]; } hwrm_func_key_ctx_alloc_input_t, *phwrm_func_key_ctx_alloc_input_t; -/* hwrm_func_key_ctx_alloc_output (size:128b/16B) */ +/* hwrm_func_key_ctx_alloc_output (size:192b/24B) */ typedef struct hwrm_func_key_ctx_alloc_output { /* The specific error status for the command. */ @@ -21094,7 +22199,7 @@ typedef struct hwrm_func_key_ctx_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Actual number of Key Contexts allocated. */ + /* Number of Key Contexts that have been allocated. */ uint16_t num_key_ctxs_allocated; /* Control flags. */ uint8_t flags; @@ -21102,21 +22207,116 @@ typedef struct hwrm_func_key_ctx_alloc_output { * When set, it indicates that all key contexts allocated by this * command are contiguous. As a result, the driver has to read the * start context ID from the first entry of the DMA data buffer - * and figures out the end context ID by “start context ID + - * num_key_ctxs_allocated - 1”. + * and figures out the end context ID by 'start context ID + + * num_key_ctxs_allocated - 1'. In XID partition mode, + * this bit should always be set. */ #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS UINT32_C(0x1) - uint8_t unused_0[4]; + uint8_t unused_0; + /* + * This field is only valid in the XID partition mode. It indicates + * the starting XID that has been allocated. + */ + uint32_t partition_start_xid; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } hwrm_func_key_ctx_alloc_output_t, *phwrm_func_key_ctx_alloc_output_t; +/************************** + * hwrm_func_key_ctx_free * + **************************/ + + +/* hwrm_func_key_ctx_free_input (size:256b/32B) */ + +typedef struct hwrm_func_key_ctx_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function ID. */ + uint16_t fid; + /* Key Context type. */ + uint8_t key_ctx_type; + /* KTLS Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0) + /* KTLS Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1) + /* QUIC Tx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2) + /* QUIC Rx Key Context type. */ + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3) + #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_LAST HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX + uint8_t unused_0; + /* Starting XID of the partition that needs to be freed. */ + uint32_t partition_start_xid; + /* + * Number of entries to be freed. + * When running in the XID partition mode, this field is only + * used by the PF driver that manages the XID partitions. + * The PF driver specifies the number of XIDs to be freed and + * this number is always equal to the number of XIDs previously + * allocated successfully using HWRM_FUNC_KEY_CTX_ALLOC. + * This field is not used by the VF driver. + */ + uint16_t num_entries; + uint8_t unused_1[6]; +} hwrm_func_key_ctx_free_input_t, *phwrm_func_key_ctx_free_input_t; + +/* hwrm_func_key_ctx_free_output (size:128b/16B) */ + +typedef struct hwrm_func_key_ctx_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t rsvd0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been completely + * written. When writing a command completion or response to + * an internal processor, the order of writes has to be such + * that this field is written last. + */ + uint8_t valid; +} hwrm_func_key_ctx_free_output_t, *phwrm_func_key_ctx_free_output_t; + /********************************** * hwrm_func_backing_store_cfg_v2 * **********************************/ @@ -21158,39 +22358,53 @@ typedef struct hwrm_func_backing_store_cfg_v2_input { /* Queue pair. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) /* SQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) /* RQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) /* SRQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) /* CQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_XID_PARTITION UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff) #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID @@ -21199,8 +22413,14 @@ typedef struct hwrm_func_backing_store_cfg_v2_input { * which means "0" indicates the first instance. For backing * stores with single instance only, leave this field to 0. * 1. If the backing store type is MPC TQM ring, use the following - * instance value to MPC client mapping: + * instance value to map to MPC clients: * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) + * 2. If the backing store type is TBL_SCOPE, use the following + * instance value to map to table scope regions: + * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) + * 3. If the backing store type is XID partition, use the following + * instance value to map to context types: + * TX_CK (0), RX_CK (1) */ uint16_t instance; /* Control flags. */ @@ -21227,10 +22447,10 @@ typedef struct hwrm_func_backing_store_cfg_v2_input { * The size specified in the command will be the new size to be * configured. The operation is only valid when the specific backing * store has been configured before. Otherwise, the firmware will - * return an error. The driver needs to zero out the “entry_size”, - * “flags”, “page_dir”, and “page_size_pbl_level” fields, and the + * return an error. The driver needs to zero out the 'entry_size', + * 'flags', 'page_dir', and 'page_size_pbl_level' fields, and the * firmware will ignore these inputs. Further, the firmware expects - * the “num_entries” and any valid split entries to be no less than + * the 'num_entries' and any valid split entries to be no less than * the initial value that has been configured. If not, it will * return an error code. */ @@ -21295,7 +22515,9 @@ typedef struct hwrm_func_backing_store_cfg_v2_input { * | SRQ | srq_split_entries | * | CQ | cq_split_entries | * | VINC | vnic_split_entries | - * | MRAV | marv_split_entries | + * | MRAV | mrav_split_entries | + * | TS | ts_split_entries | + * | CK | ck_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -21320,7 +22542,7 @@ typedef struct hwrm_func_backing_store_cfg_v2_output { uint8_t rsvd0[7]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -21370,46 +22592,69 @@ typedef struct hwrm_func_backing_store_qcfg_v2_input { /* Queue pair. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TKC UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) /* SQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) /* RQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) /* SRQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) /* CQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* VF XID partition in-use table. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_XID_PARTITION_TABLE UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff) - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID /* * Instance of the backing store type. It is zero-based, * which means "0" indicates the first instance. For backing * stores with single instance only, leave this field to 0. + * 1. If the backing store type is MPC TQM ring, use the following + * instance value to map to MPC clients: + * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) + * 2. If the backing store type is TBL_SCOPE, use the following + * instance value to map to table scope regions: + * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) + * 3. If the backing store type is XID partition, use the following + * instance value to map to context types: + * TX_CK (0), RX_CK (1) */ uint16_t instance; uint8_t rsvd[4]; @@ -21429,33 +22674,47 @@ typedef struct hwrm_func_backing_store_qcfg_v2_output { /* Type of backing store to be configured. */ uint16_t type; /* Queue pair. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP UINT32_C(0x0) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TKC UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_XID_PARTITION UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID UINT32_C(0xffff) #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID @@ -21463,6 +22722,15 @@ typedef struct hwrm_func_backing_store_qcfg_v2_output { * Instance of the backing store type. It is zero-based, * which means "0" indicates the first instance. For backing * stores with single instance only, leave this field to 0. + * 1. If the backing store type is MPC TQM ring, use the following + * instance value to map to MPC clients: + * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) + * 2. If the backing store type is TBL_SCOPE, use the following + * instance value to map to table scope regions: + * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) + * 3. If the backing store type is XID partition, use the following + * instance value to map to context types: + * TX_CK (0), RX_CK (1) */ uint16_t instance; /* Control flags. */ @@ -21526,7 +22794,9 @@ typedef struct hwrm_func_backing_store_qcfg_v2_output { * | SRQ | srq_split_entries | * | CQ | cq_split_entries | * | VINC | vnic_split_entries | - * | MRAV | marv_split_entries | + * | MRAV | mrav_split_entries | + * | TS | ts_split_entries | + * | CK | ck_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -21538,7 +22808,7 @@ typedef struct hwrm_func_backing_store_qcfg_v2_output { uint8_t rsvd2[7]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -21555,7 +22825,12 @@ typedef struct qpc_split_entries { uint32_t qp_num_l2_entries; /* Number of QP1 entries. */ uint32_t qp_num_qp1_entries; - uint64_t rsvd; + /* + * Number of RoCE QP context entries required for this + * function to support fast QP modify destroy feature. + */ + uint32_t qp_num_fast_qpmd_entries; + uint32_t rsvd; } qpc_split_entries_t, *pqpc_split_entries_t; /* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ @@ -21598,6 +22873,37 @@ typedef struct mrav_split_entries { uint64_t rsvd2; } mrav_split_entries_t, *pmrav_split_entries_t; +/* Common structure to cast TBL_SCOPE split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is TBL_SCOPE. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* ts_split_entries (size:128b/16B) */ + +typedef struct ts_split_entries { + /* Max number of TBL_SCOPE region entries (QCAPS). */ + uint32_t region_num_entries; + /* tsid to configure (CFG). */ + uint8_t tsid; + /* + * Lkup static bucket count (power of 2). + * Array is indexed by enum cfa_dir + */ + uint8_t lkup_static_bkt_cnt_exp[2]; + uint8_t rsvd; + uint64_t rsvd2; +} ts_split_entries_t, *pts_split_entries_t; + +/* Common structure to cast crypto key split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is TX_CK or RX_CK. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* ck_split_entries (size:128b/16B) */ + +typedef struct ck_split_entries { + /* + * Number of QUIC backing store entries. That means the number of KTLS + * backing store entries is the difference between this number and the + * total number of crypto key entries. + */ + uint32_t num_quic_entries; + uint32_t rsvd; + uint64_t rsvd2; +} ck_split_entries_t, *pck_split_entries_t; + /************************************ * hwrm_func_backing_store_qcaps_v2 * ************************************/ @@ -21639,39 +22945,53 @@ typedef struct hwrm_func_backing_store_qcaps_v2_input { /* Queue pair. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM UINT32_C(0xf) - /* Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TKC UINT32_C(0x13) - /* Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15) /* SQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) /* RQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) /* SRQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) /* CQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_XID_PARTITION UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID UINT32_C(0xffff) #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID @@ -21694,39 +23014,53 @@ typedef struct hwrm_func_backing_store_qcaps_v2_output { /* Queue pair. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QP UINT32_C(0x0) /* Shared receive queue. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1) /* Completion queue. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ UINT32_C(0x2) /* Virtual NIC. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3) /* Statistic context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT UINT32_C(0x4) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT UINT32_C(0x4) /* Slow-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5) /* Fast-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6) /* Memory Region and Memory Address Vector Context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe) /* TIM. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM UINT32_C(0xf) - /* KTLS Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TKC UINT32_C(0x13) - /* KTLS Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RKC UINT32_C(0x14) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM UINT32_C(0xf) + /* Tx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TX_CK UINT32_C(0x13) + /* Rx crypto key. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RX_CK UINT32_C(0x14) /* Mid-path TQM ring. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15) /* SQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16) /* RQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17) /* SRQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18) /* CQ Doorbell shadow region. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) - /* QUIC Tx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_TKC UINT32_C(0x1a) - /* QUIC Rx key context. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QUIC_RKC UINT32_C(0x1b) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19) + /* CFA table scope context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TBL_SCOPE UINT32_C(0x1c) + /* XID partition context. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_XID_PARTITION UINT32_C(0x1d) + /* SRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT_TRACE UINT32_C(0x1e) + /* SRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT2_TRACE UINT32_C(0x1f) + /* CRT trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT_TRACE UINT32_C(0x20) + /* CRT2 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT2_TRACE UINT32_C(0x21) + /* RIGP0 trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RIGP0_TRACE UINT32_C(0x22) + /* L2 HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23) + /* RoCE HWRM trace. */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24) /* Invalid type. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID UINT32_C(0xffff) #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_LAST HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID @@ -21736,23 +23070,46 @@ typedef struct hwrm_func_backing_store_qcaps_v2_output { uint32_t flags; /* * When set, it indicates the context type should be initialized - * with the “ctx_init_value” at the specified offset. + * with the 'ctx_init_value' at the specified offset. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT UINT32_C(0x1) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT UINT32_C(0x1) /* When set, it indicates the context type is valid. */ - #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID UINT32_C(0x2) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID UINT32_C(0x2) /* * When set, it indicates the region for this type is not a regular * context memory but a driver managed memory that is created, * initialized and managed by the driver. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY UINT32_C(0x4) + /* + * When set, it indicates the support of the following capability + * that is specific to the QP type: + * - For 2-port adapters, the ability to extend the RoCE QP + * entries configured on a PF, during some network events such as + * Link Down. These additional entries count is included in the + * advertised 'max_num_entries'. + * - The count of RoCE QP entries, derived from 'max_num_entries' + * (max_num_entries - qp_num_qp1_entries - qp_num_l2_entries - + * qp_num_fast_qpmd_entries, note qp_num_fast_qpmd_entries is + * always zero when QPs are pseudo-statically allocated), includes + * the count of QPs that can be migrated from the other PF (e.g., + * during network link down). Therefore, during normal operation + * when both PFs are active, the supported number of RoCE QPs for + * each of the PF is half of the advertised value. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC UINT32_C(0x8) /* * Bit map of the valid instances associated with the * backing store type. * 1. If the backing store type is MPC TQM ring, use the following - * bit to MPC client mapping: + * bits to map to MPC clients: * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) + * 2. If the backing store type is TBL_SCOPE, use the following + * bits to map to table scope regions: + * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3) + * 3. If the backing store type is VF XID partition in-use table, use + * the following bits to map to context types: + * TX_CK (0), RX_CK (1) */ uint32_t instance_bit_map; /* @@ -21799,7 +23156,37 @@ typedef struct hwrm_func_backing_store_qcaps_v2_output { * | 4 | All four split entries have valid data. | */ uint8_t subtype_valid_cnt; - uint8_t rsvd2; + /* + * Bitmap that indicates if each of the 'split_entry' denotes an + * exact count (i.e., min = max). When the exact count bit is set, + * it indicates the exact number of entries as advertised has to be + * configured. The 'split_entry' to be set to contain exact count by + * this bitmap needs to be a valid split entry specified by + * 'subtype_valid_cnt'. + */ + uint8_t exact_cnt_bit_map; + /* + * When this bit is '1', it indicates 'split_entry_0' contains + * an exact count. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT UINT32_C(0x1) + /* + * When this bit is '1', it indicates 'split_entry_1' contains + * an exact count. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT UINT32_C(0x2) + /* + * When this bit is '1', it indicates 'split_entry_2' contains + * an exact count. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT UINT32_C(0x4) + /* + * When this bit is '1', it indicates 'split_entry_3' contains + * an exact count. + */ + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT UINT32_C(0x8) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_MASK UINT32_C(0xf0) + #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_SFT 4 /* * Split entry #0. Note that the four split entries (as a group) * must be cast to a type-specific data structure first before @@ -21811,7 +23198,8 @@ typedef struct hwrm_func_backing_store_qcaps_v2_output { * | SRQ | srq_split_entries | * | CQ | cq_split_entries | * | VINC | vnic_split_entries | - * | MRAV | marv_split_entries | + * | MRAV | mrav_split_entries | + * | TS | ts_split_entries | */ uint32_t split_entry_0; /* Split entry #1. */ @@ -21823,7 +23211,7 @@ typedef struct hwrm_func_backing_store_qcaps_v2_output { uint8_t rsvd3[3]; /* * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be + * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been completely * written. When writing a command completion or response to * an internal processor, the order of writes has to be such @@ -21890,7 +23278,7 @@ typedef struct hwrm_func_dbr_pacing_cfg_input { */ #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID UINT32_C(0x2) /* - * Specify primary function’s NQ ID to receive the doorbell pacing + * Specify primary function's NQ ID to receive the doorbell pacing * threshold crossing events. */ uint32_t primary_nq_id; @@ -21916,7 +23304,7 @@ typedef struct hwrm_func_dbr_pacing_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -22088,9 +23476,10 @@ typedef struct hwrm_func_dbr_pacing_qcfg_output { */ uint8_t dbr_throttling_aeq_arm_reg_val; uint8_t unused_3[3]; - uint32_t dbr_stat_db_max_fifo_depth; + /* This field indicates the maximum depth of the doorbell FIFO. */ + uint32_t dbr_stat_db_max_fifo_depth; /* - * Specifies primary function’s NQ ID. + * Specifies primary function's NQ ID. * A value of 0xFFFF FFFF indicates NQ ID is invalid. */ uint32_t primary_nq_id; @@ -22102,7 +23491,7 @@ typedef struct hwrm_func_dbr_pacing_qcfg_output { uint8_t unused_4[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -22163,7 +23552,7 @@ typedef struct hwrm_func_dbr_pacing_broadcast_event_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -22258,9 +23647,9 @@ typedef struct hwrm_func_dbr_pacing_nqlist_query_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22328,7 +23717,7 @@ typedef struct hwrm_func_dbr_recovery_completed_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -22433,9 +23822,9 @@ typedef struct hwrm_func_synce_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22515,14 +23904,817 @@ typedef struct hwrm_func_synce_qcfg_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } hwrm_func_synce_qcfg_output_t, *phwrm_func_synce_qcfg_output_t; +/************************ + * hwrm_func_lag_create * + ************************/ + + +/* hwrm_func_lag_create_input (size:192b/24B) */ + +typedef struct hwrm_func_lag_create_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t enables; + /* + * This bit must be '1' for the active_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x1) + /* + * This bit must be '1' for the member_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x2) + /* This bit must be '1' for the aggr_mode field to be configured. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_AGGR_MODE UINT32_C(0x4) + /* rsvd1 is 5 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xf8) + #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_SFT 3 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. + * + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[4]; +} hwrm_func_lag_create_input_t, *phwrm_func_lag_create_input_t; + +/* hwrm_func_lag_create_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_create_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * LAG ID of the created LAG. This LAG ID will also be returned + * in the HWRM_FUNC_QCFG response of all member ports. + */ + uint8_t fw_lag_id; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_lag_create_output_t, *phwrm_func_lag_create_output_t; + +/************************ + * hwrm_func_lag_update * + ************************/ + + +/* hwrm_func_lag_update_input (size:192b/24B) */ + +typedef struct hwrm_func_lag_update_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Link aggregation group ID of the LAG to be updated. */ + uint8_t fw_lag_id; + uint8_t enables; + /* + * This bit must be '1' for the active_port_map field to be + * updated. + */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x1) + /* + * This bit must be '1' for the member_port_map field to be + * updated. + */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x2) + /* This bit must be '1' for the aggr_mode field to be updated. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_AGGR_MODE UINT32_C(0x4) + /* rsvd1 is 5 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xf8) + #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_SFT 3 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. + * + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[3]; +} hwrm_func_lag_update_input_t, *phwrm_func_lag_update_input_t; + +/* hwrm_func_lag_update_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_update_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_lag_update_output_t, *phwrm_func_lag_update_output_t; + +/********************** + * hwrm_func_lag_free * + **********************/ + + +/* hwrm_func_lag_free_input (size:192b/24B) */ + +typedef struct hwrm_func_lag_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Link aggregation group ID of the LAG to be freed. */ + uint8_t fw_lag_id; + uint8_t unused_0[7]; +} hwrm_func_lag_free_input_t, *phwrm_func_lag_free_input_t; + +/* hwrm_func_lag_free_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_lag_free_output_t, *phwrm_func_lag_free_output_t; + +/********************** + * hwrm_func_lag_qcfg * + **********************/ + + +/* hwrm_func_lag_qcfg_input (size:192b/24B) */ + +typedef struct hwrm_func_lag_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Link aggregation group ID of the LAG to be queried. */ + uint8_t fw_lag_id; + uint8_t unused_0[7]; +} hwrm_func_lag_qcfg_input_t, *phwrm_func_lag_qcfg_input_t; + +/* hwrm_func_lag_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. The active_port_map must always be a subset of the + * member_port_map. An active port is eligible to send and receive + * traffic. + * + * If the LAG mode is active-backup, only one port can be an active + * port at a given time. All other ports in the member_port_map that + * are not the active port are backup port. When the active port + * fails, another member port takes over to become the active port. + * The driver should use HWRM_FUNC_LAG_UPDATE to update + * the active_port_map by only setting the port bit of the new active + * port. + * + * In active-active, balance_xor or 802_3_ad mode, all member ports + * can be active ports. If the driver determines that an active + * port is down or unable to function, it should use + * HWRM_FUNC_LAG_UPDATE to update the active_port_map by clearing + * the port bit that has failed. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device. Ports are numbered + * from 0 to n - 1 on a device with n ports. The number of front panel + * ports is specified in the port_cnt field of the HWRM_PORT_PHY_QCAPS + * response. There must be at least 2 ports in the member ports and + * each must not be a member of another LAG. Note that on a 4-port + * device, there can be either 2 ports or 4 ports in the member ports. + * Using 3 member ports is not supported. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_lag_qcfg_output_t, *phwrm_func_lag_qcfg_output_t; + +/************************** + * hwrm_func_lag_mode_cfg * + **************************/ + + +/* hwrm_func_lag_mode_cfg_input (size:192b/24B) */ + +typedef struct hwrm_func_lag_mode_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t enables; + /* + * This bit must be '1' for the link aggregation enable or + * disable flags to be configured. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_FLAGS UINT32_C(0x1) + /* + * This bit must be '1' for the active_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x2) + /* + * This bit must be '1' for the member_port_map field to be + * configured. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x4) + /* This bit must be '1' for the aggr_mode field to be configured. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_AGGR_MODE UINT32_C(0x8) + /* This bit must be '1' for the lag id field to be configured. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_LAG_ID UINT32_C(0x10) + /* rsvd1 is 3 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xe0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_SFT 5 + uint8_t flags; + /* + * If this bit is set to 1, the driver is requesting FW to disable + * link aggregation feature during run time. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_DISABLE UINT32_C(0x1) + /* + * If this bit is set to 1, the driver is requesting FW to enable + * link aggregation feature during run time. + */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_ENABLE UINT32_C(0x2) + /* rsvd2 is 6 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_MASK UINT32_C(0xfc) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_SFT 2 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "active port" is one of member ports which is eligible to + * send or receive the traffic. + * In the active-backup mode, only one member port is active port at + * any given time. If the active port fails, another member port + * automatically takes over the active role to ensure continuous + * network connectivity. + * In the active-active, balance_xor or 802_3_ad mode, all member ports + * could be active port, if link status on one port is down, driver + * needs to send the NIC a new active-port bitmap with marking this + * port as not active port. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "member port" refers to a front panel port that is added to + * the bond group as a slave device. These member ports are combined to + * create a logical bond interface. + * For a 4-port NIC, the LAG member port combination can consist of + * either two ports or four ports. However, it is important to note + * that the case with three ports in the same lag group is not + * supported. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. There could be a case to use multiple LAG groups, + * for example, if the NIC has four front panel ports, the lag feature + * can use up to two LAG groups, with two ports assigned to each group. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd4 is 4 b */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD + /* Link aggregation group idx being used. */ + uint8_t lag_id; + uint8_t unused_0[2]; +} hwrm_func_lag_mode_cfg_input_t, *phwrm_func_lag_mode_cfg_input_t; + +/* hwrm_func_lag_mode_cfg_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_mode_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Link aggregation group idx being used. */ + uint8_t lag_id; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_lag_mode_cfg_output_t, *phwrm_func_lag_mode_cfg_output_t; + +/*************************** + * hwrm_func_lag_mode_qcfg * + ***************************/ + + +/* hwrm_func_lag_mode_qcfg_input (size:192b/24B) */ + +typedef struct hwrm_func_lag_mode_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} hwrm_func_lag_mode_qcfg_input_t, *phwrm_func_lag_mode_qcfg_input_t; + +/* hwrm_func_lag_mode_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_func_lag_mode_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t aggr_enabled; + /* + * This flag is used to query whether link aggregation is enabled + * or disabled during run time. + */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_ENABLED UINT32_C(0x1) + /* rsvd1 is 7 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_MASK UINT32_C(0xfe) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_SFT 1 + /* + * This is the bitmap of all active ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "active port" is one of member ports which is eligible to + * send or receive the traffic. + * In the active-backup mode, only one member port is active port at + * any given time. If the active port fails, another member port + * automatically takes over the active role to ensure continuous + * network connectivity. + * In the active-active, balance_xor or 802_3_ad mode, all member ports + * could be active port, if link status on one port is down, driver + * needs to send the NIC a new active-port bitmap with marking this + * port as not active port. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. + */ + uint8_t active_port_map; + /* If this bit is set to '1', the port0 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag active port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd2 is 4 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_SFT 4 + /* + * This is the bitmap of all member ports in the LAG. Each bit + * represents a front panel port of the device starting from port 0. + * The number of front panel ports is specified in the port_cnt field + * of the HWRM_PORT_PHY_QCAPS response. + * The term "member port" refers to a front panel port that is added to + * the bond group as a slave device. These member ports are combined to + * create a logical bond interface. + * For a 4-port NIC, the LAG member port combination can consist of + * either two ports or four ports. However, it is important to note + * that the case with three ports in the same lag group is not + * supported. + * The PORT_2 and PORT_3 are only valid if the NIC has four front + * panel ports. There could be a case to use multiple LAG groups, + * for example, if the NIC has four front panel ports, the lag feature + * can use up to two LAG groups, with two ports assigned to each group. + */ + uint8_t member_port_map; + /* If this bit is set to '1', the port0 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1) + /* If this bit is set to '1', the port1 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2) + /* If this bit is set to '1', the port2 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4) + /* If this bit is set to '1', the port3 is a lag member port. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8) + /* rsvd3 is 4 b */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_MASK UINT32_C(0xf0) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_SFT 4 + /* Link aggregation mode being used. */ + uint8_t link_aggr_mode; + /* active active mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1) + /* active backup mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2) + /* Balance XOR mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3) + /* 802.3AD mode. */ + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4) + #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_LAST HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_func_lag_mode_qcfg_output_t, *phwrm_func_lag_mode_qcfg_output_t; + /*********************** * hwrm_func_vlan_qcfg * ***********************/ @@ -22587,8 +24779,8 @@ typedef struct hwrm_func_vlan_qcfg_output { uint8_t stag_pcp; uint8_t unused_1; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * S-TAG TPID value configured for the function. This field is + * specified in network byte order. */ uint16_t stag_tpid; /* C-TAG VLAN identifier configured for the function. */ @@ -22597,8 +24789,8 @@ typedef struct hwrm_func_vlan_qcfg_output { uint8_t ctag_pcp; uint8_t unused_2; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * C-TAG TPID value configured for the function. This field is + * specified in network byte order. */ uint16_t ctag_tpid; /* Future use. */ @@ -22608,9 +24800,9 @@ typedef struct hwrm_func_vlan_qcfg_output { uint8_t unused_3[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22697,8 +24889,8 @@ typedef struct hwrm_func_vlan_cfg_input { uint8_t stag_pcp; uint8_t unused_1; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * S-TAG TPID value configured for the function. This field is + * specified in network byte order. */ uint16_t stag_tpid; /* C-TAG VLAN identifier configured for the function. */ @@ -22707,8 +24899,8 @@ typedef struct hwrm_func_vlan_cfg_input { uint8_t ctag_pcp; uint8_t unused_2; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * C-TAG TPID value configured for the function. This field is + * specified in network byte order. */ uint16_t ctag_tpid; /* Future use. */ @@ -22732,9 +24924,9 @@ typedef struct hwrm_func_vlan_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22808,9 +25000,9 @@ typedef struct hwrm_func_vf_vnic_ids_query_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22918,9 +25110,9 @@ typedef struct hwrm_func_vf_bw_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -22989,8 +25181,8 @@ typedef struct hwrm_func_vf_bw_qcfg_output { uint16_t resp_len; /* * The number of VF functions that are being queried. - * The inline response space allows the host to query up to 50 VFs' rate - * scale percentage + * The inline response space allows the host to query up to 50 VFs' + * rate scale percentage. */ uint16_t num_vfs; uint16_t unused[3]; @@ -23041,9 +25233,9 @@ typedef struct hwrm_func_vf_bw_qcfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23088,11 +25280,11 @@ typedef struct hwrm_func_drv_if_change_input { uint32_t flags; /* * When this bit is '1', the function driver is indicating - * that the IF state is changing to UP state. The call should + * that the IF state is changing to UP state. The call should * be made at the beginning of the driver's open call before - * resources are allocated. After making the call, the driver + * resources are allocated. After making the call, the driver * should check the response to see if any resources may have - * changed (see the response below). If the driver fails + * changed (see the response below). If the driver fails * the open call, the driver should make this call again with * this bit cleared to indicate that the IF state is not UP. * During the driver's close call when the IF state is changing @@ -23117,22 +25309,32 @@ typedef struct hwrm_func_drv_if_change_output { uint32_t flags; /* * When this bit is '1', it indicates that the resources reserved - * for this function may have changed. The driver should check + * for this function may have changed. The driver should check * resource capabilities and reserve resources again before * allocating resources. */ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE UINT32_C(0x1) /* - * When this bit is '1', it indicates that the firmware got changed / reset. - * The driver should do complete re-initialization when that bit is set. + * When this bit is '1', it indicates that the firmware got changed / + * reset. The driver should do complete re-initialization when that + * bit is set. */ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE UINT32_C(0x2) + /* + * When this bit is '1', it indicates that capabilities + * for this function may have changed. The driver should + * query for changes to capabilities. + * The CAPS_CHANGE bit will only be set when it is safe for the + * driver to completely re-initialize all resources for the function + * including any children VFs. + */ + #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_CAPS_CHANGE UINT32_C(0x4) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23321,9 +25523,9 @@ typedef struct hwrm_func_host_pf_ids_query_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23518,9 +25720,9 @@ typedef struct hwrm_func_spd_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23678,9 +25880,9 @@ typedef struct hwrm_func_spd_qcfg_output { uint8_t unused_2[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -23691,7 +25893,7 @@ typedef struct hwrm_func_spd_qcfg_output { *********************/ -/* hwrm_port_phy_cfg_input (size:448b/56B) */ +/* hwrm_port_phy_cfg_input (size:512b/64B) */ typedef struct hwrm_port_phy_cfg_input { /* The HWRM command request type. */ @@ -23738,7 +25940,7 @@ typedef struct hwrm_port_phy_cfg_input { * settings specified in this command. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1) - /* deprecated bit. Do not use!!! */ + /* deprecated bit. Do not use!!! */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED UINT32_C(0x2) /* * When this bit is set to '1', and the force_pam4_link_speed @@ -23798,33 +26000,33 @@ typedef struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE UINT32_C(0x80) /* - * When set to 1, then the HWRM shall enable FEC autonegotitation - * on this port if supported. When enabled, at least one of the + * When set to 1, then the HWRM shall enable FEC autonegotiation + * on this port if supported. When enabled, at least one of the * FEC modes must be advertised by enabling the fec_clause_74_enable, * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable, - * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none + * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none * of the FEC mode is currently enabled, the HWRM shall choose * a default advertisement setting. * The default advertisement setting can be queried by calling - * hwrm_port_phy_qcfg. Note that the link speed must be + * hwrm_port_phy_qcfg. Note that the link speed must be * in autonegotiation mode for FEC autonegotiation to take effect. * When set to 0, then this flag shall be ignored. - * If FEC autonegotiation is not supported, then the HWRM shall ignore this - * flag. + * If FEC autonegotiation is not supported, then the HWRM shall + * ignore this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE UINT32_C(0x100) /* * When set to 1, then the HWRM shall disable FEC autonegotiation - * on this port and use forced FEC mode. In forced FEC mode, one + * on this port and use forced FEC mode. In forced FEC mode, one * or more FEC forced settings under the same clause can be set. * When set to 0, then this flag shall be ignored. - * If FEC autonegotiation is not supported, then the HWRM shall ignore this - * flag. + * If FEC autonegotiation is not supported, then the HWRM shall + * ignore this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE UINT32_C(0x200) /* - * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) - * on this port if supported, by advertising FEC CLAUSE 74 if + * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire + * Code) on this port if supported, by advertising FEC CLAUSE 74 if * FEC autonegotiation is enabled or force enabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this @@ -23832,9 +26034,9 @@ typedef struct hwrm_port_phy_cfg_input { */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE UINT32_C(0x400) /* - * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) - * on this port if supported, by not advertising FEC CLAUSE 74 if - * FEC autonegotiation is enabled or force disabled otherwise. + * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire + * Code) on this port if supported, by not advertising FEC CLAUSE 74 + * if FEC autonegotiation is enabled or force disabled otherwise. * When set to 0, then this flag shall be ignored. * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this * flag. @@ -23844,8 +26046,8 @@ typedef struct hwrm_port_phy_cfg_input { * When set to 1, then the HWRM shall enable FEC CLAUSE 91 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, * by advertising FEC RS(528,514) if FEC autonegotiation is enabled - * or force enabled otherwise. In forced FEC mode, this flag - * will only take effect if the speed is NRZ. Additional + * or force enabled otherwise. In forced FEC mode, this flag + * will only take effect if the speed is NRZ. Additional * RS544 or RS272 flags (also under clause 91) may be set for PAM4 * in forced FEC mode. * When set to 0, then this flag shall be ignored. @@ -23857,8 +26059,8 @@ typedef struct hwrm_port_phy_cfg_input { * When set to 1, then the HWRM shall disable FEC CLAUSE 91 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by * not advertising RS(528,514) if FEC autonegotiation is enabled or - * force disabled otherwise. When set to 0, then this flag shall be - * ignored. If FEC RS(528,514) is not supported, then the HWRM + * force disabled otherwise. When set to 0, then this flag shall be + * ignored. If FEC RS(528,514) is not supported, then the HWRM * shall ignore this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE UINT32_C(0x2000) @@ -23886,7 +26088,7 @@ typedef struct hwrm_port_phy_cfg_input { * on this port if supported, by advertising FEC RS544_1XN if * FEC autonegotiation is enabled or force enabled otherwise. * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs544_ieee_enable are set, the + * PAM4. If this flag and fec_rs544_ieee_enable are set, the * HWRM shall choose one of the RS544 modes. * When set to 0, then this flag shall be ignored. * If FEC RS544_1XN is not supported, then the HWRM shall ignore this @@ -23898,8 +26100,8 @@ typedef struct hwrm_port_phy_cfg_input { * on this port if supported, by not advertising FEC RS544_1XN if * FEC autonegotiation is enabled or force disabled otherwise. * When set to 0, then this flag shall be ignored. - * If FEC RS544_1XN is not supported, then the HWRM shall ignore this - * flag. + * If FEC RS544_1XN is not supported, then the HWRM shall ignore + * this flag. */ #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE UINT32_C(0x10000) /* @@ -23907,7 +26109,7 @@ typedef struct hwrm_port_phy_cfg_input { * on this port if supported, by advertising FEC RS(544,514) if * FEC autonegotiation is enabled or force enabled otherwise. * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs544_1xn_enable are set, the + * PAM4. If this flag and fec_rs544_1xn_enable are set, the * HWRM shall choose one of the RS544 modes. * When set to 0, then this flag shall be ignored. * If FEC RS(544,514) is not supported, then the HWRM shall ignore @@ -23928,8 +26130,8 @@ typedef struct hwrm_port_phy_cfg_input { * on this port if supported, by advertising FEC RS272_1XN if * FEC autonegotiation is enabled or force enabled otherwise. * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs272_ieee_enable are set, the - * HWRM shall choose one of the RS272 modes. Note that RS272 + * PAM4. If this flag and fec_rs272_ieee_enable are set, the + * HWRM shall choose one of the RS272 modes. Note that RS272 * and RS544 modes cannot be set at the same time in forced FEC mode. * When set to 0, then this flag shall be ignored. * If FEC RS272_1XN is not supported, then the HWRM shall ignore this @@ -23950,8 +26152,8 @@ typedef struct hwrm_port_phy_cfg_input { * on this port if supported, by advertising FEC RS(272,257) if * FEC autonegotiation is enabled or force enabled otherwise. * In forced mode, this flag will only take effect if the speed is - * PAM4. If this flag and fec_rs272_1xn_enable are set, the - * HWRM shall choose one of the RS272 modes. Note that RS272 + * PAM4. If this flag and fec_rs272_1xn_enable are set, the + * HWRM shall choose one of the RS272 modes. Note that RS272 * and RS544 modes cannot be set at the same time in forced FEC mode. * When set to 0, then this flag shall be ignored. * If FEC RS(272,257) is not supported, then the HWRM shall ignore @@ -24033,11 +26235,21 @@ typedef struct hwrm_port_phy_cfg_input { * be configured. */ #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK UINT32_C(0x1000) + /* + * This bit must be '1' for the force_link_speeds2 field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_LINK_SPEEDS2 UINT32_C(0x2000) + /* + * This bit must be '1' for the auto_link_speeds2_mask field to + * be configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEEDS2_MASK UINT32_C(0x4000) /* Port ID of port that is to be configured. */ uint16_t port_id; /* * This is the speed that will be used if the force - * bit is '1'. If unsupported speed is selected, an error + * bit is '1'. If unsupported speed is selected, an error * will be generated. */ uint16_t force_link_speed; @@ -24074,18 +26286,19 @@ typedef struct hwrm_port_phy_cfg_input { /* Select all possible speeds for autoneg mode. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. + * Select only the auto_link_speed speed for autoneg mode. This mode + * has been DEPRECATED. An HWRM client should not use this mode. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should not + * use this mode. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) /* - * Select the speeds based on the corresponding link speed mask values - * that are provided. The included speeds are specified in the + * Select the speeds based on the corresponding link speed mask + * values that are provided. The included speeds are specified in the * auto_link_speed and auto_pam4_link_speed fields. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) @@ -24133,10 +26346,29 @@ typedef struct hwrm_port_phy_cfg_input { * 1, auto_pause bits should be ignored and should be set to 0. */ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4) - uint8_t unused_0; + /* + * This field is only used by management firmware to communicate with + * core firmware regarding phy_port_cfg. + * It mainly used to notify core firmware that management firmware is + * using port for NCSI over RMII communication or not. + */ + uint8_t mgmt_flag; + /* + * Bit denoting if management firmware is using the link for + * NCSI over RMII communication. + * When set to 1, management firmware is no longer using the given + * port. + * When set to 0, management firmware is using the given port. + */ + #define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_LINK_RELEASE UINT32_C(0x1) + /* + * Validity bit, set to 1 to indicate other bits in mgmt_flags are + * valid. + */ + #define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_MGMT_VALID UINT32_C(0x80) /* * This is the speed that will be used if the autoneg_mode - * is "one_speed" or "one_or_below". If an unsupported speed + * is "one_speed" or "one_or_below". If an unsupported speed * is selected, an error will be generated. */ uint16_t auto_link_speed; @@ -24165,7 +26397,7 @@ typedef struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB /* * This is a mask of link speeds that will be used if - * autoneg_mode is "mask". If unsupported speed is enabled + * autoneg_mode is "mask". If unsupported speed is enabled * an error will be generated. */ uint16_t auto_link_speed_mask; @@ -24206,7 +26438,7 @@ typedef struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON /* This value controls the loopback setting for the PHY. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -24222,7 +26454,8 @@ typedef struct hwrm_port_phy_cfg_input { /* * The HW will be configured with external loopback such that * host data is sent on the transmitter and based on the external - * loopback connection the data will be received without modification. + * loopback connection the data will be received without + * modification. */ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3) #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL @@ -24244,7 +26477,7 @@ typedef struct hwrm_port_phy_cfg_input { uint8_t unused_1; /* * This value controls the pre-emphasis to be used for the - * link. Driver should not set this value (use + * link. Driver should not set this value (use * enable.preemphasis = 0) unless driver is sure of setting. * Normally HWRM FW will determine proper pre-emphasis. */ @@ -24275,7 +26508,7 @@ typedef struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40) /* * This is the speed that will be used if the force and force_pam4 - * bits are '1'. If unsupported speed is selected, an error + * bits are '1'. If unsupported speed is selected, an error * will be generated. */ uint16_t force_pam4_link_speed; @@ -24299,7 +26532,76 @@ typedef struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G UINT32_C(0x1) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G UINT32_C(0x2) #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G UINT32_C(0x4) - uint8_t unused_2[2]; + /* + * This is the speed that will be used if the force_link_speeds2 + * bit is '1'. If unsupported speed is selected, an error + * will be generated. + */ + uint16_t force_link_speeds2; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB UINT32_C(0xa) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB UINT32_C(0x64) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB UINT32_C(0xfa) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB UINT32_C(0x190) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB UINT32_C(0x1f4) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB UINT32_C(0x3e8) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x1f5) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x3e9) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x7d1) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0xfa1) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42) + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_LAST HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 + /* + * This is a mask of link speeds that will be used if + * auto_link_speeds2_mask bit in the "enables" field is 1. + * If unsupported speed is enabled an error will be generated. + */ + uint16_t auto_link_speeds2_mask; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 UINT32_C(0x2000) + uint8_t unused_2[6]; } hwrm_port_phy_cfg_input_t, *phwrm_port_phy_cfg_input_t; /* hwrm_port_phy_cfg_output (size:128b/16B) */ @@ -24316,9 +26618,9 @@ typedef struct hwrm_port_phy_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -24344,7 +26646,7 @@ typedef struct hwrm_port_phy_cfg_cmd_err { * but if a 0 is returned at any time then this should * be treated as an un recoverable failure, * - * retry interval in milli seconds is returned in opaque_1. + * retry interval in milliseconds is returned in opaque_1. * This specifies the time that user should wait before * issuing the next port_phy_cfg command. */ @@ -24423,9 +26725,11 @@ typedef struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0 /* NRZ signaling */ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ UINT32_C(0x0) - /* PAM4 signaling */ + /* PAM4-56 signaling */ #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 UINT32_C(0x1) - #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 + /* PAM4-112 signaling */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 UINT32_C(0x2) + #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 /* This value indicates the current active FEC mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK UINT32_C(0xf0) #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4 @@ -24433,15 +26737,15 @@ typedef struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE (UINT32_C(0x0) << 4) /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (UINT32_C(0x1) << 4) - /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */ + /* FEC CLAUSE 91 RS(528,514) active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (UINT32_C(0x2) << 4) - /* FEC RS544_1XN active, autonegoatiated or forced. */ + /* FEC RS544_1XN active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (UINT32_C(0x3) << 4) - /* FEC RS(544,528) active, autonegoatiated or forced. */ + /* FEC RS(544,528) active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (UINT32_C(0x4) << 4) /* FEC RS272_1XN active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (UINT32_C(0x5) << 4) - /* FEC RS(272,257) active, autonegoatiated or forced. */ + /* FEC RS(272,257) active, autonegotiated or forced. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (UINT32_C(0x6) << 4) #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE /* @@ -24472,6 +26776,10 @@ typedef struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8) /* 200Gb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0) + /* 400Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB UINT32_C(0xfa0) + /* 800Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_800GB UINT32_C(0x1f40) /* 10Mb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff) #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB @@ -24571,13 +26879,14 @@ typedef struct hwrm_port_phy_qcfg_output { /* Select all possible speeds for autoneg mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. + * Select only the auto_link_speed speed for autoneg mode. This mode + * has been DEPRECATED. An HWRM client should not use this mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should not + * use this mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) /* @@ -24689,7 +26998,7 @@ typedef struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON /* Current setting for loopback. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -24705,7 +27014,8 @@ typedef struct hwrm_port_phy_qcfg_output { /* * The HW will be configured with external loopback such that * host data is sent on the transmitter and based on the external - * loopback connection the data will be received without modification. + * loopback connection the data will be received without + * modification. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3) #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL @@ -24835,7 +27145,51 @@ typedef struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 UINT32_C(0x26) /* 100G_BASEER2 */ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 UINT32_C(0x27) - #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 + /* 400G_BASECR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR UINT32_C(0x28) + /* 100G_BASESR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR UINT32_C(0x29) + /* 100G_BASELR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR UINT32_C(0x2a) + /* 100G_BASEER */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER UINT32_C(0x2b) + /* 200G_BASECR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR2 UINT32_C(0x2c) + /* 200G_BASESR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR2 UINT32_C(0x2d) + /* 200G_BASELR2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR2 UINT32_C(0x2e) + /* 200G_BASEER2 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER2 UINT32_C(0x2f) + /* 400G_BASECR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR8 UINT32_C(0x30) + /* 200G_BASESR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR8 UINT32_C(0x31) + /* 400G_BASELR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR8 UINT32_C(0x32) + /* 400G_BASEER8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER8 UINT32_C(0x33) + /* 400G_BASECR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR4 UINT32_C(0x34) + /* 400G_BASESR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR4 UINT32_C(0x35) + /* 400G_BASELR4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR4 UINT32_C(0x36) + /* 400G_BASEER4 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER4 UINT32_C(0x37) + /* 800G_BASECR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASECR8 UINT32_C(0x38) + /* 800G_BASESR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASESR8 UINT32_C(0x39) + /* 800G_BASELR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASELR8 UINT32_C(0x3a) + /* 800G_BASEER8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEER8 UINT32_C(0x3b) + /* 800G_BASEFR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEFR8 UINT32_C(0x3c) + /* 800G_BASEDR8 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEDR8 UINT32_C(0x3d) + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEDR8 /* This value represents a media type. */ uint8_t media_type; /* Unknown */ @@ -24867,9 +27221,9 @@ typedef struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK UINT32_C(0xe0) #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5 /* - * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled. - * Speeds for autoneg with EEE mode enabled - * are based on eee_link_speed_mask. + * When set to 1, Energy Efficient Ethernet (EEE) mode is + * enabled. Speeds for autoneg with EEE mode enabled are based on + * eee_link_speed_mask. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED UINT32_C(0x20) /* @@ -24959,13 +27313,14 @@ typedef struct hwrm_port_phy_qcfg_output { /* Select all possible speeds for autoneg mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) /* - * Select only the auto_link_speed speed for autoneg mode. This mode has - * been DEPRECATED. An HWRM client should not use this mode. + * Select only the auto_link_speed speed for autoneg mode. This mode + * has been DEPRECATED. An HWRM client should not use this mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED UINT32_C(0x2) /* - * Select the auto_link_speed or any speed below that speed for autoneg. - * This mode has been DEPRECATED. An HWRM client should not use this mode. + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should not + * use this mode. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) /* @@ -25047,43 +27402,55 @@ typedef struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP (UINT32_C(0xc) << 24) /* QSFP+ */ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS (UINT32_C(0xd) << 24) - /* QSFP28 */ + /* QSFP28/QSFP56 or later */ #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 (UINT32_C(0x11) << 24) - #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 + /* QSFP-DD */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPDD (UINT32_C(0x18) << 24) + /* QSFP112 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112 (UINT32_C(0x1e) << 24) + /* SFP-DD CMIS */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFPDD (UINT32_C(0x1f) << 24) + /* SFP CMIS */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP (UINT32_C(0x20) << 24) + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP /* * This value represents the current configuration of * Forward Error Correction (FEC) on the port. */ uint16_t fec_cfg; /* - * When set to 1, then FEC is not supported on this port. If this flag - * is set to 1, then all other FEC configuration flags shall be ignored. - * When set to 0, then FEC is supported as indicated by other - * configuration flags. + * When set to 1, then FEC is not supported on this port. If this + * flag is set to 1, then all other FEC configuration flags shall be + * ignored. When set to 0, then FEC is supported as indicated by + * other configuration flags. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED UINT32_C(0x1) /* * When set to 1, then FEC autonegotiation is supported on this port. - * When set to 0, then FEC autonegotiation is not supported on this port. + * When set to 0, then FEC autonegotiation is not supported on this + * port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED UINT32_C(0x2) /* * When set to 1, then FEC autonegotiation is enabled on this port. * When set to 0, then FEC autonegotiation is disabled if supported. - * This flag should be ignored if FEC autonegotiation is not supported on this port. + * This flag should be ignored if FEC autonegotiation is not + * supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED UINT32_C(0x4) /* - * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port. - * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port. + * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this + * port. When set to 0, then FEC CLAUSE 74 (Fire Code) is not + * supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED UINT32_C(0x8) /* * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this * port. This means that FEC CLAUSE 74 is either advertised if * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled. - * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported. - * This flag should be ignored if FEC CLAUSE 74 is not supported on this port. + * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if + * supported. This flag should be ignored if FEC CLAUSE 74 is not + * supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED UINT32_C(0x10) /* @@ -25096,9 +27463,10 @@ typedef struct hwrm_port_phy_qcfg_output { * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for * NRZ) is enabled on this port. This means that FEC RS(528,514) is * either advertised if FEC autonegotiation is enabled or FEC - * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514) + * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514) * is disabled if supported. - * This flag should be ignored if FEC CLAUSE 91 is not supported on this port. + * This flag should be ignored if FEC CLAUSE 91 is not supported on + * this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED UINT32_C(0x40) /* @@ -25111,7 +27479,8 @@ typedef struct hwrm_port_phy_qcfg_output { * port. This means that FEC RS544_1XN is either advertised if * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled. * When set to 0, then FEC RS544_1XN is disabled if supported. - * This flag should be ignored if FEC RS544_1XN is not supported on this port. + * This flag should be ignored if FEC RS544_1XN is not supported on + * this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED UINT32_C(0x100) /* @@ -25123,8 +27492,9 @@ typedef struct hwrm_port_phy_qcfg_output { * When set to 1, then RS(544,514) is enabled on this * port. This means that FEC RS(544,514) is either advertised if * FEC autonegotiation is enabled or FEC RS(544,514) is force - * enabled. When set to 0, then FEC RS(544,514) is disabled if supported. - * This flag should be ignored if FEC RS(544,514) is not supported on this port. + * enabled. When set to 0, then FEC RS(544,514) is disabled if + * supported. This flag should be ignored if FEC RS(544,514) is not + * supported on this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED UINT32_C(0x400) /* @@ -25136,8 +27506,10 @@ typedef struct hwrm_port_phy_qcfg_output { * When set to 1, then RS272_1XN is enabled on this * port. This means that FEC RS272_1XN is either advertised if * FEC autonegotiation is enabled or FEC RS272_1XN is force - * enabled. When set to 0, then FEC RS272_1XN is disabled if supported. - * This flag should be ignored if FEC RS272_1XN is not supported on this port. + * enabled. When set to 0, then FEC RS272_1XN is disabled if + * supported. + * This flag should be ignored if FEC RS272_1XN is not supported on + * this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED UINT32_C(0x1000) /* @@ -25149,8 +27521,10 @@ typedef struct hwrm_port_phy_qcfg_output { * When set to 1, then RS(272,257) is enabled on this * port. This means that FEC RS(272,257) is either advertised if * FEC autonegotiation is enabled or FEC RS(272,257) is force - * enabled. When set to 0, then FEC RS(272,257) is disabled if supported. - * This flag should be ignored if FEC RS(272,257) is not supported on this port. + * enabled. When set to 0, then FEC RS(272,257) is disabled if + * supported. + * This flag should be ignored if FEC RS(272,257) is not supported on + * this port. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED UINT32_C(0x4000) /* @@ -25172,6 +27546,11 @@ typedef struct hwrm_port_phy_qcfg_output { * trusted. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN UINT32_C(0x2) + /* + * When this bit is '1', speeds2 fields are used to get + * speed details. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SPEEDS2_SUPPORTED UINT32_C(0x4) /* * Up to 16 bytes of null padded ASCII string representing * PHY vendor. @@ -25237,12 +27616,125 @@ typedef struct hwrm_port_phy_qcfg_output { uint8_t link_down_reason; /* Remote fault */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1) - uint8_t unused_0[7]; + /* + * The supported speeds for the port. This is a bit mask. + * For each speed that is supported, the corresponding + * bit will be set to '1'. This is valid only if speeds2_supported + * is set in option_flags + */ + uint16_t support_speeds2; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_800GB_PAM4_112 UINT32_C(0x2000) + /* + * Current setting of forced link speed. When the link speed is not + * being forced, this value shall be set to 0. + * This field is valid only if speeds2_supported is set in + * option_flags. + */ + uint16_t force_link_speeds2; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_1GB UINT32_C(0xa) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_10GB UINT32_C(0x64) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_25GB UINT32_C(0xfa) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_40GB UINT32_C(0x190) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB UINT32_C(0x1f4) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB UINT32_C(0x3e8) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x1f5) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x3e9) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x7d1) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0xfa1) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42) + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_LAST HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 + /* + * Current setting of auto_link speed_mask that is used to advertise + * speeds during autonegotiation. + * This field is only valid when auto_mode is set to "mask". + * and if speeds2_supported is set in option_flags + * The speeds specified in this field shall be a subset of + * supported speeds on this port. + */ + uint16_t auto_link_speeds2; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x2000) + /* + * This field is indicate the number of lanes used to transfer + * data. If the link is down, the value is zero. + * This is valid only if speeds2_supported is set in option_flags. + */ + uint8_t active_lanes; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -25425,13 +27917,13 @@ typedef struct hwrm_port_mac_cfg_input { */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI UINT32_C(0x20) /* - * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be - * configured. + * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to + * be configured. */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x40) /* - * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be - * configured. + * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to + * be configured. */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x80) /* @@ -25449,6 +27941,11 @@ typedef struct hwrm_port_mac_cfg_input { * configured. */ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE UINT32_C(0x400) + /* + * This bit must be '1' for the ptp_load_control field to + * be configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_LOAD_CONTROL UINT32_C(0x800) /* Port ID of port that is to be configured. */ uint16_t port_id; /* @@ -25458,7 +27955,7 @@ typedef struct hwrm_port_mac_cfg_input { uint8_t ipg; /* This value controls the loopback setting for the MAC. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -25623,7 +28120,25 @@ typedef struct hwrm_port_mac_cfg_input { * of sync timer updates (measured in parts per billion). */ int32_t ptp_freq_adj_ppb; - uint8_t unused_1[4]; + uint8_t unused_1[3]; + /* + * This value controls how PTP configuration like freq_adj and + * phase are loaded in the hardware block. + */ + uint8_t ptp_load_control; + /* PTP configuration is not loaded in hardware. */ + #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_NONE UINT32_C(0x0) + /* + * PTP configuration will be loaded immediately in the hardware + * block. By default, it will always be immediate. + */ + #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1) + /* + * PTP configuration will loaded at the next Pulse per second (PPS) + * event in the hardware block. + */ + #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2) + #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_LAST HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_PPS_EVENT /* * This unsigned field specifies the phase offset to be applied * to the PHC (PTP Hardware Clock). This field is specified in @@ -25661,7 +28176,7 @@ typedef struct hwrm_port_mac_cfg_output { uint8_t ipg; /* Current value of the loopback value. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -25678,9 +28193,9 @@ typedef struct hwrm_port_mac_cfg_output { uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -25759,7 +28274,7 @@ typedef struct hwrm_port_mac_qcfg_output { uint8_t ipg; /* The loopback setting for the MAC. */ uint8_t lpbk; - /* No loopback is selected. Normal operation. */ + /* No loopback is selected. Normal operation. */ #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) /* * The HW will be configured with local loopback such that @@ -25947,20 +28462,35 @@ typedef struct hwrm_port_mac_qcfg_output { uint8_t unused_1; uint16_t port_svif_info; /* - * This field specifies the source virtual interface of the port being - * queried. Drivers can use this to program port svif field in the - * L2 context table + * This field specifies the source virtual interface of the port + * being queried. Drivers can use this to program port svif field in + * the L2 context table. */ #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK UINT32_C(0x7fff) #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0 /* This field specifies whether port_svif is valid or not */ #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID UINT32_C(0x8000) - uint8_t unused_2[5]; + /* + * This field indicates the configured load control for PTP + * time of day (TOD) block. + */ + uint8_t ptp_load_control; + /* Indicates the current load control is none. */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_NONE UINT32_C(0x0) + /* Indicates the current load control is immediate. */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1) + /* + * Indicates current load control is at next Pulse per Second (PPS) + * event. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2) + #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_LAST HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_PPS_EVENT + uint8_t unused_2[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -26049,6 +28579,11 @@ typedef struct hwrm_port_mac_ptp_qcfg_output { * configured 64bit RTC. */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_RTC_CONFIGURED UINT32_C(0x20) + /* + * When this bit is set to '1', it indicates that current time + * exposed to driver is 64bit. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_64B_PHC_TIME UINT32_C(0x40) uint8_t unused_0[3]; /* * Offset of the PTP register for the lower 32 bits of timestamp @@ -26099,9 +28634,9 @@ typedef struct hwrm_port_mac_ptp_qcfg_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -26541,9 +29076,9 @@ typedef struct hwrm_port_qstats_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -26620,7 +29155,7 @@ typedef struct tx_port_stats_ext { } tx_port_stats_ext_t, *ptx_port_stats_ext_t; /* Port Rx Statistics extended Format */ -/* rx_port_stats_ext (size:3776b/472B) */ +/* rx_port_stats_ext (size:3904b/488B) */ typedef struct rx_port_stats_ext { /* Number of times link state changed to down */ @@ -26747,6 +29282,21 @@ typedef struct rx_port_stats_ext { * FEC function in the PHY */ uint64_t rx_fec_uncorrectable_blocks; + /* + * Total number of packets that are dropped due to not matching + * any RX filter rules. This value is zero on the non supported + * controllers. This counter is per controller, Firmware reports the + * same value on active ports. This counter does not include the + * packet discards because of no available buffers. + */ + uint64_t rx_filter_miss; + /* + * This field represents the number of FEC symbol errors by counting + * once for each 10-bit symbol corrected by FEC block. + * rx_fec_corrected_blocks will be incremented if all symbol errors in a + * codeword gets corrected. + */ + uint64_t rx_fec_symbol_err; } rx_port_stats_ext_t, *prx_port_stats_ext_t; /* @@ -27261,9 +29811,9 @@ typedef struct hwrm_port_qstats_ext_output { #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED UINT32_C(0x1) /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27336,16 +29886,15 @@ typedef struct hwrm_port_qstats_ext_pfc_wd_output { * statistics block in bytes. */ uint16_t pfc_wd_stat_size; - uint8_t flags; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; - uint8_t unused_0[4]; } hwrm_port_qstats_ext_pfc_wd_output_t, *phwrm_port_qstats_ext_pfc_wd_output_t; /************************* @@ -27353,7 +29902,7 @@ typedef struct hwrm_port_qstats_ext_pfc_wd_output { *************************/ -/* hwrm_port_lpbk_qstats_input (size:128b/16B) */ +/* hwrm_port_lpbk_qstats_input (size:256b/32B) */ typedef struct hwrm_port_lpbk_qstats_input { /* The HWRM command request type. */ @@ -27384,9 +29933,30 @@ typedef struct hwrm_port_lpbk_qstats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * The size of the loopback statistics buffer passed in the + * loopback_stat_host_addr in bytes. + * Firmware will not exceed this size when it DMAs the + * statistics structure to the host. The actual DMA size + * will be returned in the response. + */ + uint16_t lpbk_stat_size; + uint8_t flags; + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_PORT_LPBK_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + uint8_t unused_0[5]; + /* + * This is the host address where + * loopback statistics will be stored + */ + uint64_t lpbk_stat_host_addr; } hwrm_port_lpbk_qstats_input_t, *phwrm_port_lpbk_qstats_input_t; -/* hwrm_port_lpbk_qstats_output (size:768b/96B) */ +/* hwrm_port_lpbk_qstats_output (size:128b/16B) */ typedef struct hwrm_port_lpbk_qstats_output { /* The specific error status for the command. */ @@ -27397,6 +29967,29 @@ typedef struct hwrm_port_lpbk_qstats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* + * The size of the loopback statistics block in bytes DMA'ed by the + * firmware. Note that this size will never exceed the lpbk_stat_size + * field passed in by the driver in the hwrm_port_lpbk_qstats_input + * structure. + */ + uint16_t lpbk_stat_size; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_port_lpbk_qstats_output_t, *phwrm_port_lpbk_qstats_output_t; + +/* Loopback Port Statistic Format */ +/* port_lpbk_stats (size:640b/80B) */ + +typedef struct port_lpbk_stats { /* Number of transmitted unicast frames */ uint64_t lpbk_ucast_frames; /* Number of transmitted multicast frames */ @@ -27409,24 +30002,15 @@ typedef struct hwrm_port_lpbk_qstats_output { uint64_t lpbk_mcast_bytes; /* Number of transmitted bytes for broadcast traffic */ uint64_t lpbk_bcast_bytes; - /* Total Tx Drops for loopback traffic reported by STATS block */ - uint64_t tx_stat_discard; - /* Total Tx Error Drops for loopback traffic reported by STATS block */ - uint64_t tx_stat_error; - /* Total Rx Drops for loopback traffic reported by STATS block */ - uint64_t rx_stat_discard; - /* Total Rx Error Drops for loopback traffic reported by STATS block */ - uint64_t rx_stat_error; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} hwrm_port_lpbk_qstats_output_t, *phwrm_port_lpbk_qstats_output_t; + /* Number of dropped tx packets */ + uint64_t lpbk_tx_discards; + /* Number of error dropped tx packets */ + uint64_t lpbk_tx_errors; + /* Number of dropped rx packets */ + uint64_t lpbk_rx_discards; + /* Number of error dropped rx packets */ + uint64_t lpbk_rx_errors; +} port_lpbk_stats_t, *pport_lpbk_stats_t; /************************ * hwrm_port_ecn_qstats * @@ -27510,9 +30094,9 @@ typedef struct hwrm_port_ecn_qstats_output { uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27617,7 +30201,8 @@ typedef struct hwrm_port_clr_stats_input { * RoCE associated TX/RX cos counters * CNP associated TX/RX cos counters * RoCE/CNP specific TX/RX flow counters - * Firmware will determine the RoCE/CNP cos queue based on qos profile. + * Firmware will determine the RoCE/CNP cos queue based on qos + * profile. * This flag is honored only when RoCE is enabled on that port. */ #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1) @@ -27638,9 +30223,9 @@ typedef struct hwrm_port_clr_stats_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27651,7 +30236,7 @@ typedef struct hwrm_port_clr_stats_output { ****************************/ -/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ +/* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */ typedef struct hwrm_port_lpbk_clr_stats_input { /* The HWRM command request type. */ @@ -27682,6 +30267,9 @@ typedef struct hwrm_port_lpbk_clr_stats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; } hwrm_port_lpbk_clr_stats_input_t, *phwrm_port_lpbk_clr_stats_input_t; /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ @@ -27698,9 +30286,9 @@ typedef struct hwrm_port_lpbk_clr_stats_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27824,9 +30412,9 @@ typedef struct hwrm_port_ts_query_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -27873,7 +30461,7 @@ typedef struct hwrm_port_phy_qcaps_input { uint8_t unused_0[6]; } hwrm_port_phy_qcaps_input_t, *phwrm_port_phy_qcaps_input_t; -/* hwrm_port_phy_qcaps_output (size:256b/32B) */ +/* hwrm_port_phy_qcaps_output (size:320b/40B) */ typedef struct hwrm_port_phy_qcaps_output { /* The specific error status for the command. */ @@ -27902,9 +30490,9 @@ typedef struct hwrm_port_phy_qcaps_output { */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED UINT32_C(0x4) /* - * Indicates if the configuration of shared PHY settings is supported. - * In cases where a physical port is shared by multiple functions - * (e.g. NPAR, multihost, etc), the configuration of PHY + * Indicates if the configuration of shared PHY settings is + * supported. In cases where a physical port is shared by multiple + * functions (e.g. NPAR, multihost, etc), the configuration of PHY * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case. */ @@ -27912,7 +30500,7 @@ typedef struct hwrm_port_phy_qcaps_output { /* * If set to 1, it indicates that the port counters and extended * port counters will not reset when the firmware shuts down or - * resets the PHY. These counters will only be reset during power + * resets the PHY. These counters will only be reset during power * cycle or by calling HWRM_PORT_CLR_STATS. * If set to 0, the state of the counters is unspecified when * firmware shuts down or resets the PHY. @@ -28101,12 +30689,23 @@ typedef struct hwrm_port_phy_qcaps_output { * If set to 1, then this field indicates that * priority-based flow control is not supported. */ - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED UINT32_C(0x2) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED UINT32_C(0x2) /* * If set to 1, then this field indicates that * bank based addressing is supported in firmware. */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED UINT32_C(0x4) + /* + * If set to 1, then this field indicates that + * supported_speed2 field is to be used in lieu of all + * supported_speed variants. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED UINT32_C(0x8) + /* + * If set to 1, then this field indicates that + * the device does not support remote loopback. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_REMOTE_LPBK_UNSUPPORTED UINT32_C(0x10) /* * Number of internal ports for this device. This field allows the FW * to advertise how many internal ports are present. Manufacturing @@ -28115,11 +30714,85 @@ typedef struct hwrm_port_phy_qcaps_output { * option "HPTN_MODE" is set to 1. */ uint8_t internal_port_cnt; + uint8_t unused_0; + /* + * This is a bit mask to indicate what speeds are supported + * as forced speeds on this link. + * For each speed that can be forced on this link, the + * corresponding mask bit shall be set to '1'. + * This field is valid only if speeds2_supported bit is set in flags2 + */ + uint16_t supported_speeds2_force_mode; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 UINT32_C(0x2000) + /* + * This is a bit mask to indicate what speeds are supported + * for autonegotiation on this link. + * For each speed that can be autonegotiated on this link, the + * corresponding mask bit shall be set to '1'. + * This field is valid only if speeds2_supported bit is set in flags2 + */ + uint16_t supported_speeds2_auto_mode; + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_1GB UINT32_C(0x1) + /* 10Gb (NRZ: 10G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_10GB UINT32_C(0x2) + /* 25Gb (NRZ: 25G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_25GB UINT32_C(0x4) + /* 40Gb (NRZ: 10G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_40GB UINT32_C(0x8) + /* 50Gb (NRZ: 25G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB UINT32_C(0x10) + /* 100Gb (NRZ: 25G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB UINT32_C(0x20) + /* 50Gb (PAM4-56: 50G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 UINT32_C(0x40) + /* 100Gb (PAM4-56: 50G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 UINT32_C(0x80) + /* 200Gb (PAM4-56: 50G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 UINT32_C(0x100) + /* 400Gb (PAM4-56: 50G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 UINT32_C(0x200) + /* 100Gb (PAM4-112: 100G per lane, 1 lane) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 UINT32_C(0x400) + /* 200Gb (PAM4-112: 100G per lane, 2 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 UINT32_C(0x800) + /* 400Gb (PAM4-112: 100G per lane, 4 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 UINT32_C(0x1000) + /* 800Gb (PAM4-112: 100G per lane, 8 lanes) link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 UINT32_C(0x2000) + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28208,9 +30881,9 @@ typedef struct hwrm_port_phy_i2c_write_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28299,9 +30972,9 @@ typedef struct hwrm_port_phy_i2c_read_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28378,9 +31051,9 @@ typedef struct hwrm_port_phy_mdio_write_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28457,9 +31130,9 @@ typedef struct hwrm_port_phy_mdio_read_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -28851,9 +31524,9 @@ typedef struct hwrm_port_led_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29147,9 +31820,9 @@ typedef struct hwrm_port_led_qcfg_output { uint8_t unused_4[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29465,9 +32138,9 @@ typedef struct hwrm_port_led_qcaps_output { uint8_t unused_4[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29513,7 +32186,8 @@ typedef struct hwrm_port_prbs_test_input { uint64_t resp_data_addr; /* * Size of the buffer pointed to by resp_data_addr. The firmware may - * use this entire buffer or less than the entire buffer, but never more. + * use this entire buffer or less than the entire buffer, but never + * more. */ uint16_t data_len; uint16_t flags; @@ -29622,9 +32296,9 @@ typedef struct hwrm_port_prbs_test_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29669,13 +32343,20 @@ typedef struct hwrm_port_dsc_dump_input { /* Host address where response diagnostic data is returned. */ uint64_t resp_data_addr; /* - * Size of the buffer pointed to by resp_data_addr. The firmware + * Size of the host buffer pointed to by resp_data_addr. The firmware * may use this entire buffer or less than the entire buffer, but * never more. */ uint16_t data_len; uint16_t unused_0; - uint32_t unused_1; + /* + * Ignored by the start command. + * In legacy buffer mode, this is ignored. The transfer starts + * at buffer offset zero and must be transferred in one command. + * In big buffer mode, this is the offset into the NIC buffer for + * the current retrieve command to start. + */ + uint32_t data_offset; /* Port ID of port where dsc dump to be collected. */ uint16_t port_id; /* Diag level specified by the user */ @@ -29708,20 +32389,48 @@ typedef struct hwrm_port_dsc_dump_input { #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP UINT32_C(0xc) #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP /* - * This field is a lane number - * on which to collect the dsc dump + * This field is the lane number on which to collect the dsc dump. + * If this is 0xFFFF, the dsc dump will be collected for all lanes, + * if the hardware and firmware support this feature. */ uint16_t lane_number; - /* - * Configuration bits. - * Use enable bit to start dsc dump or retrieve dump - */ + /* Configuration bits. */ uint16_t dsc_dump_config; /* * Set 0 to retrieve the dsc dump * Set 1 to start the dsc dump + * Some configuration parameter for the dscdump report are + * set by the start request, and can not be modified until the + * retrieve operation is complete, on the next start. */ #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE UINT32_C(0x1) + /* + * Set 0 to limit the report size to 65535 bytes. + * Set 1 to allow a larger buffer size. + * This can only be set 1 in the start operation. + * If this is set 0 in the start operation, the firmware will + * assume it needs to only expose up to 65535 bytes of the report, + * and only allow a single retrieve operation to retrieve the + * entire report. This mode will truncate longer reports. + * If this is set 1 in the start operation, the firmware will + * report the full size of the report (up to the firmware's limit), + * permit retrieve operations to hold the buffer using the config + * defer_close, and honour the data_offset value so later data + * in the report can be retrieved. + */ + #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_BIG_BUFFER UINT32_C(0x2) + /* + * Set 0 on the last 'retrieve' to release the firmware buffer + * Set 1 on the other 'retrieve' to hold the firmware buffer + * This only affects retrieve operations. + * In big_buffer mode, this allows the driver or tool to tell + * the firmware to keep the report around, as it intends to read + * more of it in. The final read must set this to zero, to tell + * the firmware the report buffer can be released. + * This only works if the start request specified big_buffer as + * one; it is ignored otherwise. + */ + #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_DEFER_CLOSE UINT32_C(0x4) } hwrm_port_dsc_dump_input_t, *phwrm_port_dsc_dump_input_t; /* hwrm_port_dsc_dump_output (size:128b/16B) */ @@ -29735,15 +32444,49 @@ typedef struct hwrm_port_dsc_dump_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Total length of stored data. */ + /* + * Total length of stored data; if big_buffer is one, this + * only contains the lower 16 bits of the total length. + * In legacy buffer mode, this is zero in the 'start' response. + * In big buffer mode, this has the size of the report even + * in the 'start' response. + * In both modes, this contains the number of bytes written + * to the host in 'retrieve' responses. + */ uint16_t total_data_len; - uint16_t unused_0; - uint8_t unused_1[3]; + /* + * The upper 16 bits of the total length of stored data. + * In legacy buffer mode, this will always be zero. + * In big buffer mode, this will be populated even in the + * 'start' response. + * This is always zero for 'retrieve' responses. + */ + uint16_t total_data_len_high; + uint8_t unused_1[2]; + /* Result information bits. */ + uint8_t flags; + /* + * Set according to the start request's input big_buffer. + * If this is zero, it indicates the function is acting per + * legacy behaviour -- it will report a buffer size up to almost + * 64KiB, and allow only one retrieval request before releasing + * the firmware buffer containing the report (total_data_len_high + * will be zero). The request's data_offset field and defer_close + * and use_offset config flags are ignored. + * If this is one, it indicates support for (and request of) + * support for larger reports. The full 32b report size (up to the + * firmware buffer limit) is provided by the start response in + * total_data_len (low 16b) and total_data_len_high (high 16b), + * and retrieve requests may keep the buffer using the defer_close + * flag, and retrieve the later parts of the report using the + * data_offset field. + */ + #define HWRM_PORT_DSC_DUMP_OUTPUT_FLAGS_BIG_BUFFER UINT32_C(0x1) /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -29870,7 +32613,7 @@ typedef struct hwrm_port_sfp_sideband_cfg_output { uint8_t unused[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. When * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -29985,7 +32728,7 @@ typedef struct hwrm_port_sfp_sideband_qcfg_output { uint8_t unused[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. When * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. @@ -30040,7 +32783,7 @@ typedef struct hwrm_port_phy_mdio_bus_acquire_input { */ uint16_t client_id; /* - * Timeout in milli seconds, MDIO BUS will be released automatically + * Timeout in milliseconds, MDIO BUS will be released automatically * after this time, if another mdio acquire command is not received * within the timeout window from the same client. * A 0xFFFF will hold the bus until this bus is released. @@ -30069,9 +32812,9 @@ typedef struct hwrm_port_phy_mdio_bus_acquire_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30140,9 +32883,9 @@ typedef struct hwrm_port_phy_mdio_bus_release_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30187,10 +32930,20 @@ typedef struct hwrm_port_tx_fir_cfg_input { /* Modulation types of TX FIR: NRZ, PAM4. */ uint8_t mod_type; /* For NRZ */ - #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) /* For PAM4 */ - #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) - #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) + /* For Optical NRZ */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_NRZ UINT32_C(0x2) + /* For Optical PAM4 */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4 UINT32_C(0x3) + /* For DAC PAM4 112G */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4_112 UINT32_C(0x4) + /* For Optical PAM4 112G */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4_112G UINT32_C(0x5) + /* For LPO PAM4 112G */ + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LPO_PAM4_112G UINT32_C(0x6) + #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LPO_PAM4_112G /* The lane mask of the lane TX FIR will be configured. */ uint8_t lane_mask; uint8_t unused_0[2]; @@ -30219,9 +32972,9 @@ typedef struct hwrm_port_tx_fir_cfg_output { uint8_t unused[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30266,10 +33019,20 @@ typedef struct hwrm_port_tx_fir_qcfg_input { /* Modulation types of TX FIR: NRZ, PAM4. */ uint8_t mod_type; /* For NRZ */ - #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) - /* For PAM4 */ - #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) - #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0) + /* For PAM4 56G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1) + /* For Optical NRZ */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_NRZ UINT32_C(0x2) + /* For Optical PAM4 56G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4 UINT32_C(0x3) + /* For DAC PAM4 112G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4_112 UINT32_C(0x4) + /* For Optical PAM4 112G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4_112 UINT32_C(0x5) + /* For LPO PAM4 112G */ + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LPO_PAM4_112 UINT32_C(0x6) + #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LPO_PAM4_112 /* The ID of the lane TX FIR will be queried. */ uint8_t lane_id; uint8_t unused[6]; @@ -30297,9 +33060,9 @@ typedef struct hwrm_port_tx_fir_qcfg_output { uint8_t unused[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30403,9 +33166,9 @@ typedef struct hwrm_port_ep_tx_cfg_input { */ uint8_t ep2_min_bw; /* - * Specifies the maximum portion of the port's bandwidth that the set of - * PFs and VFs on PCIe endpoint 2 may use. The value is a percentage of - * the link bandwidth, from 0 to 100. A value of 0 indicates no + * Specifies the maximum portion of the port's bandwidth that the set + * of PFs and VFs on PCIe endpoint 2 may use. The value is a percentage + * of the link bandwidth, from 0 to 100. A value of 0 indicates no * maximum rate. */ uint8_t ep2_max_bw; @@ -30680,9 +33443,9 @@ typedef struct hwrm_port_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -30761,14 +33524,89 @@ typedef struct hwrm_port_qcfg_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } hwrm_port_qcfg_output_t, *phwrm_port_qcfg_output_t; +/*********************** + * hwrm_port_mac_qcaps * + ***********************/ + + +/* hwrm_port_mac_qcaps_input (size:192b/24B) */ + +typedef struct hwrm_port_mac_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} hwrm_port_mac_qcaps_input_t, *phwrm_port_mac_qcaps_input_t; + +/* hwrm_port_mac_qcaps_output (size:128b/16B) */ + +typedef struct hwrm_port_mac_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* MAC capability flags */ + uint8_t flags; + /* + * If set to 1, then this field indicates that the + * MAC does not support local loopback. + */ + #define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED UINT32_C(0x1) + /* + * If set to 1, then this field indicates that the + * MAC is capable of supporting remote loopback. + */ + #define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_REMOTE_LPBK_SUPPORTED UINT32_C(0x2) + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_port_mac_qcaps_output_t, *phwrm_port_mac_qcaps_output_t; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -31304,8 +34142,8 @@ typedef struct hwrm_queue_qportcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31401,8 +34239,8 @@ typedef struct hwrm_queue_qcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31446,9 +34284,9 @@ typedef struct hwrm_queue_cfg_input { uint64_t resp_addr; uint32_t flags; /* - * Enumeration denoting the RX, TX, or both directions applicable to the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Enumeration denoting the RX, TX, or both directions applicable to + * the resource. This enumeration is used for resources that are + * similar for both TX and RX paths of the chip. */ #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0 @@ -31505,8 +34343,8 @@ typedef struct hwrm_queue_cfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31605,8 +34443,8 @@ typedef struct hwrm_queue_pfcenable_qcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31705,8 +34543,8 @@ typedef struct hwrm_queue_pfcenable_cfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31856,8 +34694,8 @@ typedef struct hwrm_queue_pri2cos_qcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -31901,9 +34739,9 @@ typedef struct hwrm_queue_pri2cos_cfg_input { uint64_t resp_addr; uint32_t flags; /* - * Enumeration denoting the RX, TX, or both directions applicable to the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * Enumeration denoting the RX, TX, or both directions applicable to + * the resource. This enumeration is used for resources that are + * similar for both TX and RX paths of the chip. */ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3) #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0 @@ -31979,7 +34817,7 @@ typedef struct hwrm_queue_pri2cos_cfg_input { */ uint8_t pri1_cos_queue_id; /* - * CoS Queue assigned to priority 2 This value can only + * CoS Queue assigned to priority 2. This value can only * be changed before traffic has started. */ uint8_t pri2_cos_queue_id; @@ -32026,8 +34864,8 @@ typedef struct hwrm_queue_pri2cos_cfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -32799,8 +35637,8 @@ typedef struct hwrm_queue_cos2bw_qcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33613,8 +36451,8 @@ typedef struct hwrm_queue_cos2bw_cfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33685,8 +36523,8 @@ typedef struct hwrm_queue_dscp_qcaps_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33770,8 +36608,8 @@ typedef struct hwrm_queue_dscp2pri_qcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33865,8 +36703,8 @@ typedef struct hwrm_queue_dscp2pri_cfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -33950,8 +36788,8 @@ typedef struct hwrm_queue_mpls_qcaps_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34073,8 +36911,8 @@ typedef struct hwrm_queue_mplstc2pri_qcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34175,7 +37013,7 @@ typedef struct hwrm_queue_mplstc2pri_cfg_input { */ uint8_t tc1_pri_queue_id; /* - * pri assigned to MPLS TC(EXP) 2 This value can only + * pri assigned to MPLS TC(EXP) 2. This value can only * be changed before traffic has started. */ uint8_t tc2_pri_queue_id; @@ -34221,8 +37059,8 @@ typedef struct hwrm_queue_mplstc2pri_cfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34293,8 +37131,8 @@ typedef struct hwrm_queue_vlanpri_qcaps_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34408,8 +37246,8 @@ typedef struct hwrm_queue_vlanpri2pri_qcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34556,8 +37394,8 @@ typedef struct hwrm_queue_vlanpri2pri_cfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34688,8 +37526,8 @@ typedef struct hwrm_queue_global_cfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34831,13 +37669,1647 @@ typedef struct hwrm_queue_global_qcfg_output { /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; } hwrm_queue_global_qcfg_output_t, *phwrm_queue_global_qcfg_output_t; +/**************************************** + * hwrm_queue_adptv_qos_rx_feature_qcfg * + ****************************************/ + + +/* hwrm_queue_adptv_qos_rx_feature_qcfg_input (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_rx_feature_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_queue_adptv_qos_rx_feature_qcfg_input_t, *phwrm_queue_adptv_qos_rx_feature_qcfg_input_t; + +/* hwrm_queue_adptv_qos_rx_feature_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_rx_feature_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Bitmask indicating which RX CoS queues are enabled or disabled. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is not enabled. + * A value of 1 indicates that the queue is enabled. + */ + uint8_t queue_enable; + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED + /* + * Bitmask indicating which CoS queues are lossy or lossless. + * This setting is kept same across Rx and Tx directions, despite + * the name mentioning only Rx. Each bit represents a specific queue + * where bit 0 represents queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is lossy. + * A value of 1 indicates that the queue is lossless. + */ + uint8_t queue_mode; + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE UINT32_C(0x1) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSY UINT32_C(0x0) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSLESS UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE UINT32_C(0x2) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSY (UINT32_C(0x0) << 1) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSLESS (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE UINT32_C(0x4) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSY (UINT32_C(0x0) << 2) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSLESS (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE UINT32_C(0x8) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSY (UINT32_C(0x0) << 3) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSLESS (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE UINT32_C(0x10) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSY (UINT32_C(0x0) << 4) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSLESS (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE UINT32_C(0x20) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSY (UINT32_C(0x0) << 5) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSLESS (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE UINT32_C(0x40) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSY (UINT32_C(0x0) << 6) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSLESS (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE UINT32_C(0x80) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSY (UINT32_C(0x0) << 7) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSLESS (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSLESS + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_adptv_qos_rx_feature_qcfg_output_t, *phwrm_queue_adptv_qos_rx_feature_qcfg_output_t; + +/*************************************** + * hwrm_queue_adptv_qos_rx_feature_cfg * + ***************************************/ + + +/* hwrm_queue_adptv_qos_rx_feature_cfg_input (size:192b/24B) */ + +typedef struct hwrm_queue_adptv_qos_rx_feature_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* This bit must be '1' for the queue_enable field to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE UINT32_C(0x1) + /* This bit must be '1' for the queue_mode field to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_MODE UINT32_C(0x2) + /* + * Bitmask indicating which RX CoS queues are enabled or disabled. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is not enabled. + * A value of 1 indicates that the queue is enabled. + */ + uint8_t queue_enable; + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED + /* + * Bitmask indicating which CoS queues are lossy or lossless. + * This setting is kept symmetric (or same) across Tx and Rx. + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is lossy. + * A value of 1 indicates that the queue is lossless. + */ + uint8_t queue_mode; + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE UINT32_C(0x1) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSY UINT32_C(0x0) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSLESS UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE UINT32_C(0x2) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSY (UINT32_C(0x0) << 1) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSLESS (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE UINT32_C(0x4) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSY (UINT32_C(0x0) << 2) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSLESS (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE UINT32_C(0x8) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSY (UINT32_C(0x0) << 3) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSLESS (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE UINT32_C(0x10) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSY (UINT32_C(0x0) << 4) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSLESS (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE UINT32_C(0x20) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSY (UINT32_C(0x0) << 5) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSLESS (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE UINT32_C(0x40) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSY (UINT32_C(0x0) << 6) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSLESS (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSLESS + /* If set to 0, then the queue is lossy, else lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE UINT32_C(0x80) + /* Lossy (best-effort). */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSY (UINT32_C(0x0) << 7) + /* Lossless. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSLESS (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LAST HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSLESS + uint8_t unused_0[2]; +} hwrm_queue_adptv_qos_rx_feature_cfg_input_t, *phwrm_queue_adptv_qos_rx_feature_cfg_input_t; + +/* hwrm_queue_adptv_qos_rx_feature_cfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_rx_feature_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_adptv_qos_rx_feature_cfg_output_t, *phwrm_queue_adptv_qos_rx_feature_cfg_output_t; + +/**************************************** + * hwrm_queue_adptv_qos_tx_feature_qcfg * + ****************************************/ + + +/* hwrm_queue_adptv_qos_tx_feature_qcfg_input (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_tx_feature_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_queue_adptv_qos_tx_feature_qcfg_input_t, *phwrm_queue_adptv_qos_tx_feature_qcfg_input_t; + +/* hwrm_queue_adptv_qos_tx_feature_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_tx_feature_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Bitmask indicating which TX CoS queues are enabled or disabled. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is not enabled. + * A value of 1 indicates that the queue is enabled. + */ + uint8_t queue_enable; + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_adptv_qos_tx_feature_qcfg_output_t, *phwrm_queue_adptv_qos_tx_feature_qcfg_output_t; + +/*************************************** + * hwrm_queue_adptv_qos_tx_feature_cfg * + ***************************************/ + + +/* hwrm_queue_adptv_qos_tx_feature_cfg_input (size:192b/24B) */ + +typedef struct hwrm_queue_adptv_qos_tx_feature_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* This bit must be '1' for the queue_enable field to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE UINT32_C(0x1) + /* + * Bitmask indicating which TX CoS queues are enabled or disabled. + * + * Each bit represents a specific queue where bit 0 represents + * queue 0 and bit 7 represents queue 7. + * A value of 0 indicates that the queue is not enabled. + * A value of 1 indicates that the queue is enabled. + */ + uint8_t queue_enable; + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED + /* If set to 1, then the queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80) + /* Queue is disabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7) + /* Queue is enabled. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7) + #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_LAST HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED + uint8_t unused_0[3]; +} hwrm_queue_adptv_qos_tx_feature_cfg_input_t, *phwrm_queue_adptv_qos_tx_feature_cfg_input_t; + +/* hwrm_queue_adptv_qos_tx_feature_cfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_tx_feature_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_adptv_qos_tx_feature_cfg_output_t, *phwrm_queue_adptv_qos_tx_feature_cfg_output_t; + +/******************** + * hwrm_queue_qcaps * + ********************/ + + +/* hwrm_queue_qcaps_input (size:128b/16B) */ + +typedef struct hwrm_queue_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_queue_qcaps_input_t, *phwrm_queue_qcaps_input_t; + +/* hwrm_queue_qcaps_output (size:256b/32B) */ + +typedef struct hwrm_queue_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Adaptive QoS RX feature parameter capability flags. */ + uint32_t rx_feature_params; + /* + * When this bit is '1' the capability to configure queue_enable + * is supported. + * If set to '0', then the capability to configure queue_enable + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_ENABLE_CAP UINT32_C(0x1) + /* + * When this bit is '1' the capability to configure queue_mode + * is supported. + * If set to '0', then the capability to configure queue_mode + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_MODE_CAP UINT32_C(0x2) + /* Adaptive QoS TX feature parameter capability flags. */ + uint32_t tx_feature_params; + /* + * When this bit is '1' the capability to configure queue_enable + * is supported. + * If set to '0', then the capability to configure queue_enable + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_FEATURE_PARAMS_QUEUE_ENABLE_CAP UINT32_C(0x1) + /* + * The maximum number of queues that can be configured on this device. + * Valid values range from 1 through 8. + */ + uint8_t max_configurable_queues; + uint8_t unused_0[3]; + /* Adaptive QoS RX tuning parameter capability flags. */ + uint32_t rx_tuning_params; + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_COST_CAP UINT32_C(0x1) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP UINT32_C(0x2) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP UINT32_C(0x4) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_PCIE_BW_EFF_CAP UINT32_C(0x8) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_XOFF_HEADROOM_FACTOR_CAP UINT32_C(0x10) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MIN_LATENCY_CAP UINT32_C(0x20) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MAX_LATENCY_CAP UINT32_C(0x40) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP UINT32_C(0x80) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP UINT32_C(0x100) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_PIPE_COS_LATENCY_CAP UINT32_C(0x200) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_PIPE_COS_LATENCY_CAP UINT32_C(0x400) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_COS_SHARED_MIN_RATIO_CAP UINT32_C(0x800) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP UINT32_C(0x1000) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP UINT32_C(0x2000) + /* Adaptive QoS TX tuning parameter capability flags. */ + uint32_t tx_tuning_params; + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_COST_CAP UINT32_C(0x1) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP UINT32_C(0x2) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP UINT32_C(0x4) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP UINT32_C(0x8) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MIN_LATENCY_CAP UINT32_C(0x10) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MAX_LATENCY_CAP UINT32_C(0x20) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP UINT32_C(0x40) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP UINT32_C(0x80) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_MAX_TBM_CELLS_PRERESERVED_CAP UINT32_C(0x100) + /* + * When this bit is '1' the capability to configure the option + * is supported. + * If set to '0', then the capability to configure the option + * is not supported. + */ + #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP UINT32_C(0x200) + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_qcaps_output_t, *phwrm_queue_qcaps_output_t; + +/*************************************** + * hwrm_queue_adptv_qos_rx_tuning_qcfg * + ***************************************/ + + +/* hwrm_queue_adptv_qos_rx_tuning_qcfg_input (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_rx_tuning_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_queue_adptv_qos_rx_tuning_qcfg_input_t, *phwrm_queue_adptv_qos_rx_tuning_qcfg_input_t; + +/* hwrm_queue_adptv_qos_rx_tuning_qcfg_output (size:576b/72B) */ + +typedef struct hwrm_queue_adptv_qos_rx_tuning_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Indicates max credit as required by hardware. */ + uint32_t wfq_cost; + /* + * Specifies a factor that determines the upper bound for each + * cos_wfq_credit_weight. + */ + uint32_t wfq_upper_factor; + /* + * The algorithm multiplies this factor by the MRU size to compute the + * hysteresis window size which in turn is used in deassert + * threshold calculations. + */ + uint32_t hyst_window_size_factor; + /* + * Specifies PCIe BW efficiency in the range of 0-100%. System + * characterization determines the value of this parameter. A value of + * less than 100% accounts for internal PCIe over-subscription. The + * algorithm uses this parameter to determine the PCIe BW available + * for transferring received packets to the host. + */ + uint32_t pcie_bw_eff; + /* Scales the number of cells for xoff. */ + uint32_t xoff_headroom_factor; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_max_latency; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_max_latency; + /* + * The algorithm uses this parameter to calculate the number of cells + * to be excluded from the total buffer pool to account for the + * latency of pipeline post RE_DEC to PCIe block. Its value is derived + * from system characterization. + */ + uint32_t l2_pipe_cos_latency; + /* + * The algorithm uses this parameter to calculate the number of cells + * to be excluded from the total buffer pool to account for the + * latency of pipeline post RE_DEC to PCIe block. Its value is derived + * from system characterization. + */ + uint32_t roce_pipe_cos_latency; + /* Sets the minimum number of shared cells each cos queue can have. */ + uint32_t cos_shared_min_ratio; + /* + * The parameter limits the total reserved cells. If the computed + * total reserved cells becomes larger than rsvd_cells_limit_ratio x + * port_cells_avail, then the reserved cells are set to the limit + * value. Its range of values is 0-50%. + */ + uint32_t rsvd_cells_limit_ratio; + /* + * This parameter is used to compute the time interval for + * replenishing the shaper credit buckets for all RX cos queues. + */ + uint32_t shaper_refill_timer; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_adptv_qos_rx_tuning_qcfg_output_t, *phwrm_queue_adptv_qos_rx_tuning_qcfg_output_t; + +/************************************** + * hwrm_queue_adptv_qos_rx_tuning_cfg * + **************************************/ + + +/* hwrm_queue_adptv_qos_rx_tuning_cfg_input (size:640b/80B) */ + +typedef struct hwrm_queue_adptv_qos_rx_tuning_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_COST UINT32_C(0x1) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR UINT32_C(0x2) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR UINT32_C(0x4) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_PCIE_BW_EFF UINT32_C(0x8) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_XOFF_HEADROOM_FACTOR UINT32_C(0x10) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY UINT32_C(0x20) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY UINT32_C(0x40) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY UINT32_C(0x80) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY UINT32_C(0x100) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_PIPE_COS_LATENCY UINT32_C(0x200) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_PIPE_COS_LATENCY UINT32_C(0x400) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_COS_SHARED_MIN_RATIO UINT32_C(0x800) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO UINT32_C(0x1000) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER UINT32_C(0x2000) + /* Indicates max credit as required by hardware. */ + uint32_t wfq_cost; + /* + * Specifies a factor that determines the upper bound for each + * cos_wfq_credit_weight. + */ + uint32_t wfq_upper_factor; + /* + * The algorithm multiplies this factor by the MRU size to compute the + * hysteresis window size which in turn is used in deassert + * threshold calculations. + */ + uint32_t hyst_window_size_factor; + /* + * Specifies PCIe BW efficiency in the range of 0-100%. System + * characterization determines the value of this parameter. A value of + * less than 100% accounts for internal PCIe over-subscription. The + * algorithm uses this parameter to determine the PCIe BW available + * for transferring received packets to the host. + */ + uint32_t pcie_bw_eff; + /* Scales the number of cells for xoff. */ + uint32_t xoff_headroom_factor; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_max_latency; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_max_latency; + /* + * The algorithm uses this parameter to calculate the number of cells + * to be excluded from the total buffer pool to account for the + * latency of pipeline post RE_DEC to PCIe block. Its value is derived + * from system characterization. + */ + uint32_t l2_pipe_cos_latency; + /* + * The algorithm uses this parameter to calculate the number of cells + * to be excluded from the total buffer pool to account for the + * latency of pipeline post RE_DEC to PCIe block. Its value is derived + * from system characterization. + */ + uint32_t roce_pipe_cos_latency; + /* Sets the minimum number of shared cells each cos queue can have. */ + uint32_t cos_shared_min_ratio; + /* + * The parameter limits the total reserved cells. If the computed + * total reserved cells becomes larger than rsvd_cells_limit_ratio x + * port_cells_avail, then the reserved cells are set to the limit + * value. Its range of values is 0-50%. + */ + uint32_t rsvd_cells_limit_ratio; + /* + * This parameter is used to compute the time interval for + * replenishing the shaper credit buckets for all RX cos queues. + */ + uint32_t shaper_refill_timer; + uint8_t unused_0[4]; +} hwrm_queue_adptv_qos_rx_tuning_cfg_input_t, *phwrm_queue_adptv_qos_rx_tuning_cfg_input_t; + +/* hwrm_queue_adptv_qos_rx_tuning_cfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_rx_tuning_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_adptv_qos_rx_tuning_cfg_output_t, *phwrm_queue_adptv_qos_rx_tuning_cfg_output_t; + +/*************************************** + * hwrm_queue_adptv_qos_tx_tuning_qcfg * + ***************************************/ + + +/* hwrm_queue_adptv_qos_tx_tuning_qcfg_input (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_tx_tuning_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_queue_adptv_qos_tx_tuning_qcfg_input_t, *phwrm_queue_adptv_qos_tx_tuning_qcfg_input_t; + +/* hwrm_queue_adptv_qos_tx_tuning_qcfg_output (size:448b/56B) */ + +typedef struct hwrm_queue_adptv_qos_tx_tuning_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Indicates max credit as required by hardware. */ + uint32_t wfq_cost; + /* + * Specifies a factor that determines the upper bound for each + * cos_wfq_credit_weight. + */ + uint32_t wfq_upper_factor; + /* + * The algorithm multiplies this factor by the MRU size to compute the + * hysteresis window size which in turn is used in deassert + * threshold calculations. + */ + uint32_t hyst_window_size_factor; + /* + * The parameter limits the total reserved cells. If the computed + * total reserved cells becomes larger than rsvd_cells_limit_ratio x + * port_cells_avail, then the reserved cells are set to the limit + * value. Its range of values is 0-50%. + */ + uint32_t rsvd_cells_limit_ratio; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_max_latency; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_max_latency; + /* Specifies the number of reserved cells TRP requires per cos queue. */ + uint32_t max_tbm_cells_prereserved; + /* + * This parameter is used to compute the time interval for + * replenishing the shaper credit buckets for all TX cos queues. + */ + uint32_t shaper_refill_timer; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_adptv_qos_tx_tuning_qcfg_output_t, *phwrm_queue_adptv_qos_tx_tuning_qcfg_output_t; + +/************************************** + * hwrm_queue_adptv_qos_tx_tuning_cfg * + **************************************/ + + +/* hwrm_queue_adptv_qos_tx_tuning_cfg_input (size:512b/64B) */ + +typedef struct hwrm_queue_adptv_qos_tx_tuning_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_COST UINT32_C(0x1) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR UINT32_C(0x2) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR UINT32_C(0x4) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO UINT32_C(0x8) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY UINT32_C(0x10) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY UINT32_C(0x20) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY UINT32_C(0x40) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY UINT32_C(0x80) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_MAX_TBM_CELLS_PRERESERVED UINT32_C(0x100) + /* This bit must be '1' for the option to be configured. */ + #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER UINT32_C(0x200) + /* Indicates max credit as required by hardware. */ + uint32_t wfq_cost; + /* + * Specifies a factor that determines the upper bound for each + * cos_wfq_credit_weight. + */ + uint32_t wfq_upper_factor; + /* + * The algorithm multiplies this factor by the MRU size to compute the + * hysteresis window size which in turn is used in deassert + * threshold calculations. + */ + uint32_t hyst_window_size_factor; + /* + * The parameter limits the total reserved cells. If the computed + * total reserved cells becomes larger than rsvd_cells_limit_ratio x + * port_cells_avail, then the reserved cells are set to the limit + * value. Its range of values is 0-50%. + */ + uint32_t rsvd_cells_limit_ratio; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for L2. Its value is derived from system + * characterization. + */ + uint32_t l2_max_latency; + /* + * It is used to calculate the number of reserved cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_min_latency; + /* + * It is used to calculate the number of shared cells for cos queues + * configured for RoCE. Its value is derived from system + * characterization. + */ + uint32_t roce_max_latency; + /* Specifies the number of reserved cells TRP requires per cos queue. */ + uint32_t max_tbm_cells_prereserved; + /* + * This parameter is used to compute the time interval for + * replenishing the shaper credit buckets for all TX cos queues. + */ + uint32_t shaper_refill_timer; + uint8_t unused_0[4]; +} hwrm_queue_adptv_qos_tx_tuning_cfg_input_t, *phwrm_queue_adptv_qos_tx_tuning_cfg_input_t; + +/* hwrm_queue_adptv_qos_tx_tuning_cfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_adptv_qos_tx_tuning_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_adptv_qos_tx_tuning_cfg_output_t, *phwrm_queue_adptv_qos_tx_tuning_cfg_output_t; + +/********************************** + * hwrm_queue_pfcwd_timeout_qcaps * + **********************************/ + + +/* hwrm_queue_pfcwd_timeout_qcaps_input (size:128b/16B) */ + +typedef struct hwrm_queue_pfcwd_timeout_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_queue_pfcwd_timeout_qcaps_input_t, *phwrm_queue_pfcwd_timeout_qcaps_input_t; + +/* hwrm_queue_pfcwd_timeout_qcaps_output (size:128b/16B) */ + +typedef struct hwrm_queue_pfcwd_timeout_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Max configurable pfc watchdog timeout value in msec. */ + uint32_t max_pfcwd_timeout; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_pfcwd_timeout_qcaps_output_t, *phwrm_queue_pfcwd_timeout_qcaps_output_t; + +/******************************** + * hwrm_queue_pfcwd_timeout_cfg * + ********************************/ + + +/* hwrm_queue_pfcwd_timeout_cfg_input (size:192b/24B) */ + +typedef struct hwrm_queue_pfcwd_timeout_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* pfc watchdog timeout value in msec. */ + uint32_t pfcwd_timeout_value; + uint8_t unused_0[4]; +} hwrm_queue_pfcwd_timeout_cfg_input_t, *phwrm_queue_pfcwd_timeout_cfg_input_t; + +/* hwrm_queue_pfcwd_timeout_cfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_pfcwd_timeout_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_pfcwd_timeout_cfg_output_t, *phwrm_queue_pfcwd_timeout_cfg_output_t; + +/********************************* + * hwrm_queue_pfcwd_timeout_qcfg * + *********************************/ + + +/* hwrm_queue_pfcwd_timeout_qcfg_input (size:128b/16B) */ + +typedef struct hwrm_queue_pfcwd_timeout_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_queue_pfcwd_timeout_qcfg_input_t, *phwrm_queue_pfcwd_timeout_qcfg_input_t; + +/* hwrm_queue_pfcwd_timeout_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_queue_pfcwd_timeout_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Current configured pfc watchdog timeout value in msec. */ + uint32_t pfcwd_timeout_value; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_queue_pfcwd_timeout_qcfg_output_t, *phwrm_queue_pfcwd_timeout_qcfg_output_t; + /******************* * hwrm_vnic_alloc * *******************/ @@ -34911,9 +39383,9 @@ typedef struct hwrm_vnic_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -34985,23 +39457,18 @@ typedef struct hwrm_vnic_update_input { #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP /* * The metadata format type used in all the RX packet completions - * going through this VNIC. + * going through this VNIC. This value is product specific. Refer to + * the L2 HSI completion ring structures for the detailed + * descriptions. For Thor and Thor2, it corresponds to 'meta_format' + * in 'rx_pkt_cmpl_hi' and 'rx_pkt_v3_cmpl_hi', respectively. */ uint8_t metadata_format_type; - /* No metadata information. */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE UINT32_C(0x0) - /* - * Action record pointer (table_scope[4:0], act_rec_ptr[25:0], - * vtag[19:0]). - */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR UINT32_C(0x1) - /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID UINT32_C(0x2) - /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA UINT32_C(0x3) - /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS UINT32_C(0x4) - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 /* * The maximum receive unit of the vnic. * Each vnic is associated with a function. @@ -35028,7 +39495,7 @@ typedef struct hwrm_vnic_update_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -35092,9 +39559,9 @@ typedef struct hwrm_vnic_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -35242,25 +39709,28 @@ typedef struct hwrm_vnic_cfg_input { #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID UINT32_C(0x40) /* This bit must be '1' for the queue_id field to be configured. */ #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID UINT32_C(0x80) - /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */ + /* + * This bit must be '1' for the rx_csum_v2_mode field to be + * configured. + */ #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE UINT32_C(0x100) /* This bit must be '1' for the l2_cqe_mode field to be configured. */ #define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE UINT32_C(0x200) /* Logical vnic ID */ uint16_t vnic_id; /* - * Default Completion ring for the VNIC. This ring will + * Default Completion ring for the VNIC. This ring will * be chosen if packet does not match any RSS rules and if * there is no COS rule. */ uint16_t dflt_ring_grp; /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if * there is no RSS rule. */ uint16_t rss_rule; /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if * there is no COS rule. */ uint16_t cos_rule; @@ -35279,7 +39749,7 @@ typedef struct hwrm_vnic_cfg_input { */ uint16_t mru; /* - * Default Rx ring for the VNIC. This ring will + * Default Rx ring for the VNIC. This ring will * be chosen if packet does not match any RSS rules. * The aggregation ring associated with the Rx ring is * implied based on the Rx ring specified when the @@ -35287,16 +39757,17 @@ typedef struct hwrm_vnic_cfg_input { */ uint16_t default_rx_ring_id; /* - * Default completion ring for the VNIC. This ring will + * Default completion ring for the VNIC. This ring will * be chosen if packet does not match any RSS rules. */ uint16_t default_cmpl_ring_id; /* - * When specified, only incoming packets classified to the specified CoS - * queue ID will be arriving on this VNIC. Packet priority to CoS mapping - * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, - * ntuple filters with VNIC destination specified are invalid since they - * conflict with the CoS to VNIC steering rules in this mode. + * When specified, only incoming packets classified to the specified + * CoS queue ID will be arriving on this VNIC. Packet priority to CoS + * mapping rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this + * mode, ntuple filters with VNIC destination specified are invalid + * since they conflict with the CoS to VNIC steering rules in this + * mode. * * If this field is not specified, packet to VNIC steering will be * subject to the standard L2 filter rules and any additional ntuple @@ -35316,7 +39787,7 @@ typedef struct hwrm_vnic_cfg_input { * the number of header groups in the delivered packet with a valid * L4 checksum are reported. Valid checksums are counted from the * outermost header group to the innermost header group, stopping at - * the first error. This is the default checksum mode supported if + * the first error. This is the default checksum mode supported if * the driver doesn't explicitly configure the RX checksum mode. */ #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) @@ -35382,9 +39853,9 @@ typedef struct hwrm_vnic_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -35453,12 +39924,12 @@ typedef struct hwrm_vnic_qcfg_output { /* Default Completion ring for the VNIC. */ uint16_t dflt_ring_grp; /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if * there is no RSS rule. */ uint16_t rss_rule; /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if * there is no COS rule. */ uint16_t cos_rule; @@ -35538,9 +40009,9 @@ typedef struct hwrm_vnic_qcfg_output { /* When this bit is '1' it indicates port cos_mapping_mode enabled. */ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x100) /* - * When returned with a valid CoS Queue id, the CoS Queue/VNIC association - * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS - * queue association. + * When returned with a valid CoS Queue id, the CoS Queue/VNIC + * association is valid. Otherwise it will return 0xFFFF to indicate no + * VNIC/CoS queue association. */ uint16_t queue_id; /* @@ -35558,7 +40029,7 @@ typedef struct hwrm_vnic_qcfg_output { #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) /* * This value indicates that the VNIC is configured to use the RX - * checksum ‘all_ok’ mode for all the rings associated with this + * checksum 'all_ok' mode for all the rings associated with this * VNIC. */ #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) @@ -35591,12 +40062,33 @@ typedef struct hwrm_vnic_qcfg_output { */ #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED - uint8_t unused_1[3]; + /* + * This field conveys the metadata format type that has been + * configured. This value is product specific. Refer to the L2 HSI + * completion ring structures for the detailed descriptions. For Thor + * and Thor2, it corresponds to 'meta_format' in 'rx_pkt_cmpl_hi' and + * 'rx_pkt_v3_cmpl_hi', respectively. + */ + uint8_t metadata_format_type; + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_LAST HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 + /* This field conveys the VNIC operation state. */ + uint8_t vnic_state; + /* Normal operation state. */ + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0) + /* Drop all packets. */ + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_LAST HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP + uint8_t unused_1; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -35715,10 +40207,10 @@ typedef struct hwrm_vnic_qcaps_output { /* * When this bit is '1', it indicates that firmware supports the * ability to steer incoming packets from one CoS queue to one - * VNIC. This optional feature can then be enabled - * using HWRM_VNIC_CFG on any VNIC. This feature is only - * available when NVM option “enable_cos_classification” is set - * to 1. If set to '0', firmware does not support this feature. + * VNIC. This optional feature can then be enabled + * using HWRM_VNIC_CFG on any VNIC. This feature is only + * available when NVM option 'enable_cos_classification' is set + * to 1. If set to '0', firmware does not support this feature. */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP UINT32_C(0x100) /* @@ -35776,8 +40268,8 @@ typedef struct hwrm_vnic_qcaps_output { #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP UINT32_C(0x8000) /* * When this bit is '1', it indicates that HW is capable of using - * XOR algorithm. This mode uses XOR algorithm to hash the packets - * according to the configured hash type and hash mode. The XOR + * XOR algorithm. This mode uses 'XOR' algorithm to hash the packets + * according to the configured hash type and hash mode. The XOR * hash results and the provided XOR RSS indirection table are * used to determine the RSS rings. Host drivers provided hash key * is not honored in this mode. @@ -35790,7 +40282,7 @@ typedef struct hwrm_vnic_qcaps_output { * algorithm to calculate the hash to convey it in the RX * completions. Host drivers should provide Toeplitz hash key. * As HW uses innermost packets checksum to distribute the packets - * across the rings, host drivers can't convey hash mode to choose + * across the rings, host drivers can't convey hash mode to choose * outer headers to calculate Toeplitz hash. FW will fail such * configuration. */ @@ -35853,6 +40345,8 @@ typedef struct hwrm_vnic_qcaps_output { #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED UINT32_C(0x8000000) /* When this bit is '1' FW supports VNIC hash mode. */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP UINT32_C(0x10000000) + /* When this bit is set to '1', hardware supports tunnel TPA. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_HW_TUNNEL_TPA_CAP UINT32_C(0x20000000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2 or v3. @@ -35862,9 +40356,9 @@ typedef struct hwrm_vnic_qcaps_output { uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -35875,7 +40369,7 @@ typedef struct hwrm_vnic_qcaps_output { *********************/ -/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ +/* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ typedef struct hwrm_vnic_tpa_cfg_input { /* The HWRM command request type. */ @@ -35987,8 +40481,13 @@ typedef struct hwrm_vnic_tpa_cfg_input { * configured. */ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) - /* deprecated bit. Do not use!!! */ + /* deprecated bit. Do not use!!! */ #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) + /* + * This bit must be '1' for the tnl_tpa_en_bitmap field to be + * configured. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_TNL_TPA_EN UINT32_C(0x10) /* Logical vnic ID */ uint16_t vnic_id; /* @@ -36039,10 +40538,104 @@ typedef struct hwrm_vnic_tpa_cfg_input { /* * This is the minimum amount of payload length required to * start an aggregation context. This field is deprecated and - * should be set to 0. The minimum length is set by firmware + * should be set to 0. The minimum length is set by firmware * and can be queried using hwrm_vnic_tpa_qcfg. */ uint32_t min_agg_len; + /* + * If the device supports hardware tunnel TPA feature, as indicated by + * the HWRM_VNIC_QCAPS command, this field is used to configure the + * tunnel types to be enabled. Each bit corresponds to a specific + * tunnel type. If a bit is set to '1', then the associated tunnel + * type is enabled; otherwise, it is disabled. + */ + uint32_t tnl_tpa_en_bitmap; + /* + * When this bit is '1', enable VXLAN encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN UINT32_C(0x1) + /* + * When this bit is set to '1', enable GENEVE encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GENEVE UINT32_C(0x2) + /* + * When this bit is set to '1', enable NVGRE encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_NVGRE UINT32_C(0x4) + /* + * When this bit is set to '1', enable GRE encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE UINT32_C(0x8) + /* + * When this bit is set to '1', enable IPV4 encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV4 UINT32_C(0x10) + /* + * When this bit is set to '1', enable IPV6 encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV6 UINT32_C(0x20) + /* + * When this bit is '1', enable VXLAN_GPE encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE UINT32_C(0x40) + /* + * When this bit is '1', enable VXLAN_CUSTOMER1 encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 UINT32_C(0x80) + /* + * When this bit is '1', enable GRE_CUSTOMER1 encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 UINT32_C(0x100) + /* + * When this bit is '1', enable UPAR1 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR1 UINT32_C(0x200) + /* + * When this bit is '1', enable UPAR2 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR2 UINT32_C(0x400) + /* + * When this bit is '1', enable UPAR3 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR3 UINT32_C(0x800) + /* + * When this bit is '1', enable UPAR4 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR4 UINT32_C(0x1000) + /* + * When this bit is '1', enable UPAR5 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR5 UINT32_C(0x2000) + /* + * When this bit is '1', enable UPAR6 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR6 UINT32_C(0x4000) + /* + * When this bit is '1', enable UPAR7 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR7 UINT32_C(0x8000) + /* + * When this bit is '1', enable UPAR8 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR8 UINT32_C(0x10000) + uint8_t unused_1[4]; } hwrm_vnic_tpa_cfg_input_t, *phwrm_vnic_tpa_cfg_input_t; /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ @@ -36059,9 +40652,9 @@ typedef struct hwrm_vnic_tpa_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -36220,12 +40813,105 @@ typedef struct hwrm_vnic_tpa_qcfg_output { * start an aggregation context. */ uint32_t min_agg_len; - uint8_t unused_0[7]; + /* + * If the device supports hardware tunnel TPA feature, as indicated by + * the HWRM_VNIC_QCAPS command, this field conveys the bitmap of the + * tunnel types that have been configured. Each bit corresponds to a + * specific tunnel type. If a bit is set to '1', then the associated + * tunnel type is enabled; otherwise, it is disabled. + */ + uint32_t tnl_tpa_en_bitmap; + /* + * When this bit is '1', enable VXLAN encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN UINT32_C(0x1) + /* + * When this bit is set to '1', enable GENEVE encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GENEVE UINT32_C(0x2) + /* + * When this bit is set to '1', enable NVGRE encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_NVGRE UINT32_C(0x4) + /* + * When this bit is set to '1', enable GRE encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE UINT32_C(0x8) + /* + * When this bit is set to '1', enable IPV4 encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV4 UINT32_C(0x10) + /* + * When this bit is set to '1', enable IPV6 encapsulated packets + * for aggregation.. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV6 UINT32_C(0x20) + /* + * When this bit is '1', enable VXLAN_GPE encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE UINT32_C(0x40) + /* + * When this bit is '1', enable VXLAN_CUSTOMER1 encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 UINT32_C(0x80) + /* + * When this bit is '1', enable GRE_CUSTOMER1 encapsulated packets + * for aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 UINT32_C(0x100) + /* + * When this bit is '1', enable UPAR1 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR1 UINT32_C(0x200) + /* + * When this bit is '1', enable UPAR2 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR2 UINT32_C(0x400) + /* + * When this bit is '1', enable UPAR3 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR3 UINT32_C(0x800) + /* + * When this bit is '1', enable UPAR4 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR4 UINT32_C(0x1000) + /* + * When this bit is '1', enable UPAR5 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR5 UINT32_C(0x2000) + /* + * When this bit is '1', enable UPAR6 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR6 UINT32_C(0x4000) + /* + * When this bit is '1', enable UPAR7 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR7 UINT32_C(0x8000) + /* + * When this bit is '1', enable UPAR8 encapsulated packets for + * aggregation. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR8 UINT32_C(0x10000) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -36418,7 +41104,7 @@ typedef struct hwrm_vnic_rss_cfg_input { * specified headers. It is an error to set this flag concurrently * with hash_type_exclude. */ - #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE UINT32_C(0x1) /* * When this bit is '1', it indicates that the hash_type field is * interpreted as a change relative the current configuration. Each @@ -36430,7 +41116,12 @@ typedef struct hwrm_vnic_rss_cfg_input { * remove the specified headers. It is an error to set this flag * concurrently with hash_type_include. */ - #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE UINT32_C(0x2) + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE UINT32_C(0x2) + /* + * When this bit is '1', it indicates that the support of setting + * ipsec hash_types by the host drivers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT UINT32_C(0x4) uint8_t ring_select_mode; /* * In this mode, HW uses Toeplitz algorithm and provided Toeplitz @@ -36476,9 +41167,9 @@ typedef struct hwrm_vnic_rss_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -36719,9 +41410,9 @@ typedef struct hwrm_vnic_rss_qcfg_output { uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -36901,7 +41592,7 @@ typedef struct hwrm_vnic_plcmodes_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -37046,7 +41737,7 @@ typedef struct hwrm_vnic_plcmodes_qcfg_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -37109,9 +41800,9 @@ typedef struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -37172,9 +41863,9 @@ typedef struct hwrm_vnic_rss_cos_lb_ctx_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -37257,6 +41948,11 @@ typedef struct hwrm_ring_alloc_input { * configured. */ #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE UINT32_C(0x400) + /* + * This bit must be '1' for the steering_tag field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_STEERING_TAG_VALID UINT32_C(0x800) /* Ring Type. */ uint8_t ring_type; /* L2 Completion Ring (CR) */ @@ -37393,7 +42089,7 @@ typedef struct hwrm_ring_alloc_input { /* Used by a PF driver to associate a SCHQ with one of its TX rings. */ uint16_t schq_id; /* - * Number of 16B units in the ring. Minimum size for + * Number of 16B units in the ring. Minimum size for * a ring is 16 16B entries. */ uint32_t length; @@ -37470,7 +42166,8 @@ typedef struct hwrm_ring_alloc_input { */ #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK UINT32_C(0xff00) #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 - uint16_t unused_3; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; /* * This field is reserved for the future use. * It shall be set to 0. @@ -37606,9 +42303,9 @@ typedef struct hwrm_ring_alloc_output { uint8_t unused_0[2]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -37711,9 +42408,9 @@ typedef struct hwrm_ring_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -37766,7 +42463,7 @@ typedef struct hwrm_ring_reset_input { /* RoCE Notification Completion Ring (ROCE_CR) */ #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) /* - * Rx Ring Group. This is to reset rx and aggregation in an atomic + * Rx Ring Group. This is to reset rx and aggregation in an atomic * operation. Completion ring associated with this ring group is * not reset. */ @@ -37807,9 +42504,9 @@ typedef struct hwrm_ring_reset_output { uint8_t consumer_idx[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -37962,7 +42659,7 @@ typedef struct hwrm_ring_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -38102,7 +42799,7 @@ typedef struct hwrm_ring_qcfg_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -38187,8 +42884,8 @@ typedef struct hwrm_ring_aggint_qcaps_output { */ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR UINT32_C(0x10) /* - * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured - * on completion rings. + * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be + * configured on completion rings. */ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x20) /* @@ -38197,8 +42894,8 @@ typedef struct hwrm_ring_aggint_qcaps_output { */ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR UINT32_C(0x40) /* - * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured - * on completion rings. + * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be + * configured on completion rings. */ #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT UINT32_C(0x80) /* @@ -38245,9 +42942,9 @@ typedef struct hwrm_ring_aggint_qcaps_output { uint8_t unused_0[1]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -38361,9 +43058,9 @@ typedef struct hwrm_ring_cmpl_ring_qaggint_params_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -38470,8 +43167,8 @@ typedef struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { */ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR UINT32_C(0x1) /* - * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be - * configured. + * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to + * be configured. */ #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x2) /* @@ -38511,9 +43208,9 @@ typedef struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -38567,7 +43264,7 @@ typedef struct hwrm_ring_grp_alloc_input { uint16_t rr; /* * This value identifies the aggregation RR associated with - * the ring group. If this value is 0xFF... (All Fs), then no + * the ring group. If this value is 0xFF... (All Fs), then no * Aggregation ring will be set. */ uint16_t ar; @@ -38590,7 +43287,7 @@ typedef struct hwrm_ring_grp_alloc_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * This is the ring group ID value. Use this value to program + * This is the ring group ID value. Use this value to program * the default ring group for the VNIC or as table entries * in an RSS/COS context. */ @@ -38598,9 +43295,9 @@ typedef struct hwrm_ring_grp_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -38661,9 +43358,9 @@ typedef struct hwrm_ring_grp_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -39133,9 +43830,9 @@ typedef struct hwrm_ring_schq_alloc_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -39192,8 +43889,8 @@ typedef struct hwrm_ring_schq_cfg_input { uint32_t flags; /* The tc_max_bw array and the max_bw parameters are valid */ #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED UINT32_C(0x1) - /* The tc_min_bw array is valid */ - #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED UINT32_C(0x2) + /* The tc_bw_reservation array is valid */ + #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_RESERVATION_ENABLED UINT32_C(0x2) /* Maximum bandwidth of the traffic class, specified in Mbps. */ uint32_t max_bw_tc0; /* Maximum bandwidth of the traffic class, specified in Mbps. */ @@ -39211,61 +43908,61 @@ typedef struct hwrm_ring_schq_cfg_input { /* Maximum bandwidth of the traffic class, specified in Mbps. */ uint32_t max_bw_tc7; /* - * Bandwidth reservation for the traffic class, specified in Mbps. + * Bandwidth reservation for the traffic class, specified in percent. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of * the default SCHQ. */ - uint32_t min_bw_tc0; + uint32_t tc_bw_reservation0; /* - * Bandwidth reservation for the traffic class, specified in Mbps. + * Bandwidth reservation for the traffic class, specified in percent. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of * the default SCHQ. */ - uint32_t min_bw_tc1; + uint32_t tc_bw_reservation1; /* - * Bandwidth reservation for the traffic class, specified in Mbps. + * Bandwidth reservation for the traffic class, specified in percent. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of * the default SCHQ. */ - uint32_t min_bw_tc2; + uint32_t tc_bw_reservation2; /* - * Bandwidth reservation for the traffic class, specified in Mbps. + * Bandwidth reservation for the traffic class, specified in percent. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of * the default SCHQ. */ - uint32_t min_bw_tc3; + uint32_t tc_bw_reservation3; /* - * Bandwidth reservation for the traffic class, specified in Mbps. + * Bandwidth reservation for the traffic class, specified in percent. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of * the default SCHQ. */ - uint32_t min_bw_tc4; + uint32_t tc_bw_reservation4; /* - * Bandwidth reservation for the traffic class, specified in Mbps. + * Bandwidth reservation for the traffic class, specified in percent. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of * the default SCHQ. */ - uint32_t min_bw_tc5; + uint32_t tc_bw_reservation5; /* - * Bandwidth reservation for the traffic class, specified in Mbps. + * Bandwidth reservation for the traffic class, specified in percent. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of * the default SCHQ. */ - uint32_t min_bw_tc6; + uint32_t tc_bw_reservation6; /* - * Bandwidth reservation for the traffic class, specified in Mbps. + * Bandwidth reservation for the traffic class, specified in percent. * A value of zero signifies that traffic belonging to this class * shares the bandwidth reservation for the same traffic class of * the default SCHQ. */ - uint32_t min_bw_tc7; + uint32_t tc_bw_reservation7; /* * Indicates the max bandwidth for all enabled traffic classes in * this SCHQ, specified in Mbps. @@ -39288,9 +43985,9 @@ typedef struct hwrm_ring_schq_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -39351,9 +44048,9 @@ typedef struct hwrm_ring_schq_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -39879,7 +44576,7 @@ typedef struct hwrm_cfa_l2_filter_free_output { **************************/ -/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ +/* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ typedef struct hwrm_cfa_l2_filter_cfg_input { /* The HWRM command request type. */ @@ -39921,7 +44618,7 @@ typedef struct hwrm_cfa_l2_filter_cfg_input { #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) /* rx path */ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX /* * Setting of this flag indicates drop action. If this flag is not * set, then it should be considered accept action. @@ -39934,12 +44631,25 @@ typedef struct hwrm_cfa_l2_filter_cfg_input { #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0xc) #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2 /* To support old drivers */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 2) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 2) /* Only L2 traffic */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 2) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 2) /* Roce & L2 traffic */ #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 2) #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE + /* + * Enumeration denoting how the L2 Context TCAM remap operation is + * updated. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_MASK UINT32_C(0x30) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_SFT 4 + /* No change to remap opcode */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_NO_UPDATE (UINT32_C(0x0) << 4) + /* Bypass CFA Lookup */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_BYPASS_LKUP (UINT32_C(0x1) << 4) + /* Enable CFA Lookup */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_ENABLE_LKUP (UINT32_C(0x2) << 4) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_ENABLE_LKUP uint32_t enables; /* * This bit must be '1' for the dst_id field to be @@ -39951,6 +44661,16 @@ typedef struct hwrm_cfa_l2_filter_cfg_input { * configured. */ #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) + /* + * This bit must be '1' for the prof_func field to be configured in + * the remap entry. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_PROF_FUNC UINT32_C(0x4) + /* + * This bit must be '1' for the l2_context_id field to be configured + * in the remap entry. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_L2_CONTEXT_ID UINT32_C(0x8) /* * This value identifies a set of CFA data structures used for an L2 * context. @@ -39968,6 +44688,18 @@ typedef struct hwrm_cfa_l2_filter_cfg_input { * mirrored. */ uint32_t new_mirror_vnic_id; + /* + * Profile function value to be programmed into the L2 context entry's + * remap. This will be used by the host application to program the CFA + * Profile TCAM entry for further classification. + */ + uint32_t prof_func; + /* + * L2 context ID value to be programmed into the L2 context entry's + * remap. This will be used by the host application to program the CFA + * Lookup entry for further classification. + */ + uint32_t l2_context_id; } hwrm_cfa_l2_filter_cfg_input_t, *phwrm_cfa_l2_filter_cfg_input_t; /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ @@ -41363,13 +46095,16 @@ typedef struct hwrm_cfa_ntuple_filter_alloc_input { /* * Setting of this flag indicates that the dst_id field contains RFS * ring table index. If this is not set it indicates dst_id is VNIC - * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx - * can’t be set at the same time. + * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx + * can't be set at the same time. Updated drivers should pass ring + * idx in the rfs_ring_tbl_idx field if the firmware indicates + * support for the new field in the HWRM_CFA_ADV_FLOW_MGMT_QCAPS + * response. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x20) /* * Setting of this flag indicates that when the ntuple filter is - * created, the L2 context should not be used in the filter. This + * created, the L2 context should not be used in the filter. This * allows packet from different L2 contexts to match and be directed * to the same destination. */ @@ -41460,17 +46195,17 @@ typedef struct hwrm_cfa_ntuple_filter_alloc_input { * configured. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x10000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ + /* This flag is deprecated. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x20000) /* * This bit must be '1' for the dst_macaddr field to be * configured. */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x40000) - /* This flag is deprecated. */ + /* + * This bit must be '1' for the rfs_ring_tbl_idx field to + * be configured. + */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX UINT32_C(0x80000) /* * This value identifies a set of CFA data structures used for an L2 @@ -41499,7 +46234,7 @@ typedef struct hwrm_cfa_ntuple_filter_alloc_input { #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * The value of protocol filed in IP header. + * The value of protocol field in IP header. * Applies to UDP and TCP traffic. * 6 - TCP * 17 - UDP @@ -41529,10 +46264,12 @@ typedef struct hwrm_cfa_ntuple_filter_alloc_input { */ uint16_t dst_id; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * If set, this value shall represent the ring table + * index for receive flow steering. Note that this offset + * was formerly used for the mirror_vnic_id field, which + * is no longer supported. */ - uint16_t mirror_vnic_id; + uint16_t rfs_ring_tbl_idx; /* * This value indicates the tunnel type for this filter. * If this field is not specified, then the filter shall @@ -41842,13 +46579,13 @@ typedef struct hwrm_cfa_ntuple_filter_cfg_input { /* * Setting of this flag indicates that the new_dst_id field contains * RFS ring table index. If this is not set it indicates new_dst_id - * is VNIC or VPORT or function ID. Note dest_fid and - * dest_rfs_ring_idx can’t be set at the same time. + * is VNIC or VPORT or function ID. Note dest_fid and + * dest_rfs_ring_idx can't be set at the same time. */ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x2) /* * Setting of this flag indicates that when the ntuple filter is - * created, the L2 context should not be used in the filter. This + * created, the L2 context should not be used in the filter. This * allows packet from different L2 contexts to match and be directed * to the same destination. */ @@ -42173,7 +46910,7 @@ typedef struct hwrm_cfa_em_flow_alloc_input { #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * The value of protocol filed in IP header. + * The value of protocol field in IP header. * Applies to UDP and TCP traffic. * 6 - TCP * 17 - UDP @@ -43553,7 +48290,7 @@ typedef struct hwrm_cfa_decap_filter_alloc_input { #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * The value of protocol filed in IP header. + * The value of protocol field in IP header. * Applies to UDP and TCP traffic. * 6 - TCP * 17 - UDP @@ -44754,7 +49491,7 @@ typedef struct hwrm_cfa_flow_stats_output { * If a flow has been hit, the bit representing the flow will be 1. * Likewise, if a flow has not, the bit representing the flow * will be 0. Mapping will match flow numbers where bitX is for flowX - * (ex: bit 0 is flow0). This only applies for NIC flows. Upon + * (ex: bit 0 is flow0). This only applies for NIC flows. Upon * reading of the flow, the bit will be cleared for the flow and only * set again when traffic is received by the flow. */ @@ -46959,7 +51696,7 @@ typedef struct hwrm_cfa_eem_qcaps_output { /* * When set to 1, indicates the FW supports the Centralized * Memory Model. The concept designates one entity for the - * memory allocation while all others ‘subscribe’ to it. + * memory allocation while all others 'subscribe' to it. */ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x4) /* @@ -47495,10 +52232,16 @@ typedef struct hwrm_cfa_adv_flow_mgnt_qcaps_output { #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED UINT32_C(0x80000) /* * If set to 1, firmware is capable of supporting these additional - * ip_protoccols: ICMP, ICMPV6, RSVD for ntuple rules. By default, + * ip_protocols: ICMP, ICMPV6, RSVD for ntuple rules. By default, * this flag should be 0 for older version of firmware. */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED UINT32_C(0x100000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx (new offset) in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates ring tbl idx should be passed using dst_id. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED UINT32_C(0x200000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -47634,7 +52377,7 @@ typedef struct hwrm_cfa_lag_group_member_rgtr_input { /* * Transmit based on packet header ntuple hash. Packet with only * layer 2 headers will hash using the destination MAC, source MAC - * and Ethertype fields. Packets with layer 3 (IP) headers will + * and Ethertype fields. Packets with layer 3 (IP) headers will * hash using the destination MAC, source MAC, IP protocol/next * header, source IP address and destination IP address. Packets * with layer 4 (TCP/UDP) headers will hash using the destination @@ -47749,7 +52492,7 @@ typedef struct hwrm_cfa_lag_group_member_unrgtr_output { *****************************/ -/* hwrm_cfa_tls_filter_alloc_input (size:704b/88B) */ +/* hwrm_cfa_tls_filter_alloc_input (size:768b/96B) */ typedef struct hwrm_cfa_tls_filter_alloc_input { /* The HWRM command request type. */ @@ -47786,47 +52529,47 @@ typedef struct hwrm_cfa_tls_filter_alloc_input { * This bit must be '1' for the l2_filter_id field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) /* * This bit must be '1' for the ethertype field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2) /* * This bit must be '1' for the ipaddr_type field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x4) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x4) /* * This bit must be '1' for the src_ipaddr field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x8) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x8) /* * This bit must be '1' for the dst_ipaddr field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x10) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x10) /* * This bit must be '1' for the ip_protocol field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x20) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x20) /* * This bit must be '1' for the src_port field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x40) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x40) /* * This bit must be '1' for the dst_port field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x80) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x80) /* * This bit must be '1' for the kid field to be * configured. */ - #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID UINT32_C(0x100) + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID UINT32_C(0x100) /* * This bit must be '1' for the dst_id field to be * configured. @@ -47837,6 +52580,11 @@ typedef struct hwrm_cfa_tls_filter_alloc_input { * configured. */ #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400) + /* + * This bit must be '1' for the quic_dst_connect_id field to be + * configured. + */ + #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_QUIC_DST_CONNECT_ID UINT32_C(0x800) /* * This value identifies a set of CFA data structures used for an L2 * context. @@ -47860,7 +52608,7 @@ typedef struct hwrm_cfa_tls_filter_alloc_input { #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * The value of protocol filed in IP header. + * The value of protocol field in IP header. * Applies to UDP and TCP traffic. * 6 - TCP * 17 - UDP @@ -47907,10 +52655,12 @@ typedef struct hwrm_cfa_tls_filter_alloc_input { */ uint16_t dst_port; /* - * The Key Context Identifier (KID) for use with KTLS. + * The Key Context Identifier (KID) for use with KTLS or QUIC. * KID is limited to 20-bits. */ uint32_t kid; + /* The Destination Connection ID of QUIC. */ + uint64_t quic_dst_connect_id; } hwrm_cfa_tls_filter_alloc_input_t, *phwrm_cfa_tls_filter_alloc_input_t; /* hwrm_cfa_tls_filter_alloc_output (size:192b/24B) */ @@ -48032,6 +52782,93 @@ typedef struct hwrm_cfa_tls_filter_free_output { uint8_t valid; } hwrm_cfa_tls_filter_free_output_t, *phwrm_cfa_tls_filter_free_output_t; +/***************************** + * hwrm_cfa_release_afm_func * + *****************************/ + + +/* hwrm_cfa_release_afm_func_input (size:256b/32B) */ + +typedef struct hwrm_cfa_release_afm_func_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Function identifier, may be of type efid, rfid or dfid. */ + uint16_t fid; + /* Representor function identifier. */ + uint16_t rfid; + /* Fid type. */ + uint8_t type; + /* Endpoint fid. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_EFID UINT32_C(0x1) + /* Representor fid. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_RFID UINT32_C(0x2) + /* Redirect fid. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_DFID UINT32_C(0x3) + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_LAST HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_DFID + uint8_t unused_0[3]; + /* + * Flags used to control AFMs actions when releasing the function. + * Only used when type is dfid. + */ + uint32_t flags; + /* Remove broadcast. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_BC_REM UINT32_C(0x1) + /* Remove multicast. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_MC_REM UINT32_C(0x2) + /* Remove promiscuous. */ + #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_PROMISC_REM UINT32_C(0x4) + uint32_t unused_1; +} hwrm_cfa_release_afm_func_input_t, *phwrm_cfa_release_afm_func_input_t; + +/* hwrm_cfa_release_afm_func_output (size:128b/16B) */ + +typedef struct hwrm_cfa_release_afm_func_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_cfa_release_afm_func_output_t, *phwrm_cfa_release_afm_func_output_t; + /*********** * hwrm_tf * ***********/ @@ -48103,7 +52940,7 @@ typedef struct hwrm_tf_output { * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been - * completely written. When writing a command completion or + * completely written. When writing a command completion or * response to an internal processor, the order of writes has * to be such that this field is written last. */ @@ -48278,91 +53115,6 @@ typedef struct hwrm_tf_session_open_output { uint8_t valid; } hwrm_tf_session_open_output_t, *phwrm_tf_session_open_output_t; -/************************** - * hwrm_tf_session_attach * - **************************/ - - -/* hwrm_tf_session_attach_input (size:704b/88B) */ - -typedef struct hwrm_tf_session_attach_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * Unique session identifier for the session that the attach - * request want to attach to. This value originates from the - * shared session memory that the attach request opened by - * way of the 'attach name' that was passed in to the core - * attach API. - * The fw_session_id of the attach session includes PCIe bus - * info to distinguish the PF and session info to identify - * the associated TruFlow session. - */ - uint32_t attach_fw_session_id; - /* unused. */ - uint32_t unused0; - /* Name of the session it self. */ - uint8_t session_name[64]; -} hwrm_tf_session_attach_input_t, *phwrm_tf_session_attach_input_t; - -/* hwrm_tf_session_attach_output (size:128b/16B) */ - -typedef struct hwrm_tf_session_attach_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * Unique session identifier for the session created by the - * firmware. It includes PCIe bus info to distinguish the PF - * and session info to identify the associated TruFlow - * session. This fw_session_id is unique to the attach - * request. - */ - uint32_t fw_session_id; - /* unused. */ - uint8_t unused0[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. - */ - uint8_t valid; -} hwrm_tf_session_attach_output_t, *phwrm_tf_session_attach_output_t; - /**************************** * hwrm_tf_session_register * ****************************/ @@ -48903,91 +53655,6 @@ typedef struct hwrm_tf_session_resc_alloc_output { uint8_t valid; } hwrm_tf_session_resc_alloc_output_t, *phwrm_tf_session_resc_alloc_output_t; -/***************************** - * hwrm_tf_session_resc_free * - *****************************/ - - -/* hwrm_tf_session_resc_free_input (size:256b/32B) */ - -typedef struct hwrm_tf_session_resc_free_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX - /* - * Defines the size, in bytes, of the provided free_addr - * buffer. - */ - uint16_t free_size; - /* - * This is the DMA address for the free input data array - * buffer. Array is of tf_rm_resc_entry type. Size of the - * buffer is provided by the 'free_size' field of this - * message. - */ - uint64_t free_addr; -} hwrm_tf_session_resc_free_input_t, *phwrm_tf_session_resc_free_input_t; - -/* hwrm_tf_session_resc_free_output (size:128b/16B) */ - -typedef struct hwrm_tf_session_resc_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field is - * written last. - */ - uint8_t valid; -} hwrm_tf_session_resc_free_output_t, *phwrm_tf_session_resc_free_output_t; - /****************************** * hwrm_tf_session_resc_flush * ******************************/ @@ -49042,7 +53709,7 @@ typedef struct hwrm_tf_session_resc_flush_input { uint16_t flush_size; /* * This is the DMA address for the flush input data array - * buffer. Array of tf_rm_resc_entry type. Size of the + * buffer. Array of tf_rm_resc_entry type. Size of the * buffer is provided by the 'flush_size' field in this * message. */ @@ -49197,6 +53864,103 @@ typedef struct tf_rm_resc_entry { uint16_t stride; } tf_rm_resc_entry_t, *ptf_rm_resc_entry_t; +/************************** + * hwrm_tf_tbl_type_alloc * + **************************/ + + +/* hwrm_tf_tbl_type_alloc_input (size:192b/24B) */ + +typedef struct hwrm_tf_tbl_type_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_TX + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_LAST HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* + * This field is blktype specific. For any of the UPAR types it is + * set to a non-zero value in case of a re-alloc, specifies a + * tunnel-type of dynamic UPAR tunnel. + */ + uint8_t type; +} hwrm_tf_tbl_type_alloc_input_t, *phwrm_tf_tbl_type_alloc_input_t; + +/* hwrm_tf_tbl_type_alloc_output (size:128b/16B) */ + +typedef struct hwrm_tf_tbl_type_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* + * Table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx_tbl_id; + /* unused */ + uint8_t unused0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tf_tbl_type_alloc_output_t, *phwrm_tf_tbl_type_alloc_output_t; + /************************ * hwrm_tf_tbl_type_get * ************************/ @@ -49249,8 +54013,19 @@ typedef struct hwrm_tf_tbl_type_get_input { * the table entry on read. */ #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2) + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_LAST HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE /* unused. */ - uint8_t unused0[2]; + uint8_t unused0; /* * Type of the resource, defined globally in the * hwrm_tf_resc_type enum. @@ -49341,8 +54116,19 @@ typedef struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX /* Indicate table data is being sent via DMA. */ #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_LAST HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE /* unused. */ - uint8_t unused0[2]; + uint8_t unused0; /* * Type of the resource, defined globally in the * hwrm_tf_resc_type enum. @@ -49382,121 +54168,14 @@ typedef struct hwrm_tf_tbl_type_set_output { uint8_t valid; } hwrm_tf_tbl_type_set_output_t, *phwrm_tf_tbl_type_set_output_t; -/************************** - * hwrm_tf_ctxt_mem_alloc * - **************************/ - - -/* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */ - -typedef struct hwrm_tf_ctxt_mem_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Size in KB of memory to be allocated. */ - uint32_t mem_size; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; -} hwrm_tf_ctxt_mem_alloc_input_t, *phwrm_tf_ctxt_mem_alloc_input_t; - -/* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */ - -typedef struct hwrm_tf_ctxt_mem_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; - /* Size of memory allocated. */ - uint32_t mem_size; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* - * PBL pointer points to PDE table with each entry pointing - * to PTE tables. - */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 128KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5) - /* 256KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 512KB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7) - /* 1MB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 8MB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb) - /* 1GB page size. */ - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G - /* unused. */ - uint8_t unused0; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tf_ctxt_mem_alloc_output_t, *phwrm_tf_ctxt_mem_alloc_output_t; - /************************* - * hwrm_tf_ctxt_mem_free * + * hwrm_tf_tbl_type_free * *************************/ -/* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */ +/* hwrm_tf_tbl_type_free_input (size:256b/32B) */ -typedef struct hwrm_tf_ctxt_mem_free_input { +typedef struct hwrm_tf_tbl_type_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -49527,699 +54206,40 @@ typedef struct hwrm_tf_ctxt_mem_free_input { uint64_t resp_addr; /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint32_t fw_session_id; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* - * PBL pointer points to PDE table with each entry pointing - * to PTE tables. - */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 128KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5) - /* 256KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 512KB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7) - /* 1MB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 8MB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb) - /* 1GB page size. */ - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G - /* unused. */ - uint8_t unused0[2]; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; - /* Size of memory allocated. */ - uint32_t mem_size; - /* unused. */ - uint8_t unused1[4]; -} hwrm_tf_ctxt_mem_free_input_t, *phwrm_tf_ctxt_mem_free_input_t; - -/* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */ - -typedef struct hwrm_tf_ctxt_mem_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tf_ctxt_mem_free_output_t, *phwrm_tf_ctxt_mem_free_output_t; - -/************************* - * hwrm_tf_ctxt_mem_rgtr * - *************************/ - - -/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */ - -typedef struct hwrm_tf_ctxt_mem_rgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Control flags. */ - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* - * PBL pointer points to PDE table with each entry pointing - * to PTE tables. - */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 128KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5) - /* 256KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 512KB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7) - /* 1MB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 8MB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb) - /* 1GB page size. */ - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; -} hwrm_tf_ctxt_mem_rgtr_input_t, *phwrm_tf_ctxt_mem_rgtr_input_t; - -/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */ - -typedef struct hwrm_tf_ctxt_mem_rgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* - * Id/Handle to the recently register context memory. This - * handle is passed to the TF session. - */ - uint16_t ctx_id; - /* unused. */ - uint8_t unused0[5]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tf_ctxt_mem_rgtr_output_t, *phwrm_tf_ctxt_mem_rgtr_output_t; - -/*************************** - * hwrm_tf_ctxt_mem_unrgtr * - ***************************/ - - -/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */ - -typedef struct hwrm_tf_ctxt_mem_unrgtr_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* - * Id/Handle to the recently register context memory. This - * handle is passed to the TF session. - */ - uint16_t ctx_id; - /* unused. */ - uint8_t unused0[2]; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; -} hwrm_tf_ctxt_mem_unrgtr_input_t, *phwrm_tf_ctxt_mem_unrgtr_input_t; - -/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */ - -typedef struct hwrm_tf_ctxt_mem_unrgtr_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tf_ctxt_mem_unrgtr_output_t, *phwrm_tf_ctxt_mem_unrgtr_output_t; - -/************************ - * hwrm_tf_ext_em_qcaps * - ************************/ - - -/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */ - -typedef struct hwrm_tf_ext_em_qcaps_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x2) - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; -} hwrm_tf_ext_em_qcaps_input_t, *phwrm_tf_ext_em_qcaps_input_t; - -/* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */ - -typedef struct hwrm_tf_ext_em_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint32_t flags; - /* - * When set to 1, indicates the FW supports the Centralized - * Memory Model. The concept designates one entity for the - * memory allocation while all others ‘subscribe’ to it. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x1) - /* - * When set to 1, indicates the FW supports the Detached - * Centralized Memory Model. The memory is allocated and managed - * as a separate entity. All PFs and VFs will be granted direct - * or semi-direct access to the allocated memory while none of - * which can interfere with the management of the memory. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x2) - /* When set to 1, indicates FW support for host based EEM memory. */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED UINT32_C(0x4) - /* When set to 1, indicates FW support for on-chip based EEM memory. */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED UINT32_C(0x8) - /* unused. */ - uint32_t unused0; - /* Support flags. */ - uint32_t supported; - /* - * If set to 1, then EXT EM KEY0 table is supported using - * crc32 hash. - * If set to 0, EXT EM KEY0 table is not supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE UINT32_C(0x1) - /* - * If set to 1, then EXT EM KEY1 table is supported using - * lookup3 hash. - * If set to 0, EXT EM KEY1 table is not supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE UINT32_C(0x2) - /* - * If set to 1, then EXT EM External Record table is supported. - * If set to 0, EXT EM External Record table is not - * supported. (This table includes action record, EFC - * pointers, encap pointers) - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE UINT32_C(0x4) - /* - * If set to 1, then EXT EM External Flow Counters table is - * supported. - * If set to 0, EXT EM External Flow Counters table is not - * supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE UINT32_C(0x8) - /* - * If set to 1, then FID table used for implicit flow flush - * is supported. - * If set to 0, then FID table used for implicit flow flush - * is not supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE UINT32_C(0x10) - /* - * If set to 1, then table scopes are supported. - * If set to 0, then table scopes are not supported. - */ - #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES UINT32_C(0x20) - /* - * The maximum number of entries supported by EXT EM. When - * configuring the host memory the number of numbers of - * entries that can supported are - - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, - * 128M entries. - * Any value that are not these values, the FW will round - * down to the closest support number of entries. - */ - uint32_t max_entries_supported; - /* - * The entry size in bytes of each entry in the EXT EM - * KEY0/KEY1 tables. - */ - uint16_t key_entry_size; - /* - * The entry size in bytes of each entry in the EXT EM RECORD - * tables. - */ - uint16_t record_entry_size; - /* The entry size in bytes of each entry in the EXT EM EFC tables. */ - uint16_t efc_entry_size; - /* The FID size in bytes of each entry in the EXT EM FID tables. */ - uint16_t fid_entry_size; - /* Maximum number of ctxt mem allocations allowed. */ - uint32_t max_ctxt_mem_allocs; - /* - * Maximum number of static buckets that can be assigned to lookup - * table scopes. - */ - uint32_t max_static_buckets; - /* unused. */ - uint8_t unused1[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tf_ext_em_qcaps_output_t, *phwrm_tf_ext_em_qcaps_output_t; - -/********************* - * hwrm_tf_ext_em_op * - *********************/ - - -/* hwrm_tf_ext_em_op_input (size:256b/32B) */ - -typedef struct hwrm_tf_ext_em_op_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; /* Control flags. */ uint16_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX - /* unused. */ - uint16_t unused0; - /* The number of EXT EM key table entries to be configured. */ - uint16_t op; - /* This value is reserved and should not be used. */ - #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0) - /* - * To properly stop EXT EM and ensure there are no DMA's, - * the caller must disable EXT EM for the given PF, using - * this call. This will safely disable EXT EM and ensure - * that all DMA'ed to the keys/records/efc have been - * completed. - */ - #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1) - /* - * Once the EXT EM host memory has been configured, EXT EM - * options have been configured. Then the caller should - * enable EXT EM for the given PF. Note once this call has - * been made, then the EXT EM mechanism will be active and - * DMA's will occur as packets are processed. - */ - #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2) - /* - * Clear EXT EM settings for the given PF so that the - * register values are reset back to their initial state. - */ - #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3) - #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP - /* unused. */ - uint16_t unused1; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* unused. */ - uint32_t unused2; -} hwrm_tf_ext_em_op_input_t, *phwrm_tf_ext_em_op_input_t; - -/* hwrm_tf_ext_em_op_output (size:128b/16B) */ - -typedef struct hwrm_tf_ext_em_op_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tf_ext_em_op_output_t, *phwrm_tf_ext_em_op_output_t; - -/********************** - * hwrm_tf_ext_em_cfg * - **********************/ - - -/* hwrm_tf_ext_em_cfg_input (size:512b/64B) */ - -typedef struct hwrm_tf_ext_em_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x2) - /* When set to 1, secondary, 0 means primary. */ - #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF UINT32_C(0x4) - /* - * Group_id which used by Firmware to identify memory pools belonging - * to certain group. - */ - uint16_t group_id; - /* - * Dynamically reconfigure EEM pending cache every 1/10th of second. - * If set to 0 it will disable the EEM HW flush of the pending cache. - */ - uint8_t flush_interval; - /* unused. */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_LAST HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_TX + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_LAST HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* Unused */ uint8_t unused0; /* - * Configured EXT EM with the given number of entries. All - * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the - * same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current - * maximum value is 128M. + * Table entry to be freed by the firmware using the parameters + * above. */ - uint32_t num_entries; - uint32_t enables; - /* - * This bit must be '1' for the group_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID UINT32_C(0x1) - /* - * This bit must be '1' for the flush_interval field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL UINT32_C(0x2) - /* - * This bit must be '1' for the num_entries field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES UINT32_C(0x4) - /* - * This bit must be '1' for the key0_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID UINT32_C(0x8) - /* - * This bit must be '1' for the key1_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID UINT32_C(0x10) - /* - * This bit must be '1' for the record_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID UINT32_C(0x20) - /* - * This bit must be '1' for the efc_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID UINT32_C(0x40) - /* - * This bit must be '1' for the fid_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID UINT32_C(0x80) - /* - * This bit must be '1' for the action_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID UINT32_C(0x100) - /* - * This bit must be '1' for the action_tbl_scope field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE UINT32_C(0x200) - /* - * This bit must be '1' for the lkup_ctx_id field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID UINT32_C(0x400) - /* - * This bit must be '1' for the lkup_tbl_scope field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE UINT32_C(0x800) - /* - * This bit must be '1' for the lkup_static_buckets field to be - * configured. - */ - #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS UINT32_C(0x1000) - /* Configured EXT EM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EXT EM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EXT EM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - /* Context id of action table scope. */ - uint16_t action_ctx_id; - /* Table scope id used for action record entries. */ - uint16_t action_tbl_scope; - /* Context id of lookup table scope. */ - uint16_t lkup_ctx_id; - /* Table scope id used for EM lookup entries. */ - uint16_t lkup_tbl_scope; - /* unused. */ - uint16_t unused1; - /* - * Number of 32B static buckets to be allocated at the beginning - * of table scope. - */ - uint32_t lkup_static_buckets; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* unused. */ - uint32_t unused2; -} hwrm_tf_ext_em_cfg_input_t, *phwrm_tf_ext_em_cfg_input_t; + uint16_t idx_tbl_id; + /* Unused */ + uint8_t unused1[6]; +} hwrm_tf_tbl_type_free_input_t, *phwrm_tf_tbl_type_free_input_t; -/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */ +/* hwrm_tf_tbl_type_free_output (size:128b/16B) */ -typedef struct hwrm_tf_ext_em_cfg_output { +typedef struct hwrm_tf_tbl_type_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -50228,165 +54248,20 @@ typedef struct hwrm_tf_ext_em_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; + /* Response code. */ + uint32_t resp_code; + /* unused */ + uint8_t unused0[3]; /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} hwrm_tf_ext_em_cfg_output_t, *phwrm_tf_ext_em_cfg_output_t; - -/*********************** - * hwrm_tf_ext_em_qcfg * - ***********************/ - - -/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */ - -typedef struct hwrm_tf_ext_em_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; -} hwrm_tf_ext_em_qcfg_input_t, *phwrm_tf_ext_em_qcfg_input_t; - -/* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */ - -typedef struct hwrm_tf_ext_em_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Control flags. */ - uint32_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX - /* When set to 1, all offloaded flows will be sent to EXT EM. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x2) - /* The number of entries the FW has configured for EXT EM. */ - uint32_t num_entries; - /* Configured EXT EM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EXT EM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EXT EM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EXT EM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - /* unused. */ - uint16_t unused0; - uint32_t supported; - /* This bit must be '1' for the group_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID UINT32_C(0x1) - /* This bit must be '1' for the flush_interval field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL UINT32_C(0x2) - /* This bit must be '1' for the num_entries field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES UINT32_C(0x4) - /* This bit must be '1' for the key0_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID UINT32_C(0x8) - /* This bit must be '1' for the key1_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID UINT32_C(0x10) - /* This bit must be '1' for the record_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID UINT32_C(0x20) - /* This bit must be '1' for the efc_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID UINT32_C(0x40) - /* This bit must be '1' for the fid_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID UINT32_C(0x80) - /* This bit must be '1' for the action_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID UINT32_C(0x100) - /* This bit must be '1' for the action_tbl_scope field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE UINT32_C(0x200) - /* This bit must be '1' for the lkup_ctx_id field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID UINT32_C(0x400) - /* This bit must be '1' for the lkup_tbl_scope field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE UINT32_C(0x800) - /* This bit must be '1' for the lkup_static_buckets field is set. */ - #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS UINT32_C(0x1000) - /* - * Group id is used by firmware to identify memory pools belonging - * to certain group. - */ - uint16_t group_id; - /* EEM pending cache flush interval in 1/10th of second. */ - uint8_t flush_interval; - /* unused. */ - uint8_t unused1; - /* Context id of action table scope. */ - uint16_t action_ctx_id; - /* Table scope id used for action record entries. */ - uint16_t action_tbl_scope; - /* Context id of lookup table scope. */ - uint16_t lkup_ctx_id; - /* Table scope id used for EM lookup entries. */ - uint16_t lkup_tbl_scope; - /* - * Number of 32B static buckets to be allocated at the beginning - * of table scope. - */ - uint32_t lkup_static_buckets; - /* unused. */ - uint8_t unused2[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tf_ext_em_qcfg_output_t, *phwrm_tf_ext_em_qcfg_output_t; +} hwrm_tf_tbl_type_free_output_t, *phwrm_tf_tbl_type_free_output_t; /********************* * hwrm_tf_em_insert * @@ -50467,7 +54342,16 @@ typedef struct hwrm_tf_em_insert_output { /* Number of word entries consumed by the key. */ uint8_t num_of_entries; /* unused. */ - uint32_t unused0; + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; } hwrm_tf_em_insert_output_t, *phwrm_tf_em_insert_output_t; /************************** @@ -50517,6 +54401,8 @@ typedef struct hwrm_tf_em_hash_insert_input { /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX + /* Indicates table data is being sent via DMA. */ + #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DMA UINT32_C(0x2) /* Number of bits in the EM record. */ uint16_t em_record_size_bits; /* CRC32 hash of key. */ @@ -50549,7 +54435,16 @@ typedef struct hwrm_tf_em_hash_insert_output { /* Number of word entries consumed by the key. */ uint8_t num_of_entries; /* unused. */ - uint32_t unused0; + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; } hwrm_tf_em_hash_insert_output_t, *phwrm_tf_em_hash_insert_output_t; /********************* @@ -50625,7 +54520,16 @@ typedef struct hwrm_tf_em_delete_output { /* Original stack allocation index. */ uint16_t em_index; /* unused. */ - uint16_t unused0[3]; + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; } hwrm_tf_em_delete_output_t, *phwrm_tf_em_delete_output_t; /******************* @@ -50699,7 +54603,16 @@ typedef struct hwrm_tf_em_move_output { /* Index of old entry. */ uint16_t em_index; /* unused. */ - uint16_t unused0[3]; + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; } hwrm_tf_em_move_output_t, *phwrm_tf_em_move_output_t; /******************** @@ -50798,7 +54711,7 @@ typedef struct hwrm_tf_tcam_set_output { * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been - * completely written. When writing a command completion or + * completely written. When writing a command completion or * response to an internal processor, the order of writes has * to be such that this field is written last. */ @@ -50895,7 +54808,7 @@ typedef struct hwrm_tf_tcam_get_output { * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been - * completely written. When writing a command completion or + * completely written. When writing a command completion or * response to an internal processor, the order of writes has * to be such that this field is written last. */ @@ -50979,7 +54892,7 @@ typedef struct hwrm_tf_tcam_move_output { * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been - * completely written. When writing a command completion or + * completely written. When writing a command completion or * response to an internal processor, the order of writes has * to be such that this field is written last. */ @@ -51063,7 +54976,7 @@ typedef struct hwrm_tf_tcam_free_output { * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been - * completely written. When writing a command completion or + * completely written. When writing a command completion or * response to an internal processor, the order of writes has * to be such that this field is written last. */ @@ -51117,6 +55030,8 @@ typedef struct hwrm_tf_global_cfg_set_input { /* If this bit is set to 1, then it indicates tx flow. */ #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX + /* Indicate device data is being sent via DMA. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DMA UINT32_C(0x2) /* Global Cfg type */ uint32_t type; /* Offset of the type */ @@ -51148,7 +55063,7 @@ typedef struct hwrm_tf_global_cfg_set_output { * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been - * completely written. When writing a command completion or + * completely written. When writing a command completion or * response to an internal processor, the order of writes has * to be such that this field is written last. */ @@ -51212,7 +55127,7 @@ typedef struct hwrm_tf_global_cfg_get_input { uint8_t unused0[6]; } hwrm_tf_global_cfg_get_input_t, *phwrm_tf_global_cfg_get_input_t; -/* hwrm_tf_global_cfg_get_output (size:256b/32B) */ +/* hwrm_tf_global_cfg_get_output (size:2240b/280B) */ typedef struct hwrm_tf_global_cfg_get_output { /* The specific error status for the command. */ @@ -51228,7 +55143,18 @@ typedef struct hwrm_tf_global_cfg_get_output { /* unused. */ uint8_t unused0[6]; /* Data to set */ - uint8_t data[16]; + uint8_t data[256]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; } hwrm_tf_global_cfg_get_output_t, *phwrm_tf_global_cfg_get_output_t; /********************** @@ -51660,6 +55586,208 @@ typedef struct hwrm_tf_session_hotup_state_get_output { uint8_t valid; } hwrm_tf_session_hotup_state_get_output_t, *phwrm_tf_session_hotup_state_get_output_t; +/************************** + * hwrm_tf_resc_usage_set * + **************************/ + + +/* hwrm_tf_resc_usage_set_input (size:1024b/128B) */ + +typedef struct hwrm_tf_resc_usage_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_LAST HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX + /* Indicate table data is being sent via DMA. */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* Types of the resource to set their usage state. */ + uint16_t types; + /* WC TCAM Pool */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_WC_TCAM UINT32_C(0x1) + /* EM Internal Memory Pool */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_EM UINT32_C(0x2) + /* Meter Instance */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_METER UINT32_C(0x4) + /* Counter Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_COUNTER UINT32_C(0x8) + /* Action Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACTION UINT32_C(0x10) + /* ACT MODIFY/ENCAP Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACT_MOD_ENCAP UINT32_C(0x20) + /* Source Property SMAC Record Table */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_SP_SMAC UINT32_C(0x40) + /* All Resource Types */ + #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ALL UINT32_C(0x80) + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[96]; +} hwrm_tf_resc_usage_set_input_t, *phwrm_tf_resc_usage_set_input_t; + +/* hwrm_tf_resc_usage_set_output (size:128b/16B) */ + +typedef struct hwrm_tf_resc_usage_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tf_resc_usage_set_output_t, *phwrm_tf_resc_usage_set_output_t; + +/**************************** + * hwrm_tf_resc_usage_query * + ****************************/ + + +/* hwrm_tf_resc_usage_query_input (size:256b/32B) */ + +typedef struct hwrm_tf_resc_usage_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_LAST HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* Types of the resource to retrieve their usage state. */ + uint16_t types; + /* WC TCAM Pool */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_WC_TCAM UINT32_C(0x1) + /* EM Internal Memory Pool */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_EM UINT32_C(0x2) + /* Meter Instance */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_METER UINT32_C(0x4) + /* Counter Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_COUNTER UINT32_C(0x8) + /* Action Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACTION UINT32_C(0x10) + /* ACT MODIFY/ENCAP Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACT_MOD_ENCAP UINT32_C(0x20) + /* Source Property SMAC Record Table */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_SP_SMAC UINT32_C(0x40) + /* All Resource Types */ + #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ALL UINT32_C(0x80) + /* unused */ + uint8_t unused1[6]; +} hwrm_tf_resc_usage_query_input_t, *phwrm_tf_resc_usage_query_input_t; + +/* hwrm_tf_resc_usage_query_output (size:960b/120B) */ + +typedef struct hwrm_tf_resc_usage_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[96]; + /* unused */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tf_resc_usage_query_output_t, *phwrm_tf_resc_usage_query_output_t; + /**************************** * hwrm_tfc_tbl_scope_qcaps * ****************************/ @@ -51727,7 +55855,7 @@ typedef struct hwrm_tfc_tbl_scope_qcaps_output { uint8_t tbl_scope_capable; /* * log2 of the number of lookup static buckets that a table scope can - * support. This field is only valid if tbl_scope_capable is not zero. + * support. This field is only valid if tbl_scope_capable is not zero. */ uint8_t max_lkup_static_buckets_exp; /* unused. */ @@ -51757,7 +55885,7 @@ typedef struct hwrm_tfc_tbl_scope_qcaps_output { * a fid_cnt of 0 that also means that the table scope ID has * been freed. */ -/* hwrm_tfc_tbl_scope_id_alloc_input (size:192b/24B) */ +/* hwrm_tfc_tbl_scope_id_alloc_input (size:256b/32B) */ typedef struct hwrm_tfc_tbl_scope_id_alloc_input { /* The HWRM command request type. */ @@ -51788,26 +55916,37 @@ typedef struct hwrm_tfc_tbl_scope_id_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* The maximum number of pools for this table scope. */ uint16_t max_pools; /* Non-zero if this table scope is shared. */ uint8_t shared; /* * The size of the lookup pools per direction expressed as - * log2(max_records/max_pools). That is, size=2^exp. + * log2(max_records/max_pools). That is, size=2^exp. * * Array is indexed by enum cfa_dir. */ uint8_t lkup_pool_sz_exp[2]; /* * The size of the action pools per direction expressed as - * log2(max_records/max_pools). That is, size=2^exp. + * log2(max_records/max_pools). That is, size=2^exp. * * Array is indexed by enum cfa_dir. */ uint8_t act_pool_sz_exp[2]; + /* Application type. 0 (AFM), 1 (TF) */ + uint8_t app_type; /* unused. */ - uint8_t unused0; + uint8_t unused0[6]; } hwrm_tfc_tbl_scope_id_alloc_input_t, *phwrm_tfc_tbl_scope_id_alloc_input_t; /* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */ @@ -51891,7 +56030,7 @@ typedef struct hwrm_tfc_tbl_scope_config_input { /* * The number of minimum sized lkup records per direction. * In this usage, records are the minimum lookup memory - * allocation unit in a table scope. This value is the total + * allocation unit in a table scope. This value is the total * memory required for buckets and entries. * * Array is indexed by enum cfa_dir. @@ -52056,10 +56195,19 @@ typedef struct hwrm_tfc_tbl_scope_fid_add_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* The table scope ID. */ uint8_t tsid; /* unused. */ - uint8_t unused0[7]; + uint8_t unused0[5]; } hwrm_tfc_tbl_scope_fid_add_input_t, *phwrm_tfc_tbl_scope_fid_add_input_t; /* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */ @@ -52125,10 +56273,19 @@ typedef struct hwrm_tfc_tbl_scope_fid_rem_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* The table scope ID. */ uint8_t tsid; /* unused. */ - uint8_t unused0[7]; + uint8_t unused0[5]; } hwrm_tfc_tbl_scope_fid_rem_input_t, *phwrm_tfc_tbl_scope_fid_rem_input_t; /* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */ @@ -52157,176 +56314,6 @@ typedef struct hwrm_tfc_tbl_scope_fid_rem_output { uint8_t valid; } hwrm_tfc_tbl_scope_fid_rem_output_t, *phwrm_tfc_tbl_scope_fid_rem_output_t; -/********************************* - * hwrm_tfc_tbl_scope_pool_alloc * - *********************************/ - - -/* hwrm_tfc_tbl_scope_pool_alloc_input (size:192b/24B) */ - -typedef struct hwrm_tfc_tbl_scope_pool_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Table Scope ID */ - uint8_t tsid; - /* Control flags. Direction and type. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX - /* Indicates the table type. */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE UINT32_C(0x2) - /* Lookup table */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LOOKUP (UINT32_C(0x0) << 1) - /* Action table */ - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION (UINT32_C(0x1) << 1) - #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LAST HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION - /* Unused */ - uint8_t unused[6]; -} hwrm_tfc_tbl_scope_pool_alloc_input_t, *phwrm_tfc_tbl_scope_pool_alloc_input_t; - -/* hwrm_tfc_tbl_scope_pool_alloc_output (size:128b/16B) */ - -typedef struct hwrm_tfc_tbl_scope_pool_alloc_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* Pool ID */ - uint16_t pool_id; - /* Pool size exponent. An exponent of 0 indicates a failure. */ - uint8_t pool_sz_exp; - /* unused. */ - uint8_t unused1[4]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tfc_tbl_scope_pool_alloc_output_t, *phwrm_tfc_tbl_scope_pool_alloc_output_t; - -/******************************** - * hwrm_tfc_tbl_scope_pool_free * - ********************************/ - - -/* hwrm_tfc_tbl_scope_pool_free_input (size:192b/24B) */ - -typedef struct hwrm_tfc_tbl_scope_pool_free_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Table Scope ID */ - uint8_t tsid; - /* Control flags. Direction and type. */ - uint8_t flags; - /* Indicates the flow direction. */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX - /* Indicates the table type. */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE UINT32_C(0x2) - /* Lookup table */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LOOKUP (UINT32_C(0x0) << 1) - /* Action table */ - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION (UINT32_C(0x1) << 1) - #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LAST HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION - /* Pool ID */ - uint16_t pool_id; - /* Unused */ - uint8_t unused[4]; -} hwrm_tfc_tbl_scope_pool_free_input_t, *phwrm_tfc_tbl_scope_pool_free_input_t; - -/* hwrm_tfc_tbl_scope_pool_free_output (size:128b/16B) */ - -typedef struct hwrm_tfc_tbl_scope_pool_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* unused. */ - uint8_t unused1[7]; - /* - * This field is used in Output records to indicate that the - * output is completely written to RAM. This field should be - * read as '1' to indicate that the output has been - * completely written. When writing a command completion or - * response to an internal processor, the order of writes has - * to be such that this field is written last. - */ - uint8_t valid; -} hwrm_tfc_tbl_scope_pool_free_output_t, *phwrm_tfc_tbl_scope_pool_free_output_t; - /***************************** * hwrm_tfc_session_id_alloc * *****************************/ @@ -52335,11 +56322,11 @@ typedef struct hwrm_tfc_tbl_scope_pool_free_output { /* * Allocate a TFC session. Requests the firmware to allocate a TFC * session identifier and associate a forwarding function with the - * session. Though there's not an explicit matching free for a session + * session. Though there's not an explicit matching free for a session * id alloc, dis-associating the last fid from a session id (fid_cnt goes * to 0), will result in this session id being freed automatically. */ -/* hwrm_tfc_session_id_alloc_input (size:128b/16B) */ +/* hwrm_tfc_session_id_alloc_input (size:192b/24B) */ typedef struct hwrm_tfc_session_id_alloc_input { /* The HWRM command request type. */ @@ -52370,6 +56357,17 @@ typedef struct hwrm_tfc_session_id_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; + /* Unused field */ + uint8_t unused0[6]; } hwrm_tfc_session_id_alloc_input_t, *phwrm_tfc_session_id_alloc_input_t; /* hwrm_tfc_session_id_alloc_output (size:128b/16B) */ @@ -52441,13 +56439,22 @@ typedef struct hwrm_tfc_session_fid_add_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Unique session identifier for the session created by the * firmware. */ uint16_t sid; /* Unused field */ - uint8_t unused0[6]; + uint8_t unused0[4]; } hwrm_tfc_session_fid_add_input_t, *phwrm_tfc_session_fid_add_input_t; /* hwrm_tfc_session_fid_add_output (size:128b/16B) */ @@ -52519,13 +56526,22 @@ typedef struct hwrm_tfc_session_fid_rem_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Unique session identifier for the session created by the * firmware. */ uint16_t sid; /* Unused field */ - uint8_t unused0[6]; + uint8_t unused0[4]; } hwrm_tfc_session_fid_rem_input_t, *phwrm_tfc_session_fid_rem_input_t; /* hwrm_tfc_session_fid_rem_output (size:128b/16B) */ @@ -52597,6 +56613,15 @@ typedef struct hwrm_tfc_ident_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Unique session identifier for the session created by the * firmware. Will be used to track this identifier. @@ -52626,7 +56651,7 @@ typedef struct hwrm_tfc_ident_alloc_input { #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID /* Unused field */ - uint8_t unused0[3]; + uint8_t unused0; } hwrm_tfc_ident_alloc_input_t, *phwrm_tfc_ident_alloc_input_t; /* hwrm_tfc_ident_alloc_output (size:128b/16B) */ @@ -52700,6 +56725,15 @@ typedef struct hwrm_tfc_ident_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Unique session identifier for the session created by the * firmware. Will be used to validate this request. @@ -52721,8 +56755,6 @@ typedef struct hwrm_tfc_ident_free_input { #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX /* The resource identifier to be freed */ uint16_t ident_id; - /* Reserved */ - uint8_t unused0[2]; } hwrm_tfc_ident_free_input_t, *phwrm_tfc_ident_free_input_t; /* hwrm_tfc_ident_free_output (size:128b/16B) */ @@ -52785,6 +56817,15 @@ typedef struct hwrm_tfc_idx_tbl_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Unique session id for the session created by the * firmware. Will be used to track this index table entry @@ -52801,8 +56842,13 @@ typedef struct hwrm_tfc_idx_tbl_alloc_input { #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_LAST HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. + * This field is blktype specific. + * For blktype CFA - CFA resource subtype. For definitions, + * please see cfa_v3/include/cfa_resources.h. + * For blktype rxp, re_gparse, te_gparse - + * Tunnel Type. A value of zero (or unknown) means alloc. A known + * value (previously allocated dynamic UPAR for tunnel_type) means + * realloc. Will fail if a realloc is for previously allocated FID, */ uint8_t subtype; /* Describes the type of tracking id to be used */ @@ -52814,8 +56860,17 @@ typedef struct hwrm_tfc_idx_tbl_alloc_input { /* Tracked by function id */ #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID - /* Reserved */ - uint8_t unused0[3]; + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE } hwrm_tfc_idx_tbl_alloc_input_t, *phwrm_tfc_idx_tbl_alloc_input_t; /* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */ @@ -52883,6 +56938,15 @@ typedef struct hwrm_tfc_idx_tbl_alloc_set_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Unique session id for the session created by the * firmware. Will be used to track this index table entry @@ -52904,8 +56968,13 @@ typedef struct hwrm_tfc_idx_tbl_alloc_set_input { */ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) /* - * CFA resource subtype. For definitions, please see - * cfa_v3/include/cfa_resources.h. + * This field is blktype specific. + * For blktype CFA - CFA resource subtype. For definitions, + * please see cfa_v3/include/cfa_resources.h. + * For blktype rxp, re_gparse, te_gparse - + * Tunnel Type. A value of zero (or unknown) means alloc. A known + * value (previously allocated dynamic UPAR for tunnel_type) means + * realloc. Will fail if a realloc is for previously allocated FID, */ uint8_t subtype; /* Describes the type of tracking id to be used */ @@ -52917,17 +56986,28 @@ typedef struct hwrm_tfc_idx_tbl_alloc_set_input { /* Tracked by function id */ #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID - /* Reserved */ - uint8_t unused0; + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE /* The size of the index table entry in bytes. */ uint16_t data_size; + /* Reserved */ + uint8_t unused1[6]; /* The location of the dma buffer */ uint64_t dma_addr; /* - * Index table data located at offset 0. If dma bit is set, + * Index table data located at offset 0. If dma bit is set, * then this field contains the DMA buffer pointer. */ - uint8_t dev_data[104]; + uint8_t dev_data[96]; } hwrm_tfc_idx_tbl_alloc_set_input_t, *phwrm_tfc_idx_tbl_alloc_set_input_t; /* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */ @@ -53014,6 +57094,15 @@ typedef struct hwrm_tfc_idx_tbl_set_input { * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Session id associated with the firmware. Will be used * for validation if the track type matches. @@ -53026,13 +57115,26 @@ typedef struct hwrm_tfc_idx_tbl_set_input { uint16_t idx_tbl_id; /* The size of the index table entry in bytes. */ uint16_t data_size; + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP gparse block type */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* unused. */ + uint8_t unused0[5]; /* The location of the dma buffer */ uint64_t dma_addr; /* - * Index table data located at offset 0. If dma bit is set, + * Index table data located at offset 0. If dma bit is set, * then this field contains the DMA buffer pointer. */ - uint8_t dev_data[104]; + uint8_t dev_data[96]; } hwrm_tfc_idx_tbl_set_input_t, *phwrm_tfc_idx_tbl_set_input_t; /* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */ @@ -53064,7 +57166,7 @@ typedef struct hwrm_tfc_idx_tbl_set_output { ************************/ -/* hwrm_tfc_idx_tbl_get_input (size:256b/32B) */ +/* hwrm_tfc_idx_tbl_get_input (size:320b/40B) */ typedef struct hwrm_tfc_idx_tbl_get_input { /* The HWRM command request type. */ @@ -53114,6 +57216,15 @@ typedef struct hwrm_tfc_idx_tbl_get_input { * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Session id associated with the firmware. Will be used * for validation if the track type matches. @@ -53126,6 +57237,19 @@ typedef struct hwrm_tfc_idx_tbl_get_input { uint16_t idx_tbl_id; /* The size of the index table entry buffer in bytes. */ uint16_t buffer_size; + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP block type */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE gparse block type */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE gparse block type */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* unused. */ + uint8_t unused0[5]; /* The location of the response dma buffer */ uint64_t dma_addr; } hwrm_tfc_idx_tbl_get_input_t, *phwrm_tfc_idx_tbl_get_input_t; @@ -53161,7 +57285,7 @@ typedef struct hwrm_tfc_idx_tbl_get_output { *************************/ -/* hwrm_tfc_idx_tbl_free_input (size:192b/24B) */ +/* hwrm_tfc_idx_tbl_free_input (size:256b/32B) */ typedef struct hwrm_tfc_idx_tbl_free_input { /* The HWRM command request type. */ @@ -53206,6 +57330,15 @@ typedef struct hwrm_tfc_idx_tbl_free_input { * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Session id associated with the firmware. Will be used * for validation if the track type matches. @@ -53213,8 +57346,19 @@ typedef struct hwrm_tfc_idx_tbl_free_input { uint16_t sid; /* Index table id to be freed by the firmware. */ uint16_t idx_tbl_id; - /* Reserved */ - uint8_t unused0[2]; + /* Specifies which block this idx table alloc request is for */ + uint8_t blktype; + /* CFA block type */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0) + /* RXP block type */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1) + /* RE parse block type */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2) + /* TE parse block type */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3) + #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_LAST HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE + /* unused. */ + uint8_t unused0[7]; } hwrm_tfc_idx_tbl_free_input_t, *phwrm_tfc_idx_tbl_free_input_t; /* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */ @@ -53305,6 +57449,15 @@ typedef struct hwrm_tfc_global_id_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ uint16_t sid; /* Global domain id. */ @@ -53315,8 +57468,6 @@ typedef struct hwrm_tfc_global_id_alloc_input { * request entries. */ uint16_t req_cnt; - /* unused. */ - uint8_t unused0[2]; /* * This is the DMA address for the request input data array * buffer. Array is of tfc_global_id_hwrm_req type. Size of the @@ -53402,6 +57553,15 @@ typedef struct hwrm_tfc_tcam_set_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Session id associated with the firmware. Will be used * for validation if the track type matches. @@ -53430,7 +57590,7 @@ typedef struct hwrm_tfc_tcam_set_input { */ uint8_t subtype; /* unused. */ - uint8_t unused0[6]; + uint8_t unused0[4]; /* The location of the response dma buffer */ uint64_t dma_addr; /* @@ -53457,7 +57617,7 @@ typedef struct hwrm_tfc_tcam_set_output { * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been - * completely written. When writing a command completion or + * completely written. When writing a command completion or * response to an internal processor, the order of writes has * to be such that this field is written last. */ @@ -53514,6 +57674,15 @@ typedef struct hwrm_tfc_tcam_get_input { * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Session id associated with the firmware. Will be used * for validation if the track type matches. @@ -53521,8 +57690,6 @@ typedef struct hwrm_tfc_tcam_get_input { uint16_t sid; /* Logical TCAM ID. */ uint16_t tcam_id; - /* unused. */ - uint8_t unused0[2]; } hwrm_tfc_tcam_get_input_t, *phwrm_tfc_tcam_get_input_t; /* hwrm_tfc_tcam_get_output (size:2368b/296B) */ @@ -53553,7 +57720,7 @@ typedef struct hwrm_tfc_tcam_get_output { * This field is used in Output records to indicate that the * output is completely written to RAM. This field should be * read as '1' to indicate that the output has been - * completely written. When writing a command completion or + * completely written. When writing a command completion or * response to an internal processor, the order of writes has * to be such that this field is written last. */ @@ -53610,6 +57777,15 @@ typedef struct hwrm_tfc_tcam_alloc_input { * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Unique session id for the session created by the * firmware. Will be used to track this index table entry @@ -53630,7 +57806,7 @@ typedef struct hwrm_tfc_tcam_alloc_input { #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_LAST HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID /* Unused. */ - uint8_t unused0[7]; + uint8_t unused0[5]; } hwrm_tfc_tcam_alloc_input_t, *phwrm_tfc_tcam_alloc_input_t; /* hwrm_tfc_tcam_alloc_output (size:128b/16B) */ @@ -53714,6 +57890,15 @@ typedef struct hwrm_tfc_tcam_alloc_set_input { * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Unique session id for the session created by the * firmware. Will be used to track this index table entry @@ -53736,11 +57921,11 @@ typedef struct hwrm_tfc_tcam_alloc_set_input { #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_LAST HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID /* Unused */ - uint8_t unused[5]; + uint8_t unused[3]; /* The location of the response dma buffer */ uint64_t dma_addr; /* - * Index table data located at offset 0. If dma bit is set, + * Index table data located at offset 0. If dma bit is set, * then this field contains the DMA buffer pointer. */ uint8_t dev_data[96]; @@ -53822,6 +58007,15 @@ typedef struct hwrm_tfc_tcam_free_input { * cfa_v3/include/cfa_resources.h. */ uint8_t subtype; + /* + * Function ID. + * If running on a trusted VF or PF, the fid field can be used to + * specify that the function is a non-trusted VF of the parent PF. + * If this command is used for the target_id itself, this field is + * set to 0xffff. A non-trusted VF cannot specify a valid FID in this + * field. + */ + uint16_t fid; /* * Session id associated with the firmware. Will be used * for validation if the track type matches. @@ -53829,8 +58023,6 @@ typedef struct hwrm_tfc_tcam_free_input { uint16_t sid; /* Logical TCAM ID. */ uint16_t tcam_id; - /* Reserved */ - uint8_t unused0[2]; } hwrm_tfc_tcam_free_input_t, *phwrm_tfc_tcam_free_input_t; /* hwrm_tfc_tcam_free_output (size:128b/16B) */ @@ -53857,6 +58049,371 @@ typedef struct hwrm_tfc_tcam_free_output { uint8_t valid; } hwrm_tfc_tcam_free_output_t, *phwrm_tfc_tcam_free_output_t; +/*********************** + * hwrm_tfc_if_tbl_set * + ***********************/ + + +/* hwrm_tfc_if_tbl_set_input (size:960b/120B) */ + +typedef struct hwrm_tfc_if_tbl_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Session identifier. */ + uint16_t sid; + /* Function identifier. */ + uint16_t fid; + /* + * Subtype identifying IF table type. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_TX + /* Table entry index. */ + uint16_t index; + /* Size of data in data field. */ + uint8_t data_size; + /* Reserved */ + uint8_t unused0[7]; + /* Table data. */ + uint8_t data[88]; +} hwrm_tfc_if_tbl_set_input_t, *phwrm_tfc_if_tbl_set_input_t; + +/* hwrm_tfc_if_tbl_set_output (size:128b/16B) */ + +typedef struct hwrm_tfc_if_tbl_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Reserved */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tfc_if_tbl_set_output_t, *phwrm_tfc_if_tbl_set_output_t; + +/*********************** + * hwrm_tfc_if_tbl_get * + ***********************/ + + +/* hwrm_tfc_if_tbl_get_input (size:256b/32B) */ + +typedef struct hwrm_tfc_if_tbl_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Session identifier. */ + uint16_t sid; + /* Function identifier. */ + uint16_t fid; + /* + * Subtype identifying IF table type. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_LAST HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_TX + /* Table entry index. */ + uint16_t index; + /* Size of data in data field. */ + uint8_t data_size; + /* Reserved */ + uint8_t unused0[7]; +} hwrm_tfc_if_tbl_get_input_t, *phwrm_tfc_if_tbl_get_input_t; + +/* hwrm_tfc_if_tbl_get_output (size:960b/120B) */ + +typedef struct hwrm_tfc_if_tbl_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Session identifier. */ + uint16_t sid; + /* Function identifier. */ + uint16_t fid; + /* + * Subtype identifying IF table type. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_LAST HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_TX + /* Table entry index. */ + uint16_t index; + /* Size of data in data field. */ + uint8_t data_size; + /* Reserved */ + uint8_t unused0[7]; + /* Table data. */ + uint8_t data[88]; + /* Reserved */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tfc_if_tbl_get_output_t, *phwrm_tfc_if_tbl_get_output_t; + +/********************************* + * hwrm_tfc_tbl_scope_config_get * + *********************************/ + + +/* TruFlow command to return whether the table scope is fully configured. */ +/* hwrm_tfc_tbl_scope_config_get_input (size:192b/24B) */ + +typedef struct hwrm_tfc_tbl_scope_config_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} hwrm_tfc_tbl_scope_config_get_input_t, *phwrm_tfc_tbl_scope_config_get_input_t; + +/* hwrm_tfc_tbl_scope_config_get_output (size:128b/16B) */ + +typedef struct hwrm_tfc_tbl_scope_config_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* If set to 1, the table scope is configured. */ + uint8_t configured; + /* unused. */ + uint8_t unused0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tfc_tbl_scope_config_get_output_t, *phwrm_tfc_tbl_scope_config_get_output_t; + +/***************************** + * hwrm_tfc_resc_usage_query * + *****************************/ + + +/* hwrm_tfc_resc_usage_query_input (size:256b/32B) */ + +typedef struct hwrm_tfc_resc_usage_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Session identifier. */ + uint16_t sid; + /* Function identifier. */ + uint16_t fid; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_LAST HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2) + #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_LAST HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Size of data in data field. */ + uint16_t data_size; + /* unused */ + uint8_t unused1[8]; +} hwrm_tfc_resc_usage_query_input_t, *phwrm_tfc_resc_usage_query_input_t; + +/* hwrm_tfc_resc_usage_query_output (size:960b/120B) */ + +typedef struct hwrm_tfc_resc_usage_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Size of data in data field. */ + uint16_t data_size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[96]; + /* unused */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} hwrm_tfc_resc_usage_query_output_t, *phwrm_tfc_resc_usage_query_output_t; + /****************************** * hwrm_tunnel_dst_port_query * ******************************/ @@ -53896,27 +58453,56 @@ typedef struct hwrm_tunnel_dst_port_query_input { /* Tunnel Type. */ uint8_t tunnel_type; /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) /* Custom GRE uses UPAR to parse customized GRE packets */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) /* Enhanced Common Packet Radio Interface (eCPRI) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) /* IPv6 Segment Routing (SRv6) */ - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE - uint8_t unused_0[7]; + /* Generic Routing Encapsulation */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11) + /* ULP Dynamic UPAR tunnel */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12) + /* ULP Dynamic UPAR tunnel reserved 1 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13) + /* ULP Dynamic UPAR tunnel reserved 2 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14) + /* ULP Dynamic UPAR tunnel reserved 3 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15) + /* ULP Dynamic UPAR tunnel reserved 4 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16) + /* ULP Dynamic UPAR tunnel reserved 5 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17) + /* ULP Dynamic UPAR tunnel reserved 6 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18) + /* ULP Dynamic UPAR tunnel reserved 7 */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19) + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 + /* + * This field is used to specify the next protocol value defined in the + * corresponding RFC spec for the applicable tunnel type. + */ + uint8_t tunnel_next_proto; + uint8_t unused_0[6]; } hwrm_tunnel_dst_port_query_input_t, *phwrm_tunnel_dst_port_query_input_t; /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ @@ -53971,12 +58557,24 @@ typedef struct hwrm_tunnel_dst_port_query_output { #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40) /* This bit will be '1' when UPAR7 is IN_USE */ #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80) - uint8_t unused_0[2]; + /* + * This field is used to convey the status of non udp port based + * tunnel parsing at chip level and at function level. + */ + uint8_t status; + /* This bit will be '1' when tunnel parsing is enabled globally. */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_CHIP_LEVEL UINT32_C(0x1) + /* + * This bit will be '1' when tunnel parsing is enabled + * on the corresponding function. + */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_FUNC_LEVEL UINT32_C(0x2) + uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54021,27 +58619,58 @@ typedef struct hwrm_tunnel_dst_port_alloc_input { /* Tunnel Type. */ uint8_t tunnel_type; /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* + * Custom GRE uses UPAR to parse customized GRE packets. This is not + * supported. + */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) /* Enhanced Common Packet Radio Interface (eCPRI) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) /* IPv6 Segment Routing (SRv6) */ - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE - uint8_t unused_0; + /* Generic Routing Encapsulation */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11) + /* ULP Dynamic UPAR tunnel */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12) + /* ULP Dynamic UPAR tunnel reserved 1 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13) + /* ULP Dynamic UPAR tunnel reserved 2 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14) + /* ULP Dynamic UPAR tunnel reserved 3 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15) + /* ULP Dynamic UPAR tunnel reserved 4 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16) + /* ULP Dynamic UPAR tunnel reserved 5 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17) + /* ULP Dynamic UPAR tunnel reserved 6 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18) + /* ULP Dynamic UPAR tunnel reserved 7 */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19) + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 + /* + * This field is used to specify the next protocol value defined in the + * corresponding RFC spec for the applicable tunnel type. + */ + uint8_t tunnel_next_proto; /* * This field represents the value of L4 destination port used * for the given tunnel type. This field is valid for @@ -54053,7 +58682,7 @@ typedef struct hwrm_tunnel_dst_port_alloc_input { * A value of 0 shall fail the command. */ uint16_t tunnel_dst_port_val; - uint8_t unused_1[4]; + uint8_t unused_0[4]; } hwrm_tunnel_dst_port_alloc_input_t, *phwrm_tunnel_dst_port_alloc_input_t; /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ @@ -54068,8 +58697,8 @@ typedef struct hwrm_tunnel_dst_port_alloc_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * Identifier of a tunnel L4 destination port value. Only applies to tunnel - * types that has l4 destination port parameters. + * Identifier of a tunnel L4 destination port value. Only applies to + * tunnel types that has l4 destination port parameters. */ uint16_t tunnel_dst_port_id; /* Error information */ @@ -54080,7 +58709,9 @@ typedef struct hwrm_tunnel_dst_port_alloc_output { #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED UINT32_C(0x1) /* Out of resources error */ #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE UINT32_C(0x2) - #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE + /* Tunnel type is already enabled */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED UINT32_C(0x3) + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED /* * This field represents the UPAR usage status. * Available UPARs on wh+ are UPAR0 and UPAR1 @@ -54107,9 +58738,9 @@ typedef struct hwrm_tunnel_dst_port_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54154,33 +58785,64 @@ typedef struct hwrm_tunnel_dst_port_free_input { /* Tunnel Type. */ uint8_t tunnel_type; /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + /* + * Enhance Generic Routing Encapsulation (GRE version 1) inside IP + * datagram payload + */ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) + /* + * IPV6 over virtual eXtensible Local Area Network with GPE header + * (IPV6oVXLANGPE) + */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* + * Custom GRE uses UPAR to parse customized GRE packets. This is not + * supported. + */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd) /* Enhanced Common Packet Radio Interface (eCPRI) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe) /* IPv6 Segment Routing (SRv6) */ - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf) /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10) - #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE - uint8_t unused_0; + /* Generic Routing Encapsulation */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11) + /* ULP Dynamic UPAR tunnel */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12) + /* ULP Dynamic UPAR tunnel reserved 1 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13) + /* ULP Dynamic UPAR tunnel reserved 2 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14) + /* ULP Dynamic UPAR tunnel reserved 3 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15) + /* ULP Dynamic UPAR tunnel reserved 4 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16) + /* ULP Dynamic UPAR tunnel reserved 5 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17) + /* ULP Dynamic UPAR tunnel reserved 6 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18) + /* ULP Dynamic UPAR tunnel reserved 7 */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19) + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 /* - * Identifier of a tunnel L4 destination port value. Only applies to tunnel - * types that has l4 destination port parameters. + * This field is used to specify the next protocol value defined in the + * corresponding RFC spec for the applicable tunnel type. + */ + uint8_t tunnel_next_proto; + /* + * Identifier of a tunnel L4 destination port value. Only applies to + * tunnel types that has l4 destination port parameters. */ uint16_t tunnel_dst_port_id; - uint8_t unused_1[4]; + uint8_t unused_0[4]; } hwrm_tunnel_dst_port_free_input_t, *phwrm_tunnel_dst_port_free_input_t; /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ @@ -54206,9 +58868,9 @@ typedef struct hwrm_tunnel_dst_port_free_output { uint8_t unused_1[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54366,7 +59028,7 @@ typedef struct ctx_eng_stats { ***********************/ -/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ +/* hwrm_stat_ctx_alloc_input (size:320b/40B) */ typedef struct hwrm_stat_ctx_alloc_input { /* The HWRM command request type. */ @@ -54438,6 +59100,17 @@ typedef struct hwrm_stat_ctx_alloc_input { * for the periodic DMA updates. */ uint16_t stats_dma_length; + uint16_t flags; + /* This stats context uses the steering tag specified in the command. */ + #define HWRM_STAT_CTX_ALLOC_INPUT_FLAGS_STEERING_TAG_VALID UINT32_C(0x1) + /* + * Steering tag to use for memory transactions from the periodic DMA + * updates. 'steering_tag_valid' should be set and 'steering_tag' + * should be specified, when the 'steering_tag_supported' bit is set + * under the 'flags_ext2' field of the hwrm_func_qcaps_output. + */ + uint16_t steering_tag; + uint32_t unused_1; } hwrm_stat_ctx_alloc_input_t, *phwrm_stat_ctx_alloc_input_t; /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ @@ -54456,9 +59129,9 @@ typedef struct hwrm_stat_ctx_alloc_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54521,9 +59194,9 @@ typedef struct hwrm_stat_ctx_free_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54631,9 +59304,9 @@ typedef struct hwrm_stat_ctx_query_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54745,9 +59418,9 @@ typedef struct hwrm_stat_ext_ctx_query_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54849,9 +59522,9 @@ typedef struct hwrm_stat_ctx_eng_query_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54912,9 +59585,9 @@ typedef struct hwrm_stat_ctx_clr_stats_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -54986,9 +59659,9 @@ typedef struct hwrm_pcie_qstats_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -55071,7 +59744,7 @@ typedef struct hwrm_stat_generic_qstats_input { * The size of the generic statistics buffer passed in the * generic_stat_host_addr in bytes. * Firmware will not exceed this size when it DMAs the - * statistics structure to the host. The actual DMA size + * statistics structure to the host. The actual DMA size * will be returned in the response. */ uint16_t generic_stat_size; @@ -55106,7 +59779,7 @@ typedef struct hwrm_stat_generic_qstats_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -55116,7 +59789,7 @@ typedef struct hwrm_stat_generic_qstats_output { } hwrm_stat_generic_qstats_output_t, *phwrm_stat_generic_qstats_output_t; /* Generic Statistic Format */ -/* generic_sw_hw_stats (size:1408b/176B) */ +/* generic_sw_hw_stats (size:1472b/184B) */ typedef struct generic_sw_hw_stats { /* @@ -55161,34 +59834,34 @@ typedef struct generic_sw_hw_stats { /* Available completion flow control data credits. */ uint64_t pcie_credit_fc_cmpl_data_posted; /* - * Displays Time information of the longest completon time from any of - * the 4 tags for the caller PF. The unit of time recorded is in + * Displays Time information of the longest completion time from any of + * the 4 tags for the caller PF. The unit of time recorded is in * microseconds. */ uint64_t pcie_cmpl_longest; /* - * Displays Time information of the shortest completon time from any of - * the 4 tags for the caller PF. The unit of time recorded is in + * Displays Time information of the shortest completion time from any + * of the 4 tags for the caller PF. The unit of time recorded is in * microseconds. */ uint64_t pcie_cmpl_shortest; /* - * This field containts the total number of CFCQ 'misses' observed for + * This field contains the total number of CFCQ 'misses' observed for * all the PF's. */ uint64_t cache_miss_count_cfcq; /* - * This field containts the total number of CFCS 'misses' observed for + * This field contains the total number of CFCS 'misses' observed for * all the PF's. */ uint64_t cache_miss_count_cfcs; /* - * This field containts the total number of CFCC 'misses' observed for + * This field contains the total number of CFCC 'misses' observed for * all the PF's. */ uint64_t cache_miss_count_cfcc; /* - * This field containts the total number of CFCM 'misses' observed + * This field contains the total number of CFCM 'misses' observed * for all the PF's. */ uint64_t cache_miss_count_cfcm; @@ -55210,8 +59883,107 @@ typedef struct generic_sw_hw_stats { * the hardware based doorbell drop recovery feature. */ uint64_t hw_db_recov_dbs_recovered; + /* + * Total number of out of order doorbell messages dropped. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_oo_drop_count; } generic_sw_hw_stats_t, *pgeneric_sw_hw_stats_t; +/***************************** + * hwrm_stat_db_error_qstats * + *****************************/ + + +/* hwrm_stat_db_error_qstats_input (size:128b/16B) */ + +typedef struct hwrm_stat_db_error_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_stat_db_error_qstats_input_t, *phwrm_stat_db_error_qstats_input_t; + +/* hwrm_stat_db_error_qstats_output (size:320b/40B) */ + +typedef struct hwrm_stat_db_error_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies count of doorbells dropped due to RoCE SQs or L2 + * Tx Rings being in invalid state. + */ + uint32_t tx_db_drop_invalid_qp_state; + /* + * Specifies count of doorbells dropped due to RoCE RQs/SRQs or + * L2 Rx Rings being used in invalid state. + */ + uint32_t rx_db_drop_invalid_rq_state; + /* + * Specifies count of doorbells dropped for any doorbell type + * due to formatting errors such as illegal doorbell message + * type, index out of range etc. + */ + uint32_t tx_db_drop_format_error; + /* + * Specifies count of express mode doorbells dropped for any + * doorbell type due to error conditions such as DPI check, + * context load error etc. + */ + uint32_t express_db_dropped_misc_error; + /* + * Specifies count of express mode doorbells dropped due to + * RoCE SQ overflow. + */ + uint32_t express_db_dropped_sq_overflow; + /* + * Specifies count of express mode doorbells dropped due to + * RoCE RQ overflow. + */ + uint32_t express_db_dropped_rq_overflow; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_stat_db_error_qstats_output_t, *phwrm_stat_db_error_qstats_output_t; + /***************** * hwrm_fw_reset * *****************/ @@ -55259,8 +60031,8 @@ typedef struct hwrm_fw_reset_input { /* RoCE control processor */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3) /* - * Host (in multi-host environment): This is only valid if requester is IPC. - * Reinit host hardware resources and PCIe. + * Host (in multi-host environment): This is only valid if requester + * is IPC. Reinit host hardware resources and PCIe. */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4) /* @@ -55271,17 +60043,17 @@ typedef struct hwrm_fw_reset_input { /* Reset all blocks of the chip (including all processors) */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6) /* - * Host (in multi-host environment): This is only valid if requester is IPC. - * Reinit host hardware resources. + * Host (in multi-host environment): This is only valid if requester + * is IPC. Reinit host hardware resources. */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT UINT32_C(0x7) /* - * Activate firmware that has been programmed to NVM. The + * Activate firmware that has been programmed to NVM. The * activation is done in an impactless manner as part of the scheme * where hwrm_fw_state_backup precedes the call, and - * hwrm_fw_state_restore follows it. Before this call returns, FW + * hwrm_fw_state_restore follows it. Before this call returns, FW * status is set to a non-0x8000 value to disambiguate reset pending - * from reset complete. The reset process begins after this call + * from reset complete. The reset process begins after this call * returns to ensure this HWRM has completed before reset begins. */ #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION UINT32_C(0x8) @@ -55306,8 +60078,9 @@ typedef struct hwrm_fw_reset_input { uint8_t flags; /* * When this bit is '1', then the core firmware initiates - * the reset only after graceful shut down of all registered instances. - * If not, the device will continue with the existing firmware. + * the reset only after graceful shut down of all registered + * instances. If not, the device will continue with the existing + * firmware. */ #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1) /* @@ -55345,9 +60118,9 @@ typedef struct hwrm_fw_reset_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -55399,9 +60172,15 @@ typedef struct hwrm_fw_qstatus_input { #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2) /* RoCE control processor */ #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3) - /* Host (in multi-host environment): This is only valid if requester is IPC */ + /* + * Host (in multi-host environment): This is only valid if requester + * is IPC + */ #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4) - /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */ + /* + * AP processor complex (in multi-host environment). Use host_idx to + * control which core is reset + */ #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5) /* Reset all blocks of the chip (including all processors) */ #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6) @@ -55449,9 +60228,9 @@ typedef struct hwrm_fw_qstatus_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -55535,9 +60314,9 @@ typedef struct hwrm_fw_set_time_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -55620,9 +60399,9 @@ typedef struct hwrm_fw_get_time_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -55643,9 +60422,15 @@ typedef struct hwrm_struct_hdr { #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_APP UINT32_C(0x421) /* DCBX state configuration structured data ID for all DCBX features. */ #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE UINT32_C(0x422) - /* LLDP generic structured data ID. This is used with GET_STRUCTURED_DATA only. */ + /* + * LLDP generic structured data ID. This is used with + * GET_STRUCTURED_DATA only. + */ #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_GENERIC UINT32_C(0x424) - /* LLDP device structured data ID. This is used with GET_STRUCTURED_DATA only. */ + /* + * LLDP device structured data ID. This is used with + * GET_STRUCTURED_DATA only. + */ #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_DEVICE UINT32_C(0x426) /* Power Backup info */ #define HWRM_STRUCT_HDR_STRUCT_ID_POWER_BKUP UINT32_C(0x427) @@ -55667,9 +60452,9 @@ typedef struct hwrm_struct_hdr { /* This value indicates the subtype. */ uint16_t subtype; /* - * This value indicates the count of 64-bit values that point to the next header. - * A value of 0 means that this is the last element. The value is a count of 64-bit - * words from the beginning of the current header. + * This value indicates the count of 64-bit values that point to the next + * header. A value of 0 means that this is the last element. The value is + * a count of 64-bit words from the beginning of the current header. */ uint16_t next_offset; /* This value indicates this is the last element */ @@ -55681,8 +60466,9 @@ typedef struct hwrm_struct_hdr { typedef struct hwrm_struct_data_dcbx_ets { /* - * This field indicates if this configuration is ETS recommendation or ETS configuration. - * A value 1 means it is ETS configuration, A value of 2 means it is a ETS recommendation. + * This field indicates if this configuration is ETS recommendation or + * ETS configuration. A value 1 means it is ETS configuration, A value of + * 2 means it is a ETS recommendation. */ uint8_t destination; /* ETS configuration */ @@ -55758,8 +60544,9 @@ typedef struct hwrm_struct_data_dcbx_ets { typedef struct hwrm_struct_data_dcbx_pfc { /* - * This field indicates PFC priority bit map. A value of '0' indicates PFC - * is disabled. A value of '1' indicates PFC is enabled on that priority. + * This field indicates PFC priority bit map. A value of '0' indicates + * PFC is disabled. A value of '1' indicates PFC is enabled on that + * priority. */ uint8_t pfc_priority_bitmap; /* @@ -55769,7 +60556,8 @@ typedef struct hwrm_struct_data_dcbx_pfc { uint8_t max_pfc_tcs; /* * This field indicates if MACSec bypass capability is enabled. A value - * of '1' indicates MBC is enabled. A value of '0' indicates MBC is disabled. + * of '1' indicates MBC is enabled. A value of '0' indicates MBC is + * disabled. */ uint8_t mbc; uint8_t unused_0[5]; @@ -55831,7 +60619,10 @@ typedef struct hwrm_struct_data_dcbx_feature_state { #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_LAST HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS /* unused. */ uint8_t unused[3]; - /* This field is used to reset the DCBX configuration to factory defaults. */ + /* + * This field is used to reset the DCBX configuration to factory + * defaults. + */ uint8_t resets; /* reset ETS configuration. */ #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS UINT32_C(0x1) @@ -55961,8 +60752,8 @@ typedef struct hwrm_struct_data_lldp_device { typedef struct hwrm_struct_data_port_description { /* - * Port #. Port number starts at 0 and anything greater than number of ports - * minus 1 is an error. + * Port #. Port number starts at 0 and anything greater than number of + * ports minus 1 is an error. */ uint8_t port_id; uint8_t unused_0[7]; @@ -56026,9 +60817,9 @@ typedef struct hwrm_struct_data_power_information { uint32_t bkup_power_info_ver; /* Platform backup power count */ uint32_t platform_bkup_power_count; - /* Load in milli Watt */ + /* Load in milliwatts */ uint32_t load_milli_watt; - /* Backup time in milli seconds */ + /* Backup time in milliseconds */ uint32_t bkup_time_milli_seconds; /* Backup power status */ uint32_t bkup_power_status; @@ -56143,9 +60934,9 @@ typedef struct hwrm_fw_set_structured_data_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56215,21 +61006,23 @@ typedef struct hwrm_fw_get_structured_data_input { /* size of data in bytes */ uint16_t data_len; /* - * Structure_id is the id of the structure data requesting and count is a - * requested number of instances of this data requested. The actual number - * will be returned in count_of_headers + * Structure_id is the id of the structure data requesting and count is + * a requested number of instances of this data requested. The actual + * number will be returned in count_of_headers */ uint16_t structure_id; /* - * Subtype is an optional field used to specify additional information of the data - * being retrieved. For example, if data can be categorized as "live" vs "saved" - * then this field can be used to provide an indication of "saved" vs "live" data. - * Not all structured data supports subtypes and if they are supported then the - * structured data will specify the valid values. If structured data is requested - * that supports subtypes but no subtype is given then it is implementation specific - * what will be returned. Some structure data can support a subtype of "All" which - * would cause a list of structures to be returned for all supported subtypes. "All" - * is only used on the hwrm_get_structured_data command. + * Subtype is an optional field used to specify additional information + * of the data being retrieved. For example, if data can be categorized + * as "live" vs "saved" then this field can be used to provide an + * indication of "saved" vs "live" data. Not all structured data + * supports subtypes and if they are supported then the structured data + * will specify the valid values. If structured data is requested that + * supports subtypes but no subtype is given then it is implementation + * specific what will be returned. Some structure data can support a + * subtype of "All" which would cause a list of structures to be + * returned for all supported subtypes. "All" is only used on the + * hwrm_get_structured_data command. */ uint16_t subtype; #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_UNUSED UINT32_C(0x0) @@ -56242,7 +61035,7 @@ typedef struct hwrm_fw_get_structured_data_input { #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_OPERATIONAL UINT32_C(0x202) #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL UINT32_C(0x300) #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_LAST HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL - /* Number of elements. This allows support of arrayed data */ + /* Number of elements. This allows support of arrayed data */ uint8_t count; uint8_t unused_0; } hwrm_fw_get_structured_data_input_t, *phwrm_fw_get_structured_data_input_t; @@ -56266,9 +61059,9 @@ typedef struct hwrm_fw_get_structured_data_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56350,10 +61143,12 @@ typedef struct hwrm_fw_ipc_msg_input { /* Command ID */ uint16_t command_id; /* RoCE LAG message */ - #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_LAG UINT32_C(0x1) + #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_LAG UINT32_C(0x1) /* Query information on PF mapping for x86 and MAIA. */ - #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST UINT32_C(0x2) - #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_LAST HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST + #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST UINT32_C(0x2) + /* RoCE driver version details to be sent to chimp */ + #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_DRVR_VERSION UINT32_C(0x3) + #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_LAST HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_DRVR_VERSION /* Source processor for this command. */ uint8_t src_processor; /* Chimp processor */ @@ -56392,9 +61187,9 @@ typedef struct hwrm_fw_ipc_msg_output { uint8_t reserved48[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56464,9 +61259,9 @@ typedef struct hwrm_fw_ipc_mailbox_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56554,9 +61349,9 @@ typedef struct hwrm_fw_ecn_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56617,9 +61412,9 @@ typedef struct hwrm_fw_ecn_qcfg_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56742,12 +61537,32 @@ typedef struct hwrm_fw_health_check_output { * or '1' if they do not match. */ #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FRU_MISMATCH UINT32_C(0x1000) + /* + * This bit is '0' if the primary CRT2 was used this boot, + * or '1' if the secondary CRT2 was used. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_BOOTED UINT32_C(0x2000) + /* + * This bit is '0' if the primary and secondary CRT2 images + * match, or '1' if they do not match. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_MISMATCH UINT32_C(0x4000) + /* + * This bit is '0' if the primary GXRT was used this boot, + * or '1' if the secondary GXRT was used. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_BOOTED UINT32_C(0x8000) + /* + * This bit is '0' if the primary and secondary GXRT images + * match, or '1' if they do not match. + */ + #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_MISMATCH UINT32_C(0x10000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56812,12 +61627,12 @@ typedef struct hwrm_fw_livepatch_query_output { uint16_t resp_len; /* * This field represents the patch version string of the NVM installed - * livepatch. (ASCII chars with NULL at the end). + * livepatch. (ASCII chars with NULL at the end). */ char install_ver[32]; /* * This field represents the patch version string of the active - * livepatch. (ASCII chars with NULL at the end). + * livepatch. (ASCII chars with NULL at the end). */ char active_ver[32]; uint16_t status_flags; @@ -56828,9 +61643,9 @@ typedef struct hwrm_fw_livepatch_query_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56876,7 +61691,7 @@ typedef struct hwrm_fw_livepatch_input { uint8_t opcode; /* * Activate a livepatch that is NVM installed or via direct load - * from host memory. Activate will authenticate a signed patch, + * from host memory. Activate will authenticate a signed patch, * verify the patch version for compatibility and apply the * livepatch to existing firmware at run-time. */ @@ -56899,7 +61714,7 @@ typedef struct hwrm_fw_livepatch_input { /* Load a livepatch currently installed on NVM. */ #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_NVM_INSTALL UINT32_C(0x1) /* - * Load a livepatch directly from host memory. The livepatch image + * Load a livepatch directly from host memory. The livepatch image * is available at host_addr. */ #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_MEMORY_DIRECT UINT32_C(0x2) @@ -56926,9 +61741,9 @@ typedef struct hwrm_fw_livepatch_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -56952,16 +61767,16 @@ typedef struct hwrm_fw_livepatch_cmd_err { #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED UINT32_C(0x3) /* Livepatch image is not installed in NVRAM. */ #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED UINT32_C(0x4) - /* Deactivate failed. Firmware is not currently patched. */ + /* Deactivate failed. Firmware is not currently patched. */ #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED UINT32_C(0x5) /* Authentication of a signed livepatch failed. */ #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL UINT32_C(0x6) - /* Livepatch header check failed. Patch incompatible. */ + /* Livepatch header check failed. Patch incompatible. */ #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER UINT32_C(0x7) /* Livepatch size incompatible. */ #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE UINT32_C(0x8) /* - * Activate failed. Firmware has already been patched. Deactivate + * Activate failed. Firmware has already been patched. Deactivate * existing livepatch before proceeding. */ #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED UINT32_C(0x9) @@ -57051,10 +61866,24 @@ typedef struct hwrm_fw_sync_input { * FRU to the backup FRU. */ #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_FRU UINT32_C(0x40) + /* + * If action is '1' (sync) and this bit is set, the CRT2 + * images will be synchronized, copying from the instance + * used for boot to the other instance, if they currently + * do not match. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT2 UINT32_C(0x80) + /* + * If action is '1' (sync) and this bit is set, the GXRT + * images will be synchronized, copying from the instance + * used for boot to the other instance, if they currently + * do not match. + */ + #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_GXRT UINT32_C(0x100) /* * A value of '1' instructs the firmware to perform an image * synchronization of the firmware types denoted by the - * sync_sbi, sync_srt, sync_crt bits. A value of '0' just + * sync_sbi, sync_srt, sync_crt, sync_crt2 bits. A value of '0' just * requests the status for the previously requested sync * operation. */ @@ -57090,7 +61919,7 @@ typedef struct hwrm_fw_sync_output { #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL UINT32_C(0x3) #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_LAST HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL /* - * This bit is '1' if the syncronization request has completed + * This bit is '1' if the synchronization request has completed * with an error; the 'err_code' field can be used to obtain * information about error type. */ @@ -57098,7 +61927,7 @@ typedef struct hwrm_fw_sync_output { /* * This bit is '0' if the previously requested synchronization * command is still in progress, or '1' if the previously - * requested sync command has completed. If '1', the 'sync_err' + * requested sync command has completed. If '1', the 'sync_err' * field will indicate if it completed successfully or with * an error. */ @@ -57106,9 +61935,9 @@ typedef struct hwrm_fw_sync_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -57165,7 +61994,7 @@ typedef struct hwrm_fw_state_qcaps_output { uint16_t resp_len; /* * This field indicates the size in bytes required by host backup - * memory. Host software should allocate memory according to this + * memory. Host software should allocate memory according to this * size requirement and pass the allocated memory to the * HWRM_FW_STATE_BACKUP and HWRM_FW_STATE_RESTORE commands in the form * of PBL data as specified in those commands. @@ -57198,7 +62027,7 @@ typedef struct hwrm_fw_state_qcaps_output { uint32_t fw_status_blackout; /* * This field indicates a max time for firmware to poll for status - * 0x8000 before assuming a reset failure occurred. This time does + * 0x8000 before assuming a reset failure occurred. This time does * not include fw_status_blackout time which would immediately precede * this wait. */ @@ -57207,9 +62036,9 @@ typedef struct hwrm_fw_state_qcaps_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -57355,9 +62184,9 @@ typedef struct hwrm_fw_state_unquiesce_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -57464,7 +62293,7 @@ typedef struct hwrm_fw_state_backup_output { * This bit is '0' if the backout was done in a way that firmware * may continue running normally after the backup, for example if * the host elects to skip the subsequent reset and restore for any - * reason. A value of '1' indicates the act of backing up has left + * reason. A value of '1' indicates the act of backing up has left * the firmware/device in a state where subsequent reset is * required, for example of probing state of a queue leaves changes * state in a way that is detectable by users. @@ -57476,9 +62305,9 @@ typedef struct hwrm_fw_state_backup_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -57586,7 +62415,7 @@ typedef struct hwrm_fw_state_restore_output { /* * If a failure occurs (complete is 0), restore attempts to * completely roll back any state applied so that the failure - * results in no state change. This flag indicates whether that + * results in no state change. This flag indicates whether that * rollback completed successfully and thoroughly. */ #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_FAILURE_ROLLBACK_COMPLETED UINT32_C(0x40000000) @@ -57595,9 +62424,9 @@ typedef struct hwrm_fw_state_restore_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -57722,7 +62551,7 @@ typedef struct hwrm_fw_secure_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -57799,9 +62628,9 @@ typedef struct hwrm_exec_fwd_resp_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -57875,9 +62704,9 @@ typedef struct hwrm_reject_fwd_resp_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -57929,7 +62758,7 @@ typedef struct hwrm_fwd_resp_input { uint16_t encap_resp_target_id; /* * This value indicates the completion ring the encapsulated - * response will be optionally completed on. If the value is + * response will be optionally completed on. If the value is * -1, then no CR completion shall be generated for the * encapsulated response. Any other value must be a * valid CR ring_id value. If a valid encap_resp_cmpl_ring @@ -57966,9 +62795,9 @@ typedef struct hwrm_fwd_resp_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58038,9 +62867,9 @@ typedef struct hwrm_fwd_async_event_cmpl_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58084,7 +62913,7 @@ typedef struct hwrm_temp_monitor_query_input { uint64_t resp_addr; } hwrm_temp_monitor_query_input_t, *phwrm_temp_monitor_query_input_t; -/* hwrm_temp_monitor_query_output (size:128b/16B) */ +/* hwrm_temp_monitor_query_output (size:192b/24B) */ typedef struct hwrm_temp_monitor_query_output { /* The specific error status for the command. */ @@ -58135,6 +62964,11 @@ typedef struct hwrm_temp_monitor_query_output { * available. */ #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_EXT_TEMP_FIELDS_AVAILABLE UINT32_C(0x10) + /* + * "1" in this bit indicates the thermal threshold values are + * available. + */ + #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_THRESHOLD_VALUES_AVAILABLE UINT32_C(0x20) /* * This field encodes the current device temperature in Celsius. * This field is unsigned and the value range of 0 to 255 is used to @@ -58162,11 +62996,34 @@ typedef struct hwrm_temp_monitor_query_output { * 255 represents a temperature of 191. */ uint8_t om_temp2; + /* + * This field reports the device's threshold value for reporting + * a warning indication. The temperature is reported in Celsius. + */ + uint8_t warn_threshold; + /* + * This field reports the device's threshold value for reporting + * a critical indication. The temperature is reported in Celsius. + */ + uint8_t critical_threshold; + /* + * This field reports the device's threshold value for reporting + * a fatal indication. The temperature is reported in Celsius. + */ + uint8_t fatal_threshold; + /* + * This field reports the threshold value at which the device will + * a perform a self shutdown. The temperature is reported in Celsius. + * If the value is zero, then that indicates self shutdown is not + * configured. + */ + uint8_t shutdown_threshold; + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58240,9 +63097,9 @@ typedef struct hwrm_reg_power_query_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58302,9 +63159,9 @@ typedef struct hwrm_core_frequency_query_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58418,9 +63275,9 @@ typedef struct hwrm_reg_power_histogram_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58630,9 +63487,9 @@ typedef struct hwrm_wol_filter_alloc_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58713,9 +63570,9 @@ typedef struct hwrm_wol_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58874,9 +63731,9 @@ typedef struct hwrm_wol_filter_qcfg_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -58968,9 +63825,9 @@ typedef struct hwrm_wol_reason_qcfg_output { uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59014,7 +63871,7 @@ typedef struct hwrm_dbg_read_direct_input { uint64_t resp_addr; /* * host address where the data content will be written - * when the request is complete. This area must be 16B aligned. + * when the request is complete. This area must be 16B aligned. */ uint64_t host_dest_addr; /* address(in ChiMP view) to start reading */ @@ -59043,9 +63900,9 @@ typedef struct hwrm_dbg_read_direct_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59109,9 +63966,9 @@ typedef struct hwrm_dbg_write_direct_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59155,7 +64012,7 @@ typedef struct hwrm_dbg_read_indirect_input { uint64_t resp_addr; /* * host address where the data content will be written - * when the request is complete. This area must be 16B aligned. + * when the request is complete. This area must be 16B aligned. */ uint64_t host_dest_addr; /* Length of host buffer used for transferring debug data. */ @@ -59246,9 +64103,9 @@ typedef struct hwrm_dbg_read_indirect_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59367,9 +64224,9 @@ typedef struct hwrm_dbg_write_indirect_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59455,9 +64312,9 @@ typedef struct hwrm_dbg_dump_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59519,9 +64376,9 @@ typedef struct hwrm_dbg_erase_nvm_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59593,7 +64450,7 @@ typedef struct hwrm_dbg_cfg_input { /* * If set to 1, firmware is allowed to be unresponsive to heartbeat * health checks, allowing for JTAG debugging scenarios where the - * debugger has the firmware processes stopped indefinitely. This + * debugger has the firmware processes stopped indefinitely. This * flag has effect only on debug builds of firmware. */ #define HWRM_DBG_CFG_INPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20) @@ -59620,9 +64477,9 @@ typedef struct hwrm_dbg_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59765,9 +64622,9 @@ typedef struct hwrm_dbg_crashdump_header_output { uint8_t unused_2[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59843,9 +64700,9 @@ typedef struct hwrm_dbg_crashdump_erase_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -59908,7 +64765,7 @@ typedef struct hwrm_dbg_qcaps_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; @@ -59935,9 +64792,9 @@ typedef struct hwrm_dbg_qcaps_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60023,13 +64880,13 @@ typedef struct hwrm_dbg_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * FID value. This value is used to identify operations on the PCI + * FID value. This value is used to identify operations on the PCI * bus as belonging to a particular PCI function. */ uint16_t fid; uint8_t unused_0[2]; /* - * Size in bytes of a coredump file created by the FW. This takes into + * Size in bytes of a coredump file created by the FW. This takes into * consideration any components selected in the * coredump_component_disable_flags field from hwrm_dbg_qcfg_input. */ @@ -60051,7 +64908,7 @@ typedef struct hwrm_dbg_qcfg_output { */ #define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE UINT32_C(0x4) /* - * If set to 1, then completion ring logging is enabled for the + * If set to 1, then completion ring logging is enabled for the * secondary firmware. Disabled otherwise. */ #define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8) @@ -60063,7 +64920,7 @@ typedef struct hwrm_dbg_qcfg_output { /* * If set to 1, firmware is allowed to be unresponsive to heartbeat * health checks, allowing for JTAG debugging scenarios where the - * debugger has the firmware processes stopped indefinitely. This + * debugger has the firmware processes stopped indefinitely. This * flag has effect only on debug builds of firmware. */ #define HWRM_DBG_QCFG_OUTPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20) @@ -60075,16 +64932,16 @@ typedef struct hwrm_dbg_qcfg_output { uint16_t async_cmpl_ring; uint8_t unused_2[2]; /* - * Size in bytes of a crashdump file created by the FW. Uses input + * Size in bytes of a crashdump file created by the FW. Uses input * flags to determine medium destination and corresponding size. */ uint32_t crashdump_size; uint8_t unused_3[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60193,9 +65050,9 @@ typedef struct hwrm_dbg_crashdump_medium_cfg_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60272,7 +65129,7 @@ typedef struct hwrm_dbg_coredump_list_input { uint64_t resp_addr; /* * host address where the data content will be written - * when the request is complete. This area must be 16B aligned. + * when the request is complete. This area must be 16B aligned. */ uint64_t host_dest_addr; /* Length of host buffer used for transferring debug data. */ @@ -60314,9 +65171,9 @@ typedef struct hwrm_dbg_coredump_list_output { uint8_t unused_1; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60389,9 +65246,9 @@ typedef struct hwrm_dbg_coredump_initiate_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60457,7 +65314,7 @@ typedef struct hwrm_dbg_coredump_retrieve_input { uint64_t resp_addr; /* * host address where the data content will be written - * when the request is complete. This area must be 16B aligned. + * when the request is complete. This area must be 16B aligned. */ uint64_t host_dest_addr; /* Length of host buffer used for transferring debug data. */ @@ -60509,9 +65366,9 @@ typedef struct hwrm_dbg_coredump_retrieve_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60555,13 +65412,14 @@ typedef struct hwrm_dbg_i2c_cmd_input { uint64_t resp_addr; /* * host address where the data content will be read or written. - * For master write, data content will be read from host memory and write - * to i2c slave. (size defined by write_size) - * For master read, data content will be read from i2c slave and write to - * the host memory. (size defined by read_size) - * For master write/read, data content will be first read from host memory - * and write to i2c slave. (size defined by write_size) then data read from - * i2c slave will be written back to the same host memory. (size defined by read_size) + * For master write, data content will be read from host memory and + * write to i2c slave. (size defined by write_size) + * For master read, data content will be read from i2c slave and write + * to the host memory. (size defined by read_size) + * For master write/read, data content will be first read from host + * memory and write to i2c slave. (size defined by write_size) then + * data read from i2c slave will be written back to the same host + * memory. (size defined by read_size) */ uint64_t host_dest_addr; /* read size in bytes, valid only for master read and write/read */ @@ -60569,7 +65427,8 @@ typedef struct hwrm_dbg_i2c_cmd_input { /* write size in bytes, valid only for master write and write/read */ uint16_t write_size; /* - * instance of i2c channel for this operation. Valid if multiple instances + * instance of i2c channel for this operation. Valid if multiple + * instances * of i2c channels are connected to external i2c devices. */ uint8_t chnl_id; @@ -60612,9 +65471,9 @@ typedef struct hwrm_dbg_i2c_cmd_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60686,9 +65545,9 @@ typedef struct hwrm_dbg_fw_cli_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60766,12 +65625,18 @@ typedef struct hwrm_dbg_ring_info_get_output { * Not valid for other ring types. */ uint32_t cag_vector_ctrl; - uint8_t unused_0[3]; + /* + * Steering Tag. The current value of the steering tag for the ring. + * The steering tag is only valid if it is advertised by Firmware in + * flags_ext2.steering_tag_supported of hwrm_func_qcaps response. + */ + uint16_t st_tag; + uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60850,9 +65715,9 @@ typedef struct hwrm_dbg_drv_trace_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -60894,9 +65759,15 @@ typedef struct hwrm_dbg_useq_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Number size of the allocation, in bytes, for the USEQ in the code words array */ + /* + * Number size of the allocation, in bytes, for the USEQ in the code + * words array + */ uint32_t size; - /* Number of bytes executing the USEQ will produce. Must be a multiple of 4 */ + /* + * Number of bytes executing the USEQ will produce. Must be a multiple + * of 4 + */ uint16_t output_bytes; /* This field is reserved */ uint16_t unused_0; @@ -60936,9 +65807,9 @@ typedef struct hwrm_dbg_useq_alloc_output { uint16_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint32_t valid; @@ -61018,9 +65889,9 @@ typedef struct hwrm_dbg_useq_free_output { uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint32_t valid; @@ -61105,9 +65976,9 @@ typedef struct hwrm_dbg_useq_flush_output { uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint32_t valid; @@ -61154,9 +66025,9 @@ typedef struct hwrm_dbg_useq_cw_cfg_input { /* * The code words given in this message will be placed * at this offset from the starting code word for this - * usid. NOTE: when offset is zero, the first 6 32-bit + * usid. NOTE: when offset is zero, the first 6 32-bit * words may contain values for F0-F7 as well as the - * main code word index. This is determined by checking + * main code word index. This is determined by checking * the usid_ctrl_present flag. */ uint16_t offset; @@ -61172,14 +66043,14 @@ typedef struct hwrm_dbg_useq_cw_cfg_input { uint16_t flags; /* * When set, the opaque data begins with a block of control - * information to be associated with the usid. This includes + * information to be associated with the usid. This includes * F0-F7 code word indexes as well as the code word index for * main. */ #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USID_CTRL_PRESENT UINT32_C(0x1) /* * When set, opaque contains a 64b host address used to DMA - * the entire code word sequence. The offset within the + * the entire code word sequence. The offset within the * opaque data depends on the state of other flags. */ #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USE_DMA UINT32_C(0x2) @@ -61301,9 +66172,9 @@ typedef struct hwrm_dbg_useq_qcaps_output { uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint32_t valid; @@ -61350,20 +66221,21 @@ typedef struct hwrm_dbg_useq_sched_cfg_input { /* This value will leave the global scheduler in its current state */ #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_NO_CHANGE UINT32_C(0x0) /* - * This value disables the global scheduler. This mode must be used + * This value disables the global scheduler. This mode must be used * when the RUN command is being used to run individual sequences. */ #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_DISABLE UINT32_C(0x1) /* - * This value enables the global scheduler. When enabled, USEQs will + * This value enables the global scheduler. When enabled, USEQs will * be scheduled based on their polling intervals */ #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE UINT32_C(0x2) #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_LAST HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE /* - * The given polling interval will be associated with this USID. A value - * of -1 indicates that the USID is invalid. The invalid USID is used when - * using this message only for global scheduler configuration. + * The given polling interval will be associated with this USID. A + * value of -1 indicates that the USID is invalid. The invalid USID is + * used when using this message only for global scheduler + * configuration. */ uint16_t usid; /* This value represents microseconds between runs of the USEQ */ @@ -61402,9 +66274,9 @@ typedef struct hwrm_dbg_useq_sched_cfg_output { uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint32_t valid; @@ -61453,34 +66325,40 @@ typedef struct hwrm_dbg_useq_run_input { /* This run type will execute the requested USEQ only a single time */ #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_SINGLE UINT32_C(0x0) /* - * This run type will execute the requested USEQ a number of times given - * by run_cnt with a run interval given by the run_interval parameter. + * This run type will execute the requested USEQ a number of times + * given by run_cnt with a run interval given by the run_interval + * parameter. */ #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_CNT UINT32_C(0x1) /* - * This run type will execute the requested USEQ as many times as it needs - * to fill an entire buffer to return to the host. The runs will occur - * with a run interval given by the run_interval parameter. + * This run type will execute the requested USEQ as many times as it + * needs to fill an entire buffer to return to the host. The runs + * will occur with a run interval given by the run_interval + * parameter. */ #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF UINT32_C(0x2) #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_LAST HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF /* - * If indicated by flags, this represents the number of times to run the USEQ. - * Note that runs are stopped if the buffer fills prior regardless of the - * number of runs. For example, if a run_cnt of 10 is specified and 3 runs - * results in the buffer being full then only 3 runs are executed. + * If indicated by flags, this represents the number of times to run + * the USEQ. Note that runs are stopped if the buffer fills prior + * regardless of the number of runs. For example, if a run_cnt of 10 is + * specified and 3 runs results in the buffer being full then only 3 + * runs are executed. */ uint8_t run_cnt; /* - * This value represents microseconds between runs of the USEQ when running - * multiple times as indicated by flags. + * This value represents microseconds between runs of the USEQ when + * running multiple times as indicated by flags. */ uint32_t run_interval; - /* Address of the host buffer where collected USEQ output data will be placed */ + /* + * Address of the host buffer where collected USEQ output data will be + * placed + */ uint64_t host_dest_addr; /* - * Size, in bytes, of the memory associated with host_dest_addr. It is expected - * that this is >= 4096 + * Size, in bytes, of the memory associated with host_dest_addr. It is + * expected that this is >= 4096 */ uint32_t host_dest_len; /* This field is reserved */ @@ -61516,16 +66394,16 @@ typedef struct hwrm_dbg_useq_run_output { /* Reserved */ uint8_t useq_resp_unused_0[3]; /* - * The length, in bytes, of the amount of data placed in the corresponding - * host_dest_addr given in the input message. This will always be a multiple - * of 4096 + * The length, in bytes, of the amount of data placed in the + * corresponding host_dest_addr given in the input message. This will + * always be a multiple of 4096 */ uint32_t host_dest_filled_len; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint32_t valid; @@ -61568,14 +66446,15 @@ typedef struct hwrm_dbg_useq_delivery_req_input { */ uint64_t resp_addr; /* - * Eight destination addresses provide host memory space for FW to deliver - * USEQ output details. A value of 0x0 for the address can be used to - * inform FW that the buffer is not available. + * Eight destination addresses provide host memory space for FW to + * deliver USEQ output details. A value of 0x0 for the address can be + * used to inform FW that the buffer is not available. */ uint64_t host_dest_addrs[8]; /* - * The length, in bytes, of the corresponding host_dest_addrs array entry. Each - * valid hist_dest_addrs entry must have a len of at least 4096 bytes + * The length, in bytes, of the corresponding host_dest_addrs array + * entry. Each valid hist_dest_addrs entry must have a len of at least + * 4096 bytes. */ uint32_t host_dest_len[8]; } hwrm_dbg_useq_delivery_req_input_t, *phwrm_dbg_useq_delivery_req_input_t; @@ -61609,29 +66488,122 @@ typedef struct hwrm_dbg_useq_delivery_req_output { /* Reserved */ uint8_t useq_resp_unused_0[3]; /* - * The length, in bytes, of the amount of data placed in the corresponding - * host_dest_addrs entry given in the input message. This will always be a - * multiple of 4096 + * The length, in bytes, of the amount of data placed in the + * corresponding host_dest_addrs entry given in the input message. This + * will always be a multiple of 4096. */ uint32_t host_dest_filled_len[8]; /* This field is reserved */ uint32_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint32_t valid; } hwrm_dbg_useq_delivery_req_output_t, *phwrm_dbg_useq_delivery_req_output_t; +/***************************** + * hwrm_dbg_log_buffer_flush * + *****************************/ + + +/* hwrm_dbg_log_buffer_flush_input (size:192b/24B) */ + +typedef struct hwrm_dbg_log_buffer_flush_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Type of trace buffer to flush. */ + uint16_t type; + /* SRT trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT_TRACE UINT32_C(0x0) + /* SRT2 trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1) + /* CRT trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT_TRACE UINT32_C(0x2) + /* CRT2 trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT2_TRACE UINT32_C(0x3) + /* RIGP0 trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x4) + /* L2 HWRM trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x5) + /* RoCE HWRM trace. */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6) + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_LAST HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_ROCE_HWRM_TRACE + uint8_t unused_1[2]; + /* Control flags. */ + uint32_t flags; + /* + * When set, it indicates that all buffers should be flushed. + * The type will be ignored. + */ + #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_FLAGS_FLUSH_ALL_BUFFERS UINT32_C(0x1) +} hwrm_dbg_log_buffer_flush_input_t, *phwrm_dbg_log_buffer_flush_input_t; + +/* hwrm_dbg_log_buffer_flush_output (size:128b/16B) */ + +typedef struct hwrm_dbg_log_buffer_flush_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Specifies the current host buffer offset. Data up to this offset + * has been populated by the firmware. For example, if the firmware + * has DMA-ed 8192 bytes to the host buffer, then this field has a + * value of 8192. This field rolls over to zero once the firmware + * writes the last page of the host buffer + */ + uint32_t current_buffer_offset; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_dbg_log_buffer_flush_output_t, *phwrm_dbg_log_buffer_flush_output_t; + /************************** * hwrm_nvm_raw_write_blk * **************************/ -/* hwrm_nvm_raw_write_blk_input (size:256b/32B) */ +/* hwrm_nvm_raw_write_blk_input (size:320b/40B) */ typedef struct hwrm_nvm_raw_write_blk_input { /* The HWRM command request type. */ @@ -61669,11 +66641,22 @@ typedef struct hwrm_nvm_raw_write_blk_input { uint64_t host_src_addr; /* * 32-bit Destination Address. - * This is the NVRAM byte-offset where the source data will be written to. + * This is the NVRAM byte-offset where the source data will be written + * to. */ uint32_t dest_addr; /* Length of data to be written, in bytes. */ uint32_t len; + uint8_t flags; + /* + * This bit is only used when external secure SoC is used for + * secure boot. This bit is utilized to differentiate between + * writes for NIC or Security SoC non-volatile storage on the + * device. If this bit is set, then this write is for the + * Security SoC non-volatile storage on the device. + */ + #define HWRM_NVM_RAW_WRITE_BLK_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1) + uint8_t unused_0[7]; } hwrm_nvm_raw_write_blk_input_t, *phwrm_nvm_raw_write_blk_input_t; /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */ @@ -61690,9 +66673,9 @@ typedef struct hwrm_nvm_raw_write_blk_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -61763,9 +66746,9 @@ typedef struct hwrm_nvm_read_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -61776,7 +66759,7 @@ typedef struct hwrm_nvm_read_output { *********************/ -/* hwrm_nvm_raw_dump_input (size:256b/32B) */ +/* hwrm_nvm_raw_dump_input (size:320b/40B) */ typedef struct hwrm_nvm_raw_dump_input { /* The HWRM command request type. */ @@ -61816,6 +66799,16 @@ typedef struct hwrm_nvm_raw_dump_input { uint32_t offset; /* Total length of NVRAM contents to be read, in bytes. */ uint32_t len; + uint8_t flags; + /* + * This bit is only used when external secure SoC is used for + * secure boot. This bit is utilized to differentiate between + * read for NIC or Security SoC non-volatile storage on the + * device. If this bit is set, then this read is for the Security + * SoC non-volatile storage on the device. + */ + #define HWRM_NVM_RAW_DUMP_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1) + uint8_t unused_0[7]; } hwrm_nvm_raw_dump_input_t, *phwrm_nvm_raw_dump_input_t; /* hwrm_nvm_raw_dump_output (size:128b/16B) */ @@ -61832,9 +66825,9 @@ typedef struct hwrm_nvm_raw_dump_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -61897,9 +66890,9 @@ typedef struct hwrm_nvm_get_dir_entries_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -61961,9 +66954,9 @@ typedef struct hwrm_nvm_get_dir_info_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62017,7 +67010,8 @@ typedef struct hwrm_nvm_write_input { uint16_t dir_type; /* * Directory ordinal. - * The 0-based instance of the combined Directory Entry Type and Extension. + * The 0-based instance of the combined Directory Entry Type and + * Extension. */ uint16_t dir_ordinal; /* @@ -62065,13 +67059,14 @@ typedef struct hwrm_nvm_write_input { * The requested length of the allocated NVM for the item, in bytes. * This value may be greater than or equal to the specified data * length (dir_data_length). - * If this value is less than the specified data length, it will be ignored. - * The response will contain the actual allocated item length, + * If this value is less than the specified data length, it will be + * ignored. The response will contain the actual allocated item length, * which may be greater than the requested item length. * The purpose for allocating more than the required number of bytes * for an item's data is to pre-allocate extra storage (padding) to * accommodate the potential future growth of an item (e.g. upgraded - * firmware with a size increase, log growth, expanded configuration data). + * firmware with a size increase, log growth, expanded configuration + * data). */ uint32_t dir_item_length; /* @@ -62111,9 +67106,9 @@ typedef struct hwrm_nvm_write_output { uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62221,9 +67216,9 @@ typedef struct hwrm_nvm_modify_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62325,9 +67320,9 @@ typedef struct hwrm_nvm_find_dir_entry_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62388,9 +67383,9 @@ typedef struct hwrm_nvm_erase_dir_entry_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62434,7 +67429,7 @@ typedef struct hwrm_nvm_get_dev_info_input { uint64_t resp_addr; } hwrm_nvm_get_dev_info_input_t, *phwrm_nvm_get_dev_info_input_t; -/* hwrm_nvm_get_dev_info_output (size:640b/80B) */ +/* hwrm_nvm_get_dev_info_output (size:704b/88B) */ typedef struct hwrm_nvm_get_dev_info_output { /* The specific error status for the command. */ @@ -62455,7 +67450,7 @@ typedef struct hwrm_nvm_get_dev_info_output { uint32_t nvram_size; uint32_t reserved_size; /* - * Available size that can be used, in bytes. Available size is the + * Available size that can be used, in bytes. Available size is the * NVRAM size take away the used size and reserved size. */ uint32_t available_size; @@ -62539,12 +67534,33 @@ typedef struct hwrm_nvm_get_dev_info_output { * of the roce firmware. */ uint16_t roce_fw_patch; + /* + * This field represents the major version of network control firmware, + * stored in the flash. + */ + uint16_t netctrl_fw_major; + /* + * This field represents the minor version of network control firmware, + * stored in the flash. + */ + uint16_t netctrl_fw_minor; + /* + * This field represents the build version of network control firmware, + * stored in the flash. + */ + uint16_t netctrl_fw_build; + /* + * This field can be used to represent firmware branches or customer + * specific releases tied to a specific (major, minor, build) version + * of the network control firmware. + */ + uint16_t netctrl_fw_patch; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62630,9 +67646,9 @@ typedef struct hwrm_nvm_mod_dir_entry_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62708,9 +67724,9 @@ typedef struct hwrm_nvm_verify_update_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62815,8 +67831,9 @@ typedef struct hwrm_nvm_install_update_output { uint16_t resp_len; /* * Bit-mask of successfully installed items. - * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc. - * A value of 0 indicates that no items were successfully installed. + * Bit-0 corresponding to the first packaged item, Bit-1 for the second + * item, etc. A value of 0 indicates that no items were successfully + * installed. */ uint64_t installed_items; /* result is 8 b corresponding to BCMRETVAL error codes */ @@ -62910,9 +67927,9 @@ typedef struct hwrm_nvm_install_update_output { uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -62992,9 +68009,9 @@ typedef struct hwrm_nvm_flush_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -63084,8 +68101,8 @@ typedef struct hwrm_nvm_get_variable_input { uint16_t index_3; uint8_t flags; /* - * When this bit is set to 1, the factory default value will be returned, - * 0 returns the operational value. + * When this bit is set to 1, the factory default value will be + * returned, 0 returns the operational value. */ #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT UINT32_C(0x1) uint8_t unused_0; @@ -63122,9 +68139,9 @@ typedef struct hwrm_nvm_get_variable_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -63255,9 +68272,9 @@ typedef struct hwrm_nvm_set_variable_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -63376,9 +68393,9 @@ typedef struct hwrm_nvm_validate_option_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -63487,9 +68504,9 @@ typedef struct hwrm_nvm_factory_defaults_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -63577,9 +68594,9 @@ typedef struct hwrm_nvm_req_arbitration_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -63641,9 +68658,9 @@ typedef struct hwrm_nvm_defrag_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -63665,13 +68682,163 @@ typedef struct hwrm_nvm_defrag_cmd_err { uint8_t unused_0[7]; } hwrm_nvm_defrag_cmd_err_t, *phwrm_nvm_defrag_cmd_err_t; +/******************************* + * hwrm_nvm_get_vpd_field_info * + *******************************/ + + +/* hwrm_nvm_get_vpd_field_info_input (size:192b/24B) */ + +typedef struct hwrm_nvm_get_vpd_field_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Tag ID of the requested field. To request the Product Name + * a value of [0x00, 0x82] should be used. All other fields + * would use the two byte hexadecimal value of the ASCII + * characters. The first letter of the ASCII keyword is recorded + * in tag_id[0] and the next letter in tag_id[1]. + */ + uint8_t tag_id[2]; + uint8_t unused_0[6]; +} hwrm_nvm_get_vpd_field_info_input_t, *phwrm_nvm_get_vpd_field_info_input_t; + +/* hwrm_nvm_get_vpd_field_info_output (size:2176b/272B) */ + +typedef struct hwrm_nvm_get_vpd_field_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Data retrieved from VPD field */ + uint8_t data[256]; + /* size of data retrieved in bytes */ + uint16_t data_len; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_get_vpd_field_info_output_t, *phwrm_nvm_get_vpd_field_info_output_t; + +/******************************* + * hwrm_nvm_set_vpd_field_info * + *******************************/ + + +/* hwrm_nvm_set_vpd_field_info_input (size:256b/32B) */ + +typedef struct hwrm_nvm_set_vpd_field_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This is the host address where + * VPD data value will be copied from + */ + uint64_t host_src_addr; + /* + * Tag ID of the requested field. To request the Product Name + * a value of [0x00, 0x82] should be used. All other fields + * would use the two byte hexadecimal value of the ASCII + * characters. The first letter of the ASCII keyword is recorded + * in tag_id[0] and the next letter in tag_id[1]. + */ + uint8_t tag_id[2]; + /* size of data in bytes */ + uint16_t data_len; + uint8_t unused_0[4]; +} hwrm_nvm_set_vpd_field_info_input_t, *phwrm_nvm_set_vpd_field_info_input_t; + +/* hwrm_nvm_set_vpd_field_info_output (size:128b/16B) */ + +typedef struct hwrm_nvm_set_vpd_field_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_nvm_set_vpd_field_info_output_t, *phwrm_nvm_set_vpd_field_info_output_t; + #define ROCE_SP_HSI_VERSION_MAJOR 1 #define ROCE_SP_HSI_VERSION_MINOR 8 #define ROCE_SP_HSI_VERSION_UPDATE 4 #define ROCE_SP_HSI_VERSION_STR "1.8.4" /* - * Following is the signature for ROCE_SP_HSI message field that indicates not - * applicable (All F's). Need to cast it the size of the field if needed. + * Following is the signature for ROCE_SP_HSI message field that indicates + * not applicable (All F's). Need to cast it the size of the field if + * needed. */ #define ROCE_SP_HSI_NA_SIGNATURE ((uint32_t)(-1)) @@ -63713,107 +68880,161 @@ typedef struct cmdq_base { * Create QP command allocates QP context with the specified * SQ, RQ/SRQ, CQ and other parameters. */ - #define CMDQ_BASE_OPCODE_CREATE_QP UINT32_C(0x1) + #define CMDQ_BASE_OPCODE_CREATE_QP UINT32_C(0x1) /* * Destroy QP command deletes the QP context and ceases * any further reference. */ - #define CMDQ_BASE_OPCODE_DESTROY_QP UINT32_C(0x2) + #define CMDQ_BASE_OPCODE_DESTROY_QP UINT32_C(0x2) /* * Modify QP command changes QP states and other QP specific * parameters. */ - #define CMDQ_BASE_OPCODE_MODIFY_QP UINT32_C(0x3) + #define CMDQ_BASE_OPCODE_MODIFY_QP UINT32_C(0x3) /* Query QP command retrieves info about the specified QP. */ - #define CMDQ_BASE_OPCODE_QUERY_QP UINT32_C(0x4) + #define CMDQ_BASE_OPCODE_QUERY_QP UINT32_C(0x4) /* Create SRQ command allocates a SRQ with the specified parameters. */ - #define CMDQ_BASE_OPCODE_CREATE_SRQ UINT32_C(0x5) + #define CMDQ_BASE_OPCODE_CREATE_SRQ UINT32_C(0x5) /* Destroy SRQ command deletes and flushes the specified SRQ. */ - #define CMDQ_BASE_OPCODE_DESTROY_SRQ UINT32_C(0x6) + #define CMDQ_BASE_OPCODE_DESTROY_SRQ UINT32_C(0x6) /* Query SRP command retrieves info about the specified SRQ. */ - #define CMDQ_BASE_OPCODE_QUERY_SRQ UINT32_C(0x8) + #define CMDQ_BASE_OPCODE_QUERY_SRQ UINT32_C(0x8) /* Create CQ command allocates a CQ with the specified parameters. */ - #define CMDQ_BASE_OPCODE_CREATE_CQ UINT32_C(0x9) + #define CMDQ_BASE_OPCODE_CREATE_CQ UINT32_C(0x9) /* Destroy CQ command deletes and flushes the specified CQ. */ - #define CMDQ_BASE_OPCODE_DESTROY_CQ UINT32_C(0xa) + #define CMDQ_BASE_OPCODE_DESTROY_CQ UINT32_C(0xa) /* Resize CQ command resizes the specified CQ. */ - #define CMDQ_BASE_OPCODE_RESIZE_CQ UINT32_C(0xc) + #define CMDQ_BASE_OPCODE_RESIZE_CQ UINT32_C(0xc) /* * Allocate MRW command allocates a MR/MW with the specified parameters * and returns the region's L_KEY/R_KEY */ - #define CMDQ_BASE_OPCODE_ALLOCATE_MRW UINT32_C(0xd) - /* De-allocate key command frees a MR/MW entry associated with the specified key. */ - #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY UINT32_C(0xe) + #define CMDQ_BASE_OPCODE_ALLOCATE_MRW UINT32_C(0xd) + /* + * De-allocate key command frees a MR/MW entry associated with the + * specified key. + */ + #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY UINT32_C(0xe) /* Register MR command registers memory to the specified MR. */ - #define CMDQ_BASE_OPCODE_REGISTER_MR UINT32_C(0xf) + #define CMDQ_BASE_OPCODE_REGISTER_MR UINT32_C(0xf) /* Deregister MR command de-registers memory from the specified MR. */ - #define CMDQ_BASE_OPCODE_DEREGISTER_MR UINT32_C(0x10) + #define CMDQ_BASE_OPCODE_DEREGISTER_MR UINT32_C(0x10) /* Add GID command adds a GID to the local address table. */ - #define CMDQ_BASE_OPCODE_ADD_GID UINT32_C(0x11) + #define CMDQ_BASE_OPCODE_ADD_GID UINT32_C(0x11) /* Delete GID command deletes a GID from the local address table. */ - #define CMDQ_BASE_OPCODE_DELETE_GID UINT32_C(0x12) + #define CMDQ_BASE_OPCODE_DELETE_GID UINT32_C(0x12) /* Modify GID command modifies a GID in the local address table. */ - #define CMDQ_BASE_OPCODE_MODIFY_GID UINT32_C(0x17) + #define CMDQ_BASE_OPCODE_MODIFY_GID UINT32_C(0x17) /* Query GID command queries a GID in the local address table. */ - #define CMDQ_BASE_OPCODE_QUERY_GID UINT32_C(0x18) + #define CMDQ_BASE_OPCODE_QUERY_GID UINT32_C(0x18) /* Create QP1 command allocates a QP1 only. */ - #define CMDQ_BASE_OPCODE_CREATE_QP1 UINT32_C(0x13) + #define CMDQ_BASE_OPCODE_CREATE_QP1 UINT32_C(0x13) /* Destroy QP1 command deletes and flushes the specified QP1. */ - #define CMDQ_BASE_OPCODE_DESTROY_QP1 UINT32_C(0x14) + #define CMDQ_BASE_OPCODE_DESTROY_QP1 UINT32_C(0x14) /* Create AH command allocates an AH with the specified parameters. */ - #define CMDQ_BASE_OPCODE_CREATE_AH UINT32_C(0x15) + #define CMDQ_BASE_OPCODE_CREATE_AH UINT32_C(0x15) /* Destroy AH command deletes the specified AH. */ - #define CMDQ_BASE_OPCODE_DESTROY_AH UINT32_C(0x16) + #define CMDQ_BASE_OPCODE_DESTROY_AH UINT32_C(0x16) /* * Initialize firmware command initializes the firmware with * the specified parameters. */ - #define CMDQ_BASE_OPCODE_INITIALIZE_FW UINT32_C(0x80) + #define CMDQ_BASE_OPCODE_INITIALIZE_FW UINT32_C(0x80) /* De-initialize firmware command deinitializes the firmware. */ - #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW UINT32_C(0x81) + #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW UINT32_C(0x81) /* Stop the function */ - #define CMDQ_BASE_OPCODE_STOP_FUNC UINT32_C(0x82) + #define CMDQ_BASE_OPCODE_STOP_FUNC UINT32_C(0x82) /* Query the HW capabilities for the function. */ - #define CMDQ_BASE_OPCODE_QUERY_FUNC UINT32_C(0x83) + #define CMDQ_BASE_OPCODE_QUERY_FUNC UINT32_C(0x83) /* * Set the following resources for the function: * - Max QP, CQ, MR+MW, SRQ per PF * - Max QP, CQ, MR+MW, SRQ per VF */ - #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84) - /* Read the current state of any internal resource context. Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_READ_CONTEXT UINT32_C(0x85) - /* Send a request from VF to pass a command to the PF. VF HSI is suspended until the PF returns the response */ - #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86) - /* Read VF memory (primarily to get the backchannel request blob). Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_READ_VF_MEMORY UINT32_C(0x87) - /* Write VF memory (primarily to put the backchannel response blob), and reenable VF HSI (post a CAG completion to it). Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88) - /* Extend resource (QPC, MRW, CQ, SRQ) array, after the host allocates more. Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY UINT32_C(0x89) - /* Map TC to COS. Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a) - /* Query version. */ - #define CMDQ_BASE_OPCODE_QUERY_VERSION UINT32_C(0x8b) - /* Modify congestion control. Can only be issued from a PF. */ - #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c) - /* Query congestion control. */ - #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) - /* Query RoCE statistics. */ - #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) - /* Set LAG mode. */ - #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f) - /* Modify CQ */ - #define CMDQ_BASE_OPCODE_MODIFY_CQ UINT32_C(0x90) + #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84) /* - * Query QP for a PF other than the requesting PF. Also can query for more - * than one QP. + * Read the current state of any internal resource context. Can only be + * issued from a PF. */ - #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) + #define CMDQ_BASE_OPCODE_READ_CONTEXT UINT32_C(0x85) + /* + * Send a request from VF to pass a command to the PF. VF HSI is + * suspended until the PF returns the response + */ + #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86) + /* + * Read VF memory (primarily to get the backchannel request blob). Can + * only be issued from a PF. + */ + #define CMDQ_BASE_OPCODE_READ_VF_MEMORY UINT32_C(0x87) + /* + * Write VF memory (primarily to put the backchannel response blob), + * and reenable VF HSI (post a CAG completion to it). Can only be + * issued from a PF. + */ + #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88) + /* + * Deprecated. + * Extend resource (QPC, MRW, CQ, SRQ) array, after the host allocates + * more. Can only be issued from a PF. + */ + #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRAY_DEPRECATED UINT32_C(0x89) + /* Map TC to COS. Can only be issued from a PF. */ + #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a) + /* Query version. */ + #define CMDQ_BASE_OPCODE_QUERY_VERSION UINT32_C(0x8b) + /* Modify congestion control. Can only be issued from a PF. */ + #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c) + /* Query congestion control. */ + #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) + /* Query RoCE statistics. */ + #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) + /* Set LAG mode. */ + #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f) + /* Modify CQ */ + #define CMDQ_BASE_OPCODE_MODIFY_CQ UINT32_C(0x90) + /* + * Query QP for a PF other than the requesting PF. Also can query for + * more than one QP. + */ + #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) /* Query extended RoCE statistics. */ - #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92) - #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT + #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92) + /* + * This command updates the QP context id ranges on the PF, + * to orchestrate QP context id range migration. + * This command is valid for devices that + * support the pseudo-static QP allocation feature. + */ + #define CMDQ_BASE_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93) + /* + * This command allocates a batch of the requested count of QPs + * in a sequential range. + */ + #define CMDQ_BASE_OPCODE_CREATE_QP_BATCH UINT32_C(0x94) + /* + * This command deletes a batch of the requested count of QPs. + * The starting QP ID can be specified to request a batch deletion + * of a sequential range. + */ + #define CMDQ_BASE_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95) + /* + * This command allocates an extended RoCE statistics context + * that supports periodic DMA to a host address. The extended + * statistics context id can be assigned by the driver + * via `create_qp`, `create_qp_batch`, or `modify_qp` to a specific QP, + * a subset of QPs or to all QPs of a specific function. + * These statistics can be queried via `query_roce_stats_ext_v2`. + */ + #define CMDQ_BASE_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96) + /* This command deallocates an extended RoCE statistics context. */ + #define CMDQ_BASE_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97) + /* + * This command queries extended RoCE statistics for context + * allocated via `allocate_roce_stats_ext_ctx`. + */ + #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2 /* Size of the command in 16-byte units. */ uint8_t cmd_size; /* Flags and attribs of the command. */ @@ -63858,6 +69079,390 @@ typedef struct creq_base { uint8_t reserved48[6]; } creq_base_t, *pcreq_base_t; +/* creq_resp_sb_hdr (size:64b/8B) */ + +typedef struct creq_resp_sb_hdr { + /* Command opcode. */ + uint8_t opcode; + /* Query QP command response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP UINT32_C(0x4) + /* Query SRQ command response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_SRQ UINT32_C(0x8) + /* Query GID command response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_GID UINT32_C(0x18) + /* Query info PF command response */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_FUNC UINT32_C(0x83) + /* Query version response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_VERSION UINT32_C(0x8b) + /* Query congestion control response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d) + /* Query RoCE statistics response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e) + /* Query QP extended response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) + /* Query extended RoCE statistics response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92) + /* Query extended RoCE statistics v2 response. */ + #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CREQ_RESP_SB_HDR_OPCODE_LAST CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT_V2 + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; +} creq_resp_sb_hdr_t, *pcreq_resp_sb_hdr_t; + +/* + * Structure to be used for the qp_params array of + * the `create_qp_batch` command. + */ +/* create_qp_batch_data (size:768b/96B) */ + +typedef struct create_qp_batch_data { + /* QP handle. */ + uint64_t qp_handle; + /* Create QP flags. */ + uint32_t qp_flags; + /* + * SRQ is used. + * This flag is not supported on express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_SRQ_USED UINT32_C(0x1) + /* post CQE for all SQ WQEs. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2) + /* This QP can use reserved L_Key */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4) + /* This QP can fast register physical memory */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8) + /* This QP can send variable sized WQEs. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10) + /* + * WQEs with inline data sent on this QP are able to flow + * through an optimized transmit path to lower latency. This + * transmit path is opportunistic and not guaranteed to always + * occur. + */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20) + /* + * For UD QPs the default responder CQE format is `cq_res_ud`. + * This flag specifies the `cq_res_ud_cfa` format to be used + * instead. + */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA UINT32_C(0x40) + /* + * This QP must be included in the extended RoCE statistics + * that can be queried via `query_roce_stats_ext`. + */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80) + /* This QP uses express mode. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXPRESS_MODE_ENABLED UINT32_C(0x100) + /* This QP uses the steering tag specified in the command. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_STEERING_TAG_VALID UINT32_C(0x200) + /* + * This QP can be used for RDMA Read or Atomic operations. + * This value is used to optimize metadata memory allocation + * when the device supports `internal_queue_memory` feature. + */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED UINT32_C(0x400) + /* + * This QP must be included in the extended RoCE statistics context + * specified in the field `ext_stats_ctx_id` + */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_CTX_VALID UINT32_C(0x800) + /* The schq_id field passed in by the caller is valid. */ + #define CREATE_QP_BATCH_DATA_QP_FLAGS_SCHQ_ID_VALID UINT32_C(0x1000) + #define CREATE_QP_BATCH_DATA_QP_FLAGS_LAST CREATE_QP_BATCH_DATA_QP_FLAGS_SCHQ_ID_VALID + /* Supported QP types. */ + uint8_t type; + /* Reliable Connection. */ + #define CREATE_QP_BATCH_DATA_TYPE_RC UINT32_C(0x2) + /* Unreliable Datagram. */ + #define CREATE_QP_BATCH_DATA_TYPE_UD UINT32_C(0x4) + /* Raw Ethertype. */ + #define CREATE_QP_BATCH_DATA_TYPE_RAW_ETHERTYPE UINT32_C(0x6) + /* General Services Interface on QP1 over UD. */ + #define CREATE_QP_BATCH_DATA_TYPE_GSI UINT32_C(0x7) + #define CREATE_QP_BATCH_DATA_TYPE_LAST CREATE_QP_BATCH_DATA_TYPE_GSI + uint8_t sq_pg_size_sq_lvl; + /* + * SQ PBL indirect levels. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_SQ_LVL_MASK UINT32_C(0xf) + #define CREATE_QP_BATCH_DATA_SQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_2 UINT32_C(0x2) + #define CREATE_QP_BATCH_DATA_SQ_LVL_LAST CREATE_QP_BATCH_DATA_SQ_LVL_LVL_2 + /* + * SQ page size. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_LAST CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_1G + uint8_t rq_pg_size_rq_lvl; + /* + * RQ PBL indirect levels. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_RQ_LVL_MASK UINT32_C(0xf) + #define CREATE_QP_BATCH_DATA_RQ_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ + #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_2 UINT32_C(0x2) + #define CREATE_QP_BATCH_DATA_RQ_LVL_LAST CREATE_QP_BATCH_DATA_RQ_LVL_LVL_2 + /* + * RQ page size. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_MASK UINT32_C(0xf0) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_SFT 4 + /* 4KB. */ + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4) + /* 8KB. */ + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4) + /* 64KB. */ + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4) + /* 2MB. */ + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4) + /* 8MB. */ + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4) + /* 1GB. */ + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) + #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_LAST CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_1G + uint8_t unused_0; + /* Doorbell page index. */ + uint32_t dpi; + /* + * When the SQ is configured to use variable-size WQE, 'sq_size' + * denotes the SQ size with a unit of 16B. When the SQ is configured + * to use fixed-size WQE, 'sq_size' denotes the max number of SQ WQEs. + */ + uint32_t sq_size; + /* Max number of RQ wqes. */ + uint32_t rq_size; + uint16_t sq_fwo_sq_sge; + /* + * Max send SGEs per SWQE. This is only applicable to fixed-size + * WQE support. On variable-size WQE, this is ignored. + */ + #define CREATE_QP_BATCH_DATA_SQ_SGE_MASK UINT32_C(0xf) + #define CREATE_QP_BATCH_DATA_SQ_SGE_SFT 0 + /* + * Offset of First WQE in the first SQ page, in 128 byte units. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_SQ_FWO_MASK UINT32_C(0xfff0) + #define CREATE_QP_BATCH_DATA_SQ_FWO_SFT 4 + uint16_t rq_fwo_rq_sge; + /* + * Max recv SGEs per RWQE. + * On chips with variable-size WQE support, a value of zero implies + * 30 SGEs. + */ + #define CREATE_QP_BATCH_DATA_RQ_SGE_MASK UINT32_C(0xf) + #define CREATE_QP_BATCH_DATA_RQ_SGE_SFT 0 + /* + * Offset of First WQE in the first RQ page, in 128 byte units. + * This field is ignored for express mode QPs. + */ + #define CREATE_QP_BATCH_DATA_RQ_FWO_MASK UINT32_C(0xfff0) + #define CREATE_QP_BATCH_DATA_RQ_FWO_SFT 4 + /* Send CQ context id. */ + uint32_t scq_cid; + /* Receive CQ context id. */ + uint32_t rcq_cid; + /* SRQ context id. */ + uint32_t srq_cid; + /* Protection domain id. */ + uint32_t pd_id; + /* + * SQ PBL physical address. + * This field is ignored for express mode QPs. + */ + uint64_t sq_pbl; + /* + * RQ PBL physical address. + * This field is ignored for express mode QPs. + */ + uint64_t rq_pbl; + /* + * IRRQ address. This field is ignored on devices that + * support the `internal_queue_memory` feature. + */ + uint64_t irrq_addr; + /* + * ORRQ address. This field is ignored on devices that + * support the `internal_queue_memory` feature. + */ + uint64_t orrq_addr; + /* + * xid to use for the non-QP1 QP. + * The requested xid must be within the valid range + * of the predetermined assignment scheme of the + * pseudo static QP allocation feature. The valid range + * for the data QPs is determined by the start_qid and + * max_qp fields of query_func response. When the value is zero, + * firmware will automatically choose an xid from its free pool. + * QP1 allocation, indicated by specifying `type` field as gsi, + * must specify a request_xid as zero. + * This field is ignored on devices that do not support + * the pseudo static QP allocation feature. + */ + uint32_t request_xid; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + /* + * This value is used to optimize metadata memory allocation when + * the device supports `internal_queue_memory` feature. + * When the SQ is configured to use variable-size WQEs, the SQ size is + * only specified in units of 16 Bytes. This value hints the max number + * of WQEs that would ever be present on the SQ. + */ + uint16_t sq_max_num_wqes; + /* Extended RoCE statistics context id. */ + uint32_t ext_stats_ctx_id; + /* + * Identifies the new scheduling queue to associate with + * the RoCE QP. A value of zero indicates that the QP is being + * created with the default scheduling queue. Can only be specified + * by the PF driver. VFs get assigned a scheduling queue based on PF + * configuration (via HWRM_FUNC_CFG). Specified scheduling queue id is + * allocated by firmware (via HWRM_SCHQ_ALLOC) when the device supports + * the `scheduling queue` feature. + */ + uint16_t schq_id; + uint16_t reserved16; +} create_qp_batch_data_t, *pcreate_qp_batch_data_t; + +/* Periodic extended RoCE statistics context DMA to host. */ +/* roce_stats_ext_ctx (size:1856b/232B) */ + +typedef struct roce_stats_ext_ctx { + /* Number of transmitted Atomic request packets without errors. */ + uint64_t tx_atomic_req_pkts; + /* Number of transmitted Read request packets without errors. */ + uint64_t tx_read_req_pkts; + /* Number of transmitted Read response packets without errors. */ + uint64_t tx_read_res_pkts; + /* Number of transmitted Write request packets without errors. */ + uint64_t tx_write_req_pkts; + /* Number of transmitted RC Send packets without errors. */ + uint64_t tx_rc_send_req_pkts; + /* + * Number of transmitted UD Send (including QP1) packets + * without errors. + */ + uint64_t tx_ud_send_req_pkts; + /* Number of transmitted CNPs. Includes DCN_CNPs. */ + uint64_t tx_cnp_pkts; + /* + * Number of transmitted RoCE packets. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t tx_roce_pkts; + /* + * Number of transmitted RoCE header and payload bytes. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t tx_roce_bytes; + /* + * Number of drops that occurred to lack of buffers. + * This count includes RC sends, RC writes with immediate, + * UD sends, RawEth, and QP1 packets dropped due to lack of buffers. + */ + uint64_t rx_out_of_buffer_pkts; + /* Number of packets that were received out of sequence. */ + uint64_t rx_out_of_sequence_pkts; + /* + * Number of duplicate read/atomic requests resulting in responder + * hardware retransmission. + */ + uint64_t dup_req; + /* + * Number of missing response packets resulting in hardware + * retransmission. + */ + uint64_t missing_resp; + /* + * Number of sequence error NAKs received resulting in hardware + * retransmission. + */ + uint64_t seq_err_naks_rcvd; + /* Number of RNR NAKs received resulting in hardware retransmission. */ + uint64_t rnr_naks_rcvd; + /* Number of timeouts resulting in hardware retransmission. */ + uint64_t to_retransmits; + /* Number of received Atomic request packets without errors. */ + uint64_t rx_atomic_req_pkts; + /* Number of received Read request packets without errors. */ + uint64_t rx_read_req_pkts; + /* Number of received Read response packets without errors. */ + uint64_t rx_read_res_pkts; + /* Number of received Write request packets without errors. */ + uint64_t rx_write_req_pkts; + /* Number of received RC Send packets without errors. */ + uint64_t rx_rc_send_pkts; + /* Number of received UD Send packets without errors. */ + uint64_t rx_ud_send_pkts; + /* Number of received DCN payload cut packets. */ + uint64_t rx_dcn_payload_cut; + /* Number of received ECN-marked packets. */ + uint64_t rx_ecn_marked_pkts; + /* Number of received CNP packets. Includes DCN_CNPs. */ + uint64_t rx_cnp_pkts; + /* + * Number of received RoCE packets including RoCE packets with errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_pkts; + /* + * Number of received RoCE header and payload bytes including RoCE + * packets with errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_bytes; + /* + * Number of received RoCE packets without errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_good_pkts; + /* + * Number of received RoCE header and payload bytes without errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_good_bytes; +} roce_stats_ext_ctx_t, *proce_stats_ext_ctx_t; + /***************** * query_version * *****************/ @@ -63940,7 +69545,7 @@ typedef struct creq_query_version_resp { *****************/ -/* cmdq_initialize_fw (size:896b/112B) */ +/* cmdq_initialize_fw (size:1024b/128B) */ typedef struct cmdq_initialize_fw { /* Command opcode. */ @@ -63965,6 +69570,15 @@ typedef struct cmdq_initialize_fw { * feature is supported. */ #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED UINT32_C(0x2) + /* When set, the driver version is provided. */ + #define CMDQ_INITIALIZE_FW_FLAGS_DRV_VERSION UINT32_C(0x4) + /* When set, driver supports optimizing Modify QP operation. */ + #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED UINT32_C(0x8) + /* + * When set, the VF RoCE resources will be managed by the L2 + * driver via func_cfg. + */ + #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT UINT32_C(0x10) /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; /* Size of the response buffer in 16-byte units. */ @@ -63980,7 +69594,10 @@ typedef struct cmdq_initialize_fw { #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 /* QPC page size. */ @@ -64007,7 +69624,10 @@ typedef struct cmdq_initialize_fw { #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 /* MRW page size. */ @@ -64034,7 +69654,10 @@ typedef struct cmdq_initialize_fw { #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 /* SRQ page size. */ @@ -64061,7 +69684,10 @@ typedef struct cmdq_initialize_fw { #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 /* CQ page size. */ @@ -64088,7 +69714,10 @@ typedef struct cmdq_initialize_fw { #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 /* TQM page size. */ @@ -64115,7 +69744,10 @@ typedef struct cmdq_initialize_fw { #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 /* TIM page size. */ @@ -64135,7 +69767,10 @@ typedef struct cmdq_initialize_fw { #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G uint16_t log2_dbr_pg_size; - /* Log base 2 of DBR page size - 12. 0 for 4KB. HW supported values are enumerated below. */ + /* + * Log base 2 of DBR page size - 12. 0 for 4KB. HW supported values + * are enumerated below. + */ #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK UINT32_C(0xf) #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0 /* 4KB. */ @@ -64186,15 +69821,30 @@ typedef struct cmdq_initialize_fw { uint64_t tqm_page_dir; /* TIM page directory. */ uint64_t tim_page_dir; - /* Number of QPs. */ + /* + * Number of QPs. This field is ignored when the backing store HWRM's + * are used. + */ uint32_t number_of_qp; - /* Number of MRWs. */ + /* + * Number of MRWs. This field is ignored when the backing store HWRM's + * are used. + */ uint32_t number_of_mrw; - /* Number of SRQs. */ + /* + * Number of SRQs. This field is ignored when the backing store HWRM's + * are used. + */ uint32_t number_of_srq; - /* Number of CQs. */ + /* + * Number of CQs. This field is ignored when the backing store HWRM's + * are used. + */ uint32_t number_of_cq; - /* Number of QPs per VF. */ + /* + * Number of QPs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ uint32_t max_qp_per_vf; /* * If the MR/AV split reservation flag is not set, then this field @@ -64209,16 +69859,44 @@ typedef struct cmdq_initialize_fw { * `max_av_per_vf`. The granularity of these values is defined by * the `mrav_num_entries_unit` field returned by the * `backing_store_qcaps` command. + * + * This field must be set to zero when the flag, l2_vf_resource_mgmt, + * is set and RoCE SRIOV is enabled. */ uint32_t max_mrw_per_vf; - /* Number of SRQs per VF. */ + /* + * Number of SRQs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ uint32_t max_srq_per_vf; - /* Number of CQs per VF. */ + /* + * Number of CQs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ uint32_t max_cq_per_vf; - /* Number of GIDs per VF. */ + /* + * Number of GIDs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ uint32_t max_gid_per_vf; /* Statistics context index for this function. */ uint32_t stat_ctx_id; + /* The driver HSI major version number. */ + uint8_t drv_hsi_ver_maj; + /* The driver HSI minor version number. */ + uint8_t drv_hsi_ver_min; + /* The driver HSI update version number. */ + uint8_t drv_hsi_ver_upd; + /* This is the 40bit unused. */ + uint8_t unused40[5]; + /* The driver build major version number. */ + uint16_t drv_build_ver_maj; + /* The driver build minor version number. */ + uint16_t drv_build_ver_min; + /* The driver build update version number. */ + uint16_t drv_build_ver_upd; + /* The driver build patch version number. */ + uint16_t drv_build_ver_patch; } cmdq_initialize_fw_t, *pcmdq_initialize_fw_t; /* creq_initialize_fw_resp (size:128b/16B) */ @@ -64324,7 +70002,7 @@ typedef struct creq_deinitialize_fw_resp { *************/ -/* cmdq_create_qp (size:768b/96B) */ +/* cmdq_create_qp (size:896b/112B) */ typedef struct cmdq_create_qp { /* Command opcode. */ @@ -64350,7 +70028,10 @@ typedef struct cmdq_create_qp { uint64_t qp_handle; /* Create QP flags. */ uint32_t qp_flags; - /* SRQ is used. */ + /* + * SRQ is used. + * This flag is not supported on express mode QPs. + */ #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED UINT32_C(0x1) /* post CQE for all SQ WQEs. */ #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2) @@ -64378,7 +70059,24 @@ typedef struct cmdq_create_qp { * that can be queried via `query_roce_stats_ext`. */ #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80) - #define CMDQ_CREATE_QP_QP_FLAGS_LAST CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED + /* This QP uses express mode. */ + #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED UINT32_C(0x100) + /* This QP uses the steering tag specified in the command. */ + #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID UINT32_C(0x200) + /* + * This QP can be used for RDMA Read or Atomic operations. + * This value is used to optimize metadata memory allocation + * when the device supports `internal_queue_memory` feature. + */ + #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED UINT32_C(0x400) + /* + * This QP must be included in the extended RoCE statistics context + * specified in the field `ext_stats_ctx_id` + */ + #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_CTX_VALID UINT32_C(0x800) + /* The schq_id field passed in by the caller is valid. */ + #define CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID UINT32_C(0x1000) + #define CMDQ_CREATE_QP_QP_FLAGS_LAST CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID /* Supported QP types. */ uint8_t type; /* Reliable Connection. */ @@ -64391,17 +70089,26 @@ typedef struct cmdq_create_qp { #define CMDQ_CREATE_QP_TYPE_GSI UINT32_C(0x7) #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI uint8_t sq_pg_size_sq_lvl; - /* SQ PBL indirect levels. */ + /* + * SQ PBL indirect levels. + * This field is ignored for express mode QPs. + */ #define CMDQ_CREATE_QP_SQ_LVL_MASK UINT32_C(0xf) #define CMDQ_CREATE_QP_SQ_LVL_SFT 0 /* PBL pointer is physical start address. */ #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2 - /* SQ page size. */ + /* + * SQ page size. + * This field is ignored for express mode QPs. + */ #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK UINT32_C(0xf0) #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4 /* 4KB. */ @@ -64418,17 +70125,26 @@ typedef struct cmdq_create_qp { #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4) #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G uint8_t rq_pg_size_rq_lvl; - /* RQ PBL indirect levels. */ + /* + * RQ PBL indirect levels. + * This field is ignored for express mode QPs. + */ #define CMDQ_CREATE_QP_RQ_LVL_MASK UINT32_C(0xf) #define CMDQ_CREATE_QP_RQ_LVL_SFT 0 /* PBL pointer is physical start address. */ #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to + * PTE tables. + */ #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2 - /* RQ page size. */ + /* + * RQ page size. + * This field is ignored for express mode QPs. + */ #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK UINT32_C(0xf0) #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4 /* 4KB. */ @@ -64447,25 +70163,39 @@ typedef struct cmdq_create_qp { uint8_t unused_0; /* Doorbell page index. */ uint32_t dpi; - /* Max number of SQ wqes. */ + /* + * When the SQ is configured to use variable-size WQE, 'sq_size' + * denotes the SQ size with a unit of 16B. When the SQ is configured + * to use fixed-size WQE, 'sq_size' denotes the max number of SQ WQEs. + */ uint32_t sq_size; /* Max number of RQ wqes. */ uint32_t rq_size; uint16_t sq_fwo_sq_sge; - /* Max send SGEs per SWQE. */ + /* + * Max send SGEs per SWQE. This is only applicable to fixed-size + * WQE support. On variable-size WQE, this is ignored. + */ #define CMDQ_CREATE_QP_SQ_SGE_MASK UINT32_C(0xf) #define CMDQ_CREATE_QP_SQ_SGE_SFT 0 - /* Offset of First WQE in the first SQ page, in 128 byte units */ + /* + * Offset of First WQE in the first SQ page, in 128 byte units. + * This field is ignored for express mode QPs. + */ #define CMDQ_CREATE_QP_SQ_FWO_MASK UINT32_C(0xfff0) #define CMDQ_CREATE_QP_SQ_FWO_SFT 4 uint16_t rq_fwo_rq_sge; /* * Max recv SGEs per RWQE. - * On chips with variable-size WQE support, a value of zero implies 30 SGEs. + * On chips with variable-size WQE support, a value of zero implies + * 30 SGEs. */ #define CMDQ_CREATE_QP_RQ_SGE_MASK UINT32_C(0xf) #define CMDQ_CREATE_QP_RQ_SGE_SFT 0 - /* Offset of First WQE in the first RQ page, in 128 byte units */ + /* + * Offset of First WQE in the first RQ page, in 128 byte units. + * This field is ignored for express mode QPs. + */ #define CMDQ_CREATE_QP_RQ_FWO_MASK UINT32_C(0xfff0) #define CMDQ_CREATE_QP_RQ_FWO_SFT 4 /* Send CQ context id. */ @@ -64476,14 +70206,63 @@ typedef struct cmdq_create_qp { uint32_t srq_cid; /* Protection domain id. */ uint32_t pd_id; - /* SQ PBL physical address. */ + /* + * SQ PBL physical address. + * This field is ignored for express mode QPs. + */ uint64_t sq_pbl; - /* RQ PBL physical address. */ + /* + * RQ PBL physical address. + * This field is ignored for express mode QPs. + */ uint64_t rq_pbl; - /* IRRQ address. */ + /* + * IRRQ address. This field is ignored on devices that + * support the `internal_queue_memory` feature. + */ uint64_t irrq_addr; - /* ORRQ address. */ + /* + * ORRQ address. This field is ignored on devices that + * support the `internal_queue_memory` feature. + */ uint64_t orrq_addr; + /* + * xid to use for the non-QP1 QP. + * The requested xid must be within the valid range + * of the predetermined assignment scheme of the + * pseudo static QP allocation feature. The valid range + * for the data QPs is determined by the start_qid and + * max_qp fields of query_func response. When the value is zero, + * firmware will automatically choose an xid from its free pool. + * QP1 allocation, indicated by specifying `type` field as gsi, + * must specify a request_xid as zero. + * This field is ignored on devices that do not support + * the pseudo static QP allocation feature. + */ + uint32_t request_xid; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + /* + * This value is used to optimize metadata memory allocation when + * the device supports `internal_queue_memory` feature. + * When the SQ is configured to use variable-size WQEs, the SQ size is + * only specified in units of 16 Bytes. This value hints the max number + * of WQEs that would ever be present on the SQ. + */ + uint16_t sq_max_num_wqes; + /* Extended RoCE statistics context id. */ + uint32_t ext_stats_ctx_id; + /* + * Identifies the new scheduling queue to associate with + * the RoCE QP. A value of zero indicates that the QP is being + * created with the default scheduling queue. Can only be specified + * by the PF driver. VFs get assigned a scheduling queue based on PF + * configuration (via HWRM_FUNC_CFG). Specified scheduling queue id is + * allocated by firmware (via HWRM_SCHQ_ALLOC) when the device supports + * the `scheduling queue` feature. + */ + uint16_t schq_id; + uint16_t reserved16; } cmdq_create_qp_t, *pcmdq_create_qp_t; /* creq_create_qp_resp (size:128b/16B) */ @@ -64602,7 +70381,7 @@ typedef struct creq_destroy_qp_resp { *************/ -/* cmdq_modify_qp (size:1024b/128B) */ +/* cmdq_modify_qp (size:1152b/144B) */ typedef struct cmdq_modify_qp { /* Command opcode. */ @@ -64617,11 +70396,32 @@ typedef struct cmdq_modify_qp { uint8_t cmd_size; /* Flags and attribs of the command. */ uint16_t flags; + /* + * This field, used by firmware for optimizing Modify QP operation, + * must be set when the driver has indicated support for the + * optimize_modify_qp_supported feature in cmdq_initialize_fw and + * when QP Type RC is configured to use SRQ. + */ + #define CMDQ_MODIFY_QP_FLAGS_SRQ_USED UINT32_C(0x1) /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; /* Size of the response buffer in 16-byte units. */ uint8_t resp_size; - uint8_t reserved8; + /* + * This field, used by firmware for optimizing Modify QP operation, + * must be set when the driver has indicated support for the + * optimize_modify_qp_supported feature in cmdq_initialize_fw. + */ + uint8_t qp_type; + /* Reliable Connection. */ + #define CMDQ_MODIFY_QP_QP_TYPE_RC UINT32_C(0x2) + /* Unreliable Datagram. */ + #define CMDQ_MODIFY_QP_QP_TYPE_UD UINT32_C(0x4) + /* Raw Ethertype. */ + #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6) + /* General Services Interface on QP1 over UD. */ + #define CMDQ_MODIFY_QP_QP_TYPE_GSI UINT32_C(0x7) + #define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI /* Host address of the response. */ uint64_t resp_addr; /* Modify mask signifies the field that is requesting the change. */ @@ -64735,7 +70535,10 @@ typedef struct cmdq_modify_qp { #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE UINT32_C(0x2) /* Remote read access. */ #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ UINT32_C(0x4) - /* Remote atomic access. */ + /* + * Remote atomic access. Applicable to devices that support + * Atomic operations. + */ #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC UINT32_C(0x8) /* P_KEY. */ uint16_t pkey; @@ -64816,7 +70619,7 @@ typedef struct cmdq_modify_qp { uint16_t sq_sge; /* Max recv SGEs per RWQE. */ uint16_t rq_sge; - /* Max inline data length (upto 120 bytes). */ + /* Max inline data length (up to 120 bytes). */ uint32_t max_inline_data; /* Destination QP id. */ uint32_t dest_qp_id; @@ -64837,6 +70640,29 @@ typedef struct cmdq_modify_qp { uint64_t irrq_addr; /* ORRQ address. */ uint64_t orrq_addr; + /* + * Extended Modify mask signifies the field that is requesting the + * change. + */ + uint32_t ext_modify_mask; + /* Extended RoCE statistics context id change */ + #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX UINT32_C(0x1) + /* The schq_id field is valid */ + #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID UINT32_C(0x2) + /* Extended RoCE statistics context id. */ + uint32_t ext_stats_ctx_id; + /* + * Identifies the new scheduling queue to associate to the RoCE QP. + * A value of zero indicates that the QP is being modified to use + * the default scheduling queue. Specified scheduling queue id is + * allocated by firmware (via HWRM_SCHQ_ALLOC) when the device supports + * the `scheduling queue` feature. + */ + uint16_t schq_id; + /* unused_0 is 16 b */ + uint16_t unused_0; + /* reserved32 is 32 b */ + uint32_t reserved32; } cmdq_modify_qp_t, *pcmdq_modify_qp_t; /* creq_modify_qp_resp (size:128b/16B) */ @@ -65021,7 +70847,12 @@ typedef struct creq_query_qp_resp_sb { uint16_t pkey; /* Q_KEY. */ uint32_t qkey; - uint32_t reserved32; + /* + * UDP source port used in RoCEv2 packets. Valid only when + * change_udp_src_port_wqe_supported feature is advertised. + */ + uint16_t udp_src_port; + uint16_t reserved16; /* Destination GID. */ uint32_t dgid[4]; /* Flow label. */ @@ -65088,7 +70919,7 @@ typedef struct creq_query_qp_resp_sb { uint16_t sq_sge; /* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */ uint16_t rq_sge; - /* Max inline data length (upto 120 bytes). */ + /* Max inline data length (up to 120 bytes). */ uint32_t max_inline_data; /* Destination QP id. */ uint32_t dest_qp_id; @@ -65121,8 +70952,8 @@ typedef struct cmdq_query_qp_extend { /* Command opcode. */ uint8_t opcode; /* - * Query QP extend command retrieves info about multiple QPs associated - * with a specific PF. + * Query QP extend command retrieves info about multiple QPs + * associated with a specific PF. */ #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91) #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND @@ -65134,7 +70965,10 @@ typedef struct cmdq_query_qp_extend { uint16_t cookie; /* Size of the response buffer in 16-byte units. */ uint8_t resp_size; - /* Number of QPs for which FW needs to query and provide info back to host. */ + /* + * Number of QPs for which FW needs to query and provide info back to + * host. + */ uint8_t num_qps; /* Host address of the response. */ uint64_t resp_addr; @@ -65149,8 +70983,8 @@ typedef struct cmdq_query_qp_extend { /* When set the vf_num is valid. */ #define CMDQ_QUERY_QP_EXTEND_VF_VALID UINT32_C(0x1000000) /* - * This is the current index where firmware left off for query qp. Driver - * will pass this back in the next query_qp_extend command. + * This is the current index where firmware left off for query qp. + * Driver will pass this back in the next query_qp_extend command. */ uint32_t current_index; } cmdq_query_qp_extend_t, *pcmdq_query_qp_extend_t; @@ -65191,8 +71025,8 @@ typedef struct creq_query_qp_extend_resp { #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND uint16_t reserved16; /* - * This is the current index where firmware left off for query qp. Driver - * will pass this back in the next query_qp_extend command. + * This is the current index where firmware left off for query qp. + * Driver will pass this back in the next query_qp_extend command. */ uint32_t current_index; } creq_query_qp_extend_resp_t, *pcreq_query_qp_extend_resp_t; @@ -65262,7 +71096,7 @@ typedef struct creq_query_qp_extend_resp_sb { uint32_t dest_qp_id; /* Statistic collection ID allocated for this QP. */ uint8_t stat_collection_id; - uint8_t reservred_8; + uint8_t reserved2_8; uint16_t reserved_16; } creq_query_qp_extend_resp_sb_t, *pcreq_query_qp_extend_resp_sb_t; @@ -65391,7 +71225,7 @@ typedef struct creq_query_qp_extend_resp_sb_tlv { uint32_t dest_qp_id; /* Statistic collection ID allocated for this QP. */ uint8_t stat_collection_id; - uint8_t reservred_8; + uint8_t reserved2_8; uint16_t reserved_16; } creq_query_qp_extend_resp_sb_tlv_t, *pcreq_query_qp_extend_resp_sb_tlv_t; @@ -65400,7 +71234,7 @@ typedef struct creq_query_qp_extend_resp_sb_tlv { **************/ -/* cmdq_create_srq (size:384b/48B) */ +/* cmdq_create_srq (size:512b/64B) */ typedef struct cmdq_create_srq { /* Command opcode. */ @@ -65412,6 +71246,8 @@ typedef struct cmdq_create_srq { uint8_t cmd_size; /* Flags and attribs of the command. */ uint16_t flags; + /* This SRQ uses the steering tag specified in the command. */ + #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID UINT32_C(0x1) /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; /* Size of the response buffer in 16-byte units. */ @@ -65429,7 +71265,10 @@ typedef struct cmdq_create_srq { #define CMDQ_CREATE_SRQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_CREATE_SRQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_CREATE_SRQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2 /* page size. */ @@ -65460,14 +71299,27 @@ typedef struct cmdq_create_srq { #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12 /* Max number of SRQ wqes. */ uint16_t srq_size; - /* Offset of first WQE in the first page of SRQ, in 128 byte units */ uint16_t srq_fwo; + /* Offset of first WQE in the first page of SRQ, in 128 byte units */ + #define CMDQ_CREATE_SRQ_SRQ_FWO_MASK UINT32_C(0xfff) + #define CMDQ_CREATE_SRQ_SRQ_FWO_SFT 0 + /* + * Max SGEs per SRQ WQE. This field is enabled if flag, + * create_srq_sge_supported, is set in query_func response. + */ + #define CMDQ_CREATE_SRQ_SRQ_SGE_MASK UINT32_C(0xf000) + #define CMDQ_CREATE_SRQ_SRQ_SGE_SFT 12 /* Doorbell page index. */ uint32_t dpi; /* Protection domain id. */ uint32_t pd_id; /* RQ PBL physical address. */ uint64_t pbl; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + uint8_t reserved48[6]; + /* reserved64 is 64 b */ + uint64_t reserved64; } cmdq_create_srq_t, *pcmdq_create_srq_t; /* creq_create_srq_resp (size:128b/16B) */ @@ -65573,7 +71425,10 @@ typedef struct creq_destroy_srq_resp { uint16_t enable_for_arm[3]; #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK UINT32_C(0xffff) #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0 - /* Set to 1 if this SRQ is allowed to be armed for threshold async event */ + /* + * Set to 1 if this SRQ is allowed to be armed for threshold async + * event + */ #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK UINT32_C(0x30000) #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16 } creq_destroy_srq_resp_t, *pcreq_destroy_srq_resp_t; @@ -65676,7 +71531,7 @@ typedef struct creq_query_srq_resp_sb { *************/ -/* cmdq_create_cq (size:384b/48B) */ +/* cmdq_create_cq (size:512b/64B) */ typedef struct cmdq_create_cq { /* Command opcode. */ @@ -65699,6 +71554,25 @@ typedef struct cmdq_create_cq { * by the driver when HW based doorbell recovery is enabled. */ #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1) + /* This CQ uses the steering tag specified in the command. */ + #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID UINT32_C(0x2) + /* + * This CQ uses the infinite CQ mode. + * In the infinite CQ mode, all CQEs are written to the same + * address. Note that this mode implies a HW client is + * handling each entry instantly and avoiding overwrites. + * The following limitations apply when this mode is enabled: + * -cq_size field must be 1 + * -disable_cq_overflow_detection flag must be true. + * -the CQ will never be armed. + * -the consumer index of CQ will never be changed + */ + #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE UINT32_C(0x4) + /* + * This CQ uses coalescing data specified in the command. + * This feature is not supported if infinite_cq_mode is also enabled. + */ + #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID UINT32_C(0x8) /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; /* Size of the response buffer in 16-byte units. */ @@ -65716,7 +71590,10 @@ typedef struct cmdq_create_cq { #define CMDQ_CREATE_CQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_CREATE_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_CREATE_CQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2 /* page size. */ @@ -65751,6 +71628,45 @@ typedef struct cmdq_create_cq { uint32_t cq_size; /* CQ PBL physical address. */ uint64_t pbl; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + uint8_t reserved16[2]; + uint32_t coalescing; + /* + * Buffer Max time before flushing buffer (units of 1us). This + * specifies the maximum time before completion buffers are + * flushed out to host memory even if the number of coalesced + * buffers is less than the threshold. buf_maxtime is 9 bits. + */ + #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK UINT32_C(0x1ff) + #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0 + /* + * This specifies the number of buffers coalesced before sending + * to memory during normal operation. Buffer unit is 16B + * completions. normal_maxbuf is 5 bits. + */ + #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK UINT32_C(0x3e00) + #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_SFT 9 + /* + * This specifies the number of buffers coalesced before sending + * to memory when the interrupt is masked. Buffer unit is 16B + * completions. during_maxbuf is 5 bits. + */ + #define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK UINT32_C(0x7c000) + #define CMDQ_CREATE_CQ_DURING_MAXBUF_SFT 14 + /* + * This field is used to enable ring for global idle mode interrupt + * generation. This mode will generate a notification (interrupt) + * if armed when only one completion has been generated if the chip + * is globally idle as determined by the device. + * enable_ring_idle_mode is 1 bit. + */ + #define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE UINT32_C(0x80000) + /* unused12 is 12 b */ + #define CMDQ_CREATE_CQ_UNUSED12_MASK UINT32_C(0xfff00000) + #define CMDQ_CREATE_CQ_UNUSED12_SFT 20 + /* reserved64 is 64 b */ + uint64_t reserved64; } cmdq_create_cq_t, *pcmdq_create_cq_t; /* creq_create_cq_resp (size:128b/16B) */ @@ -65863,8 +71779,9 @@ typedef struct creq_destroy_cq_resp { #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK UINT32_C(0x3) #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0 /* - * The total number of CNQ events for the CQ, incremented on each CNQ event for the CQ - * (including firmware-generated CQ error notification). + * The total number of CNQ events for the CQ, incremented on each CNQ + * event for the CQ (including firmware-generated CQ error + * notification). */ uint16_t total_cnq_events; uint16_t reserved16; @@ -65904,7 +71821,10 @@ typedef struct cmdq_resize_cq { #define CMDQ_RESIZE_CQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_RESIZE_CQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_RESIZE_CQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2 /* page size. */ @@ -66090,8 +72010,8 @@ typedef struct cmdq_allocate_mrw { /* Command opcode. */ uint8_t opcode; /* - * Allocate MRW command allocates a MR/MW with the specified parameters - * and returns the region's L_KEY/R_KEY + * Allocate MRW command allocates a MR/MW with the specified + * parameters and returns the region's L_KEY/R_KEY */ #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW UINT32_C(0xd) #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW @@ -66113,25 +72033,30 @@ typedef struct cmdq_allocate_mrw { #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK UINT32_C(0xf) #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0 /* Allocate Memory Region */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR UINT32_C(0x0) + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR UINT32_C(0x0) /* Allocate Physical Memory Region */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR UINT32_C(0x1) + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR UINT32_C(0x1) /* Allocate Memory Window (type 1) */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2) + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2) /* Allocate Memory Window (type 2A) */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3) + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3) /* Allocate Memory Window (type 2B) */ - #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4) + #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4) #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B - /* unused4 is 4 b */ - #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK UINT32_C(0xf0) - #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 4 + /* + * This Memory Region / Memory Window uses the + * steering tag specified in the command. + */ + #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID UINT32_C(0x10) + /* unused3 is 3 b */ + #define CMDQ_ALLOCATE_MRW_UNUSED3_MASK UINT32_C(0xe0) + #define CMDQ_ALLOCATE_MRW_UNUSED3_SFT 5 /* Access flags. */ uint8_t access; /* Consumer owns the key */ #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY UINT32_C(0x20) - /* unused16 is 16 b */ - uint16_t unused16; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; /* Protection domain id. */ uint32_t pd_id; } cmdq_allocate_mrw_t, *pcmdq_allocate_mrw_t; @@ -66183,7 +72108,10 @@ typedef struct creq_allocate_mrw_resp { typedef struct cmdq_deallocate_key { /* Command opcode. */ uint8_t opcode; - /* De-allocate key command frees a MR/MW entry associated with the specified key. */ + /* + * De-allocate key command frees a MR/MW entry associated with the + * specified key. + */ #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY UINT32_C(0xe) #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY /* Size of the command in 16-byte units. */ @@ -66257,12 +72185,16 @@ typedef struct creq_deallocate_key_resp { #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY uint16_t reserved16; /* - * This is advisory data to facilitate eventual destruction of lingering memory regions in Windows. - * For memory window, it contains non-zero HWID of a region this window was bound to (without the 8-bit key portion). - * The host may check if the region is lingering in destroyed state and try to destroy it now. - * For memory region, if deallocation fails because there are windows bound to this region, this field will contain - * approximate number of those windows. This number is read from the context right before the - * deregistration is attempted and can potentially be slightly different from the current number. + * This is advisory data to facilitate eventual destruction of + * lingering memory regions in Windows. For memory window, it contains + * non-zero HWID of a region this window was bound to (without the + * 8-bit key portion). The host may check if the region is lingering in + * destroyed state and try to destroy it now. For memory region, if + * deallocation fails because there are windows bound to this region, + * this field will contain approximate number of those windows. This + * number is read from the context right before the deregistration is + * attempted and can potentially be slightly different from the current + * number. */ uint32_t bound_window_info; } creq_deallocate_key_resp_t, *pcreq_deallocate_key_resp_t; @@ -66272,7 +72204,7 @@ typedef struct creq_deallocate_key_resp { ***************/ -/* cmdq_register_mr (size:384b/48B) */ +/* cmdq_register_mr (size:512b/64B) */ typedef struct cmdq_register_mr { /* Command opcode. */ @@ -66290,7 +72222,15 @@ typedef struct cmdq_register_mr { * the `key` field doesn't hold a valid L_KEY and is instead * overloaded to hold the Protection Domain ID `pd_id`. */ - #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR UINT32_C(0x1) + #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR UINT32_C(0x1) + /* + * This MR uses the steering tag specified in the command. + * This flag can only be enabled when the command is used + * to allocate a new MR first. + */ + #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID UINT32_C(0x2) + /* When set, enable per MR relaxed ordering support. */ + #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO UINT32_C(0x4) /* Driver supplied handle to associate the command and the response. */ uint16_t cookie; /* Size of the response buffer in 16-byte units. */ @@ -66306,10 +72246,16 @@ typedef struct cmdq_register_mr { #define CMDQ_REGISTER_MR_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_REGISTER_MR_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_REGISTER_MR_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2 - /* Log base 2 of page size; 12 is the minimum for 4KB. HW supported values are enumerated below. */ + /* + * Log base 2 of page size; 12 is the minimum for 4KB. HW supported + * values are enumerated below. + */ #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK UINT32_C(0x7c) #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2 /* 4KB. */ @@ -66346,7 +72292,10 @@ typedef struct cmdq_register_mr { /* Indicate Zero Based Virtual Address (ZBVA). */ #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED UINT32_C(0x20) uint16_t log2_pbl_pg_size; - /* Log base 2 of PBL page size; 12 is the minimum for 4KB. HW supported values are enumerated below */ + /* + * Log base 2 of PBL page size; 12 is the minimum for 4KB. HW + * supported values are enumerated below + */ #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK UINT32_C(0x1f) #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0 /* 4KB. */ @@ -66382,6 +72331,11 @@ typedef struct cmdq_register_mr { uint64_t va; /* Size of the MR. */ uint64_t mr_size; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + uint8_t reserved48[6]; + /* reserved64 is 64 b */ + uint64_t reserved64; } cmdq_register_mr_t, *pcmdq_register_mr_t; /* creq_register_mr_resp (size:128b/16B) */ @@ -66486,9 +72440,11 @@ typedef struct creq_deregister_mr_resp { #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR uint16_t reserved16; /* - * If deregister fails because there are windows bound to this region, this field will contain - * approximate number of those windows. This number is read from the context right before the - * deregistration is attempted and can potentially be slightly different from the current number. + * If deregister fails because there are windows bound to this region, + * this field will contain approximate number of those windows. This + * number is read from the context right before the deregistration is + * attempted and can potentially be slightly different from the current + * number. */ uint32_t bound_windows; } creq_deregister_mr_resp_t, *pcreq_deregister_mr_resp_t; @@ -66548,7 +72504,10 @@ typedef struct cmdq_add_gid { /* TPID = Configurable 3. */ #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 - /* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE header. */ + /* + * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE + * header. + */ #define CMDQ_ADD_GID_VLAN_VLAN_EN UINT32_C(0x8000) /* Identifier field in the IP header. */ uint16_t ipid; @@ -66559,7 +72518,10 @@ typedef struct cmdq_add_gid { /* stats_ctx_id is 15 b */ #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff) #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0 - /* Setting this bit to 1 enables use of own stats context ID instead of per-function */ + /* + * Setting this bit to 1 enables use of own stats context ID + * instead of per-function. + */ #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000) uint32_t unused_0; } cmdq_add_gid_t, *pcmdq_add_gid_t; @@ -66720,7 +72682,10 @@ typedef struct cmdq_modify_gid { /* TPID = Configurable 3. */ #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 - /* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE header. */ + /* + * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE + * header. + */ #define CMDQ_MODIFY_GID_VLAN_VLAN_EN UINT32_C(0x8000) /* Identifier field in the IP header. */ uint16_t ipid; @@ -66731,7 +72696,10 @@ typedef struct cmdq_modify_gid { /* stats_ctx_id is 15 b */ #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff) #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0 - /* Setting this bit to 1 enables use of own stats context ID instead of per-function */ + /* + * Setting this bit to 1 enables use of own stats context ID + * instead of per-function. + */ #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000) uint16_t unused_0; } cmdq_modify_gid_t, *pcmdq_modify_gid_t; @@ -66889,7 +72857,10 @@ typedef struct creq_query_gid_resp_sb { /* TPID = Configurable 3. */ #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12) #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 - /* Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE header. */ + /* + * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE + * header. + */ #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN UINT32_C(0x8000) /* Identifier field in the IP header. */ uint16_t ipid; @@ -66946,7 +72917,10 @@ typedef struct cmdq_create_qp1 { #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2 /* SQ page size. */ @@ -66973,7 +72947,10 @@ typedef struct cmdq_create_qp1 { #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 UINT32_C(0x0) /* PBL pointer points to PTE table. */ #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 UINT32_C(0x2) #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2 /* RQ page size. */ @@ -67311,16 +73288,17 @@ typedef struct cmdq_query_roce_stats { /* Flags and attribs of the command. */ uint16_t flags; /* - * When this bit is set FW will use the collection_id to extract RoCE statistics. - * If function_id is also specified the FW will return stats corresponding to the - * collection for the function_id specified. + * When this bit is set FW will use the collection_id to extract + * RoCE statistics. If function_id is also specified the FW will + * return stats corresponding to the collection for the function_id + * specified. */ #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID UINT32_C(0x1) /* - * When this bit is set FW will use the function_id to extract RoCE statistics. - * When collection is specified then FW will return the specific collection - * stats and if the collection is not specified then FW will return the default - * stats which will be for all QPs. + * When this bit is set FW will use the function_id to extract RoCE + * statistics. When collection is specified then FW will return the + * specific collection stats and if the collection is not specified + * then FW will return the default stats which will be for all QPs. */ #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID UINT32_C(0x2) /* Driver supplied handle to associate the command and the response. */ @@ -67382,7 +73360,7 @@ typedef struct creq_query_roce_stats_resp { } creq_query_roce_stats_resp_t, *pcreq_query_roce_stats_resp_t; /* Query RoCE Stats command response side buffer structure. */ -/* creq_query_roce_stats_resp_sb (size:2944b/368B) */ +/* creq_query_roce_stats_resp_sb (size:3072b/384B) */ typedef struct creq_query_roce_stats_resp_sb { /* Command opcode. */ @@ -67487,6 +73465,10 @@ typedef struct creq_query_roce_stats_resp_sb { uint64_t active_qp_count_p2; /* active_qp_count_p3 is 64 b */ uint64_t active_qp_count_p3; + /* express mode SQ doorbell overflow error 64b counter. */ + uint64_t xp_sq_overflow_err; + /* express mode RQ doorbell overflow error 64b counter. */ + uint64_t xp_rq_overflow_error; } creq_query_roce_stats_resp_sb_t, *pcreq_query_roce_stats_resp_sb_t; /************************ @@ -67507,16 +73489,17 @@ typedef struct cmdq_query_roce_stats_ext { /* Flags and attribs of the command. */ uint16_t flags; /* - * When this bit is set FW will use the collection_id to extract RoCE statistics. - * If function_id is also specified the FW will return stats corresponding to the - * collection for the function_id specified. + * When this bit is set FW will use the collection_id to extract + * RoCE statistics. If function_id is also specified the FW will + * return stats corresponding to the collection for the function_id + * specified. */ #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID UINT32_C(0x1) /* - * When this bit is set FW will use the function_id to extract RoCE statistics. - * When collection is specified then FW will return the specific collection - * stats and if the collection is not specified then FW will return the default - * stats which will be for all QPs. + * When this bit is set FW will use the function_id to extract RoCE + * statistics. When collection is specified then FW will return the + * specific collection stats and if the collection is not specified + * then FW will return the default stats which will be for all QPs. */ #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID UINT32_C(0x2) /* Driver supplied handle to associate the command and the response. */ @@ -67578,7 +73561,7 @@ typedef struct creq_query_roce_stats_ext_resp { } creq_query_roce_stats_ext_resp_t, *pcreq_query_roce_stats_ext_resp_t; /* Query extended RoCE Stats command response side buffer structure. */ -/* creq_query_roce_stats_ext_resp_sb (size:1984b/248B) */ +/* creq_query_roce_stats_ext_resp_sb (size:2304b/288B) */ typedef struct creq_query_roce_stats_ext_resp_sb { /* Command opcode. */ @@ -67694,7 +73677,8 @@ typedef struct creq_query_roce_stats_ext_resp_sb { */ uint64_t to_retransmit; /* - * Number of duplicate read requests resulting in HW retransmission. + * Number of duplicate read/atomic requests resulting in HW + * retransmission. * This counter is only applicable for devices that support * hardware based retransmission. */ @@ -67707,6 +73691,39 @@ typedef struct creq_query_roce_stats_ext_resp_sb { uint64_t rx_dcn_payload_cut; /* Number of transmitted packets that bypassed the transmit engine. */ uint64_t te_bypassed; + /* + * Number of transmitted DCN CNP packets. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t tx_dcn_cnp; + /* + * Number of received DCN CNP packets. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_dcn_cnp; + /* + * Number of received DCN payload cut packets. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_payload_cut; + /* + * Number of received DCN payload cut packets that are ignored + * because they failed the PSN checks. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_payload_cut_ignored; + /* + * Number of received DCN CNP packets that are ignored either + * because the ECN is not enabled on the QP or the ECN is enabled + * but the CNP packets do not pass the packet validation checks. + * This counter is only applicable for devices that support + * the DCN Payload Cut feature. + */ + uint64_t rx_dcn_cnp_ignored; } creq_query_roce_stats_ext_resp_sb_t, *pcreq_query_roce_stats_ext_resp_sb_t; /************** @@ -67773,7 +73790,7 @@ typedef struct creq_query_func_resp { } creq_query_func_resp_t, *pcreq_query_func_resp_t; /* Query function command response side buffer structure. */ -/* creq_query_func_resp_sb (size:1088b/136B) */ +/* creq_query_func_resp_sb (size:1280b/160B) */ typedef struct creq_query_func_resp_sb { /* Command opcode. */ @@ -67792,17 +73809,26 @@ typedef struct creq_query_func_resp_sb { uint8_t reserved8; /* Max MR size supported. */ uint64_t max_mr_size; - /* Max QP supported. */ + /* + * Max QP supported. + * For devices that support the pseudo static allocation scheme, + * this count: + * -excludes the QP1 count. + * -includes the count of QPs that can be migrated from the other PF + * Therefore, during normal operation when both PFs are active, + * the supported number of RoCE QPs for each of the PF is half + * of the advertised value. + */ uint32_t max_qp; /* Max WQEs per QP. */ uint16_t max_qp_wr; /* Device capability flags. */ uint16_t dev_cap_flags; /* Allow QP resizing. */ - #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP UINT32_C(0x1) + #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP UINT32_C(0x1) /* Specifies Congestion Control (CC) generation. */ #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK UINT32_C(0xe) - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1 /* * Includes support for DCTCP and TCP CC algorithms, * enabling operation in networks where PFC is enabled. @@ -67813,7 +73839,8 @@ typedef struct creq_query_func_resp_sb { * enabling fast ramp up and convergence, * as well as operation in networks where PFC is not enabled. * Includes a number of parameters that are different from cc_gen0 - * chips as well as new parameters. TCP CC algorithm is not supported. + * chips as well as new parameters. TCP CC algorithm is not + * supported. */ #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (UINT32_C(0x1) << 1) /* @@ -67821,21 +73848,29 @@ typedef struct creq_query_func_resp_sb { * reduce_init_en, reduce_init_cong_free_rtts_th, random_no_red_en, * actual_cr_shift_correction_en, quota_period_adjust_en */ - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (UINT32_C(0x2) << 1) - #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (UINT32_C(0x2) << 1) + /* + * Enhances cc_gen1_ext support, to include support for DCN/SARA. + * Enables query and modification of Queue level table attributes, + * which are used by the hardware to determine the QP's flow rate + * based on congestion level and thereby reduce RoCE packet drop + * due to network congestion. + */ + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2 (UINT32_C(0x3) << 1) + #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2 /* * Support for the extended RoCE statistics is available. These * statistics are queried via the `query_roce_stats_ext` command * and are enabled on a per-QP basis via `create_qp`. */ - #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS UINT32_C(0x10) + #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS UINT32_C(0x10) /* * Support for both allocating and registering a new MR via the * `register_mr` command is available. With this feature the * `allocate_mrw` command does not have to be called before * registering. */ - #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC UINT32_C(0x20) + #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC UINT32_C(0x20) /* * Support for optimized transmit path to lower latency for WQEs * with inline data. @@ -67846,13 +73881,40 @@ typedef struct creq_query_func_resp_sb { * the following CQE types: * RES_UD, RES_RAWETH_QP1, RES_UD_CFA */ - #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 UINT32_C(0x80) + #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 UINT32_C(0x80) /* Support for ping pong push mode is available. */ #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE UINT32_C(0x100) /* Support for hardware requester retransmission is enabled. */ - #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED UINT32_C(0x200) + #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED UINT32_C(0x200) /* Support for hardware responder retransmission is enabled. */ - #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED UINT32_C(0x400) + #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED UINT32_C(0x400) + /* Support for link aggregation is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED UINT32_C(0x800) + /* link_aggr_supported is valid. */ + #define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED_VALID UINT32_C(0x1000) + /* + * Support for pseudo static QP allocation is enabled. + * This feature enables the following capabilities: + * - QP context ID space is pseudo-static partitioned across PFs. + * - An application can use a predetermined + * QP context ID assignment scheme for specific operations. + * - For 2-port adapters, the application can migrate the QP context + * ID range across PFs, using the `orchestrate_qid_migration` HWRM, + * during network events such as Link Down. + */ + #define CREQ_QUERY_FUNC_RESP_SB_PSEUDO_STATIC_QP_ALLOC_SUPPORTED UINT32_C(0x2000) + /* + * Support for Express Mode is enabled. + * For Express mode, the QP resources (SQ/RQ) are allocated in + * on-chip queue memory. The host driver should not allocate memory + * for these queue structures. + */ + #define CREQ_QUERY_FUNC_RESP_SB_EXPRESS_MODE_SUPPORTED UINT32_C(0x4000) + /* + * IRRQ/ORRQ and MSN Table structures are allocated in internal + * queue memory. + */ + #define CREQ_QUERY_FUNC_RESP_SB_INTERNAL_QUEUE_MEMORY UINT32_C(0x8000) /* Max CQs supported. */ uint32_t max_cq; /* Max CQEs per CQ supported. */ @@ -67860,15 +73922,19 @@ typedef struct creq_query_func_resp_sb { /* Max PDs supported. */ uint32_t max_pd; /* - * Max SGEs per QP WQE supported. On chips with variable-size WQE support, - * this field is applicable only for the backward compatible mode. + * Max SGEs per QP WQE supported. On chips with variable-size WQE + * support, this field is applicable only for the backward compatible + * mode. */ uint8_t max_sge; /* Max SGEs per SRQ WQE supported. */ uint8_t max_srq_sge; /* Max outstanding RDMA read & atomic supported. */ uint8_t max_qp_rd_atom; - /* Max outstanding RDMA read & atomic that can be sent from an initiator. */ + /* + * Max outstanding RDMA read & atomic that can be sent from an + * initiator. + */ uint8_t max_qp_init_rd_atom; /* Max MRs supported. */ uint32_t max_mr; @@ -67898,21 +73964,117 @@ typedef struct creq_query_func_resp_sb { /* Max GIDs supported. */ uint32_t max_gid; /* - * An array of 48 8-bit values to specify allocation multiplier for TQM host buffer regions. - * Each region occupies 16 MB of TQM PBL address space: 0x00000000, 0x01000000, 0x02000000, etc. - * The host needs to allocate (*multiplier, rounded up to page size) of physical memory for non-zero slots - * and map the pages to the corresponding 16MB regions. - * Typically there are total 3 non-zero values in this array, their values are 16, 16, 12. - * Cu+ will only populate up to index 11. SR may populate up to index 47. + * An array of 48 8-bit values to specify allocation multiplier for TQM + * host buffer regions. Each region occupies 16 MB of TQM PBL address + * space: 0x00000000, 0x01000000, 0x02000000, etc. + * The host needs to allocate (*multiplier, rounded up + * to page size) of physical memory for non-zero slots and map the + * pages to the corresponding 16MB regions. Typically there are total + * 3 non-zero values in this array, their values are 16, 16, 12. + * Cu+ will only populate up to index 11. SR may populate up to + * index 47. */ uint32_t tqm_alloc_reqs[12]; /* Max Doorbell page indices supported. */ uint32_t max_dpi; /* Max SGEs per QP WQE supported in the variable-size WQE mode. */ uint8_t max_sge_var_wqe; - uint8_t reserved_8; + /* Device capability extended flags. */ + uint8_t dev_cap_ext_flags; + /* RDMA Atomic operations are not supported. */ + #define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED UINT32_C(0x1) + /* Support driver version registration. */ + #define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED UINT32_C(0x2) + /* Support for batch allocation of QPs is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED UINT32_C(0x4) + /* Support for batch deletion of QPs is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED UINT32_C(0x8) + /* + * Support for extended RoCE statistics context + * with periodic DMA is enabled. The statistics contexts + * are allocated via `allocate_roce_stats_ext_ctx` + * and deallocated via `deallocate_roce_stats_ext_ctx`. + * These contexts are assigned on a per-QP, per-group of QPs + * or per-function basis via `create_qp`, `create_qp_batch` + * or `modify_qp`command. + * In addition to periodic DMA to a host address, + * these statistics can be queried via `query_roce_stats_ext_v2`. + */ + #define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED UINT32_C(0x10) + /* + * Support for the srq_sge field in the create_srq command is + * enabled. + */ + #define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED UINT32_C(0x20) + /* Support for fixed size SQ wqe (128B) is disabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED UINT32_C(0x40) + /* Support for DCN (Drop Congestion Notification) is enabled. */ + #define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED UINT32_C(0x80) /* Max inline data supported in the variable-size WQE mode. */ uint16_t max_inline_data_var_wqe; + /* + * starting xid of the predetermined assignment scheme supported + * by the pseudo static allocation feature. Note that for a PF, + * the start_qid is itself pseudo_static, and can change when the QP + * context id range is migrated by the driver using the + * cmdq_orchestrate_qid_migration. The supported QP count is + * available in the `max_qp` field of `cmdq_query_func`. + */ + uint32_t start_qid; + /* + * Max number of MSN table entries supported for devices that support + * the `internal_queue_memory` feature. + */ + uint8_t max_msn_table_size; + /* reserved8_1 is 8 b */ + uint8_t reserved8_1; + /* Device capability extended flags_2 */ + uint16_t dev_cap_ext_flags_2; + /* Firmware support for optimizing Modify QP operation */ + #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED UINT32_C(0x1) + /* + * Device supports changing UDP source port of RoCEv2 packets using + * WQE. + */ + #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED UINT32_C(0x2) + /* Device supports CQ Coalescing. */ + #define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED UINT32_C(0x4) + /* + * Device allows a memory region to be designated as + * relaxed-ordering enabled or disabled. + */ + #define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED UINT32_C(0x8) + /* The type of lookup table used for requester retransmission. */ + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK UINT32_C(0x30) + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4 + /* Requester Retransmission uses a PSN table in host memory. */ + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (UINT32_C(0x0) << 4) + /* Requester Retransmission uses an MSN table in host memory. */ + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (UINT32_C(0x1) << 4) + /* + * Requester Retransmission uses an MSN table in Device Internal + * Queue Memory. + */ + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (UINT32_C(0x2) << 4) + #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE + /* + * Max number of 16B IQM memory slots supported by SQ or RQ + * when QP is in express mode. + * This field is only valid for express mode QPs. + */ + uint16_t max_xp_qp_size; + /* + * Max number of QPs that can be created in one `create_qp_batch` + * command. + */ + uint16_t create_qp_batch_size; + /* + * Max number of QPs that can be destroyed in one `destroy_qp_batch` + * command. + */ + uint16_t destroy_qp_batch_size; + uint16_t reserved16; + uint64_t reserved64; } creq_query_func_resp_sb_t, *pcreq_query_func_resp_sb_t; /********************** @@ -67948,15 +74110,34 @@ typedef struct cmdq_set_func_resources { uint8_t reserved8; /* Host address of the response. */ uint64_t resp_addr; - /* Number of QPs. It is the responsibility of the host to first extend the existing PBL with new addresses to pages to handle the adjustment. Must be greater or equal to current. */ + /* + * Number of QPs. It is the responsibility of the host to first extend + * the existing PBL with new addresses to pages to handle the + * adjustment. Must be greater or equal to current. + */ uint32_t number_of_qp; - /* Number of MRWs. It is the responsibility of the host to first extend the existing PBL with new addresses to pages to handle the adjustment. Must be greater or equal to current. */ + /* + * Number of MRWs. It is the responsibility of the host to first extend + * the existing PBL with new addresses to pages to handle the + * adjustment. Must be greater or equal to current. + */ uint32_t number_of_mrw; - /* Number of SRQs. It is the responsibility of the host to first extend the existing PBL with new addresses to pages to handle the adjustment. Must be greater or equal to current. */ + /* + * Number of SRQs. It is the responsibility of the host to first extend + * the existing PBL with new addresses to pages to handle the + * adjustment. Must be greater or equal to current. + */ uint32_t number_of_srq; - /* Number of CQs. It is the responsibility of the host to first extend the existing PBL with new addresses to pages to handle the adjustment. Must be greater or equal to current. */ + /* + * Number of CQs. It is the responsibility of the host to first extend + * the existing PBL with new addresses to pages to handle the + * adjustment. Must be greater or equal to current. + */ uint32_t number_of_cq; - /* Number of QPs per VF. */ + /* + * Number of QPs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ uint32_t max_qp_per_vf; /* * If the MR/AV split reservation flag is not set, then this field @@ -67971,13 +74152,25 @@ typedef struct cmdq_set_func_resources { * `max_av_per_vf`. The granularity of these values is defined by * the `mrav_num_entries_unit` field returned by the * `backing_store_qcaps` command. + * + * This field must be set to zero when the flag, l2_vf_resource_mgmt, + * is set and RoCE SRIOV is enabled. */ uint32_t max_mrw_per_vf; - /* Number of SRQs per VF. */ + /* + * Number of SRQs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ uint32_t max_srq_per_vf; - /* Number of CQs per VF. */ + /* + * Number of CQs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ uint32_t max_cq_per_vf; - /* Number of GIDs per VF. */ + /* + * Number of GIDs per VF. This field must be set to zero when the flag, + * l2_vf_resource_mgmt, is set and RoCE SRIOV is enabled. + */ uint32_t max_gid_per_vf; /* Statistics context index for this function. */ uint32_t stat_ctx_id; @@ -68091,7 +74284,10 @@ typedef struct creq_stop_func_resp { typedef struct cmdq_read_context { /* Command opcode. */ uint8_t opcode; - /* Read the current state of any internal resource context. Can only be issued from a PF. */ + /* + * Read the current state of any internal resource context. Can only + * be issued from a PF. + */ #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT UINT32_C(0x85) #define CMDQ_READ_CONTEXT_OPCODE_LAST CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT /* Size of the command in 16-byte units. */ @@ -68105,23 +74301,33 @@ typedef struct cmdq_read_context { uint8_t reserved8; /* Host address of the response. */ uint64_t resp_addr; - uint32_t type_xid; /* Context ID */ - #define CMDQ_READ_CONTEXT_XID_MASK UINT32_C(0xffffff) - #define CMDQ_READ_CONTEXT_XID_SFT 0 + uint32_t xid; /* Context type */ - #define CMDQ_READ_CONTEXT_TYPE_MASK UINT32_C(0xff000000) - #define CMDQ_READ_CONTEXT_TYPE_SFT 24 - /* Read QPC. The context (448 bytes) goes to resp_addr (as is, without a header), and resp_size should be set to 28 (448/16) */ - #define CMDQ_READ_CONTEXT_TYPE_QPC (UINT32_C(0x0) << 24) - /* Read CQ. The context (64 bytes) goes to resp_addr (as is, without a header), and resp_size should be set to 4 (64/16) */ - #define CMDQ_READ_CONTEXT_TYPE_CQ (UINT32_C(0x1) << 24) - /* Read MRW. The context (128 bytes) goes to resp_addr (as is, without a header), and resp_size should be set to 8 (128/16) */ - #define CMDQ_READ_CONTEXT_TYPE_MRW (UINT32_C(0x2) << 24) - /* Read SRQ. The context (64 bytes) goes to resp_addr (as is, without a header), and resp_size should be set to 4 (64/16) */ - #define CMDQ_READ_CONTEXT_TYPE_SRQ (UINT32_C(0x3) << 24) - #define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ - uint32_t unused_0; + uint8_t type; + /* + * Read QPC. The context (448 bytes) goes to resp_addr (as is, + * without a header), and resp_size should be set to 28 + * (448/16). + */ + #define CMDQ_READ_CONTEXT_TYPE_QPC UINT32_C(0x0) + /* + * Read CQ. The context (64 bytes) goes to resp_addr (as is, + * without a header), and resp_size should be set to 4 (64/16) + */ + #define CMDQ_READ_CONTEXT_TYPE_CQ UINT32_C(0x1) + /* + * Read MRW. The context (128 bytes) goes to resp_addr (as is, + * without a header), and resp_size should be set to 8 (128/16) + */ + #define CMDQ_READ_CONTEXT_TYPE_MRW UINT32_C(0x2) + /* + * Read SRQ. The context (64 bytes) goes to resp_addr (as is, + * without a header), and resp_size should be set to 4 (64/16) + */ + #define CMDQ_READ_CONTEXT_TYPE_SRQ UINT32_C(0x3) + #define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ + uint8_t unused_0[3]; } cmdq_read_context_t, *pcmdq_read_context_t; /* creq_read_context (size:128b/16B) */ @@ -68154,7 +74360,10 @@ typedef struct creq_read_context { #define CREQ_READ_CONTEXT_V UINT32_C(0x1) /* Event or command opcode. */ uint8_t event; - /* Read the current state of any internal resource context. Can only be issued from a PF. */ + /* + * Read the current state of any internal resource context. Can only + * be issued from a PF. + */ #define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT UINT32_C(0x85) #define CREQ_READ_CONTEXT_EVENT_LAST CREQ_READ_CONTEXT_EVENT_READ_CONTEXT uint16_t reserved16; @@ -68591,9 +74800,15 @@ typedef struct creq_query_roce_cc_gen1_resp_sb_tlv { uint64_t reserved64; /* High order bits of inactivity threshold. */ uint16_t inactivity_th_hi; - /* The number of uS between generation of CNPs when cc_mode is probabilistic marking. */ + /* + * The number of uS between generation of CNPs when cc_mode is + * probabilistic marking. + */ uint16_t min_time_between_cnps; - /* The starting value of congestion probability. Input range is 0 - 1023. */ + /* + * The starting value of congestion probability. Input range + * is 0 - 1023. + */ uint16_t init_cp; /* * In tr_update_mode 0, Target Rate (TR) is updated to @@ -68697,8 +74912,9 @@ typedef struct creq_query_roce_cc_gen1_resp_sb_tlv { uint8_t tr_prob_factor; /* * Threshold to ensure fairness between requester and responder. - * If CR is less than the fairness threshold and a quota period has passed - * priority will be given to the path that did not last transfer data. + * If CR is less than the fairness threshold and a quota period has + * passed priority will be given to the path that did not last + * transfer data. */ uint16_t fairness_cr_th; /* Log based rate reduction divider. */ @@ -68719,9 +74935,15 @@ typedef struct creq_query_roce_cc_gen1_resp_sb_tlv { * updating CP to track CR. */ uint16_t cp_exp_update_th; - /* The threshold on congestion free RTTs above which AI can increase to 16. */ + /* + * The threshold on congestion free RTTs above which AI can increase + * to 16. + */ uint16_t high_exp_ai_rtts_th1; - /* The threshold on congestion free RTTs above which AI can increase to 32. */ + /* + * The threshold on congestion free RTTs above which AI can increase + * to 32. + */ uint16_t high_exp_ai_rtts_th2; /* * The number of congestion free RTTs above which @@ -68756,19 +74978,101 @@ typedef struct creq_query_roce_cc_gen1_resp_sb_tlv { */ uint8_t reduce_init_en; /* - * Minimum threshold value for number of congestion free RTTs before reducing - * to init values for CR, TR, and CP when reduce_init_en is enabled. + * Minimum threshold value for number of congestion free RTTs before + * reducing to init values for CR, TR, and CP when reduce_init_en is + * enabled. */ uint16_t reduce_init_cong_free_rtts_th; /* Enables random no reduction of CR. */ uint8_t random_no_red_en; - /* Enables coarse correction to actual CR when actual RTT is longer than nominal. */ + /* + * Enables coarse correction to actual CR when actual RTT is longer + * than nominal. + */ uint8_t actual_cr_shift_correction_en; /* Enables adjustment to refill quota. */ uint8_t quota_period_adjust_en; uint8_t reserved[5]; } creq_query_roce_cc_gen1_resp_sb_tlv_t, *pcreq_query_roce_cc_gen1_resp_sb_tlv_t; +/* creq_query_roce_cc_gen2_resp_sb_tlv (size:512b/64B) */ + +typedef struct creq_query_roce_cc_gen2_resp_sb_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + uint64_t reserved64; + /* + * DCN queue level threshold values associated with DCN queue + * level table indices 0 to 7. + */ + uint16_t dcn_qlevel_tbl_thr[8]; + /* + * DCN queue level table action values. + * Returns CR, INC_CNP, UPD_IMM & TR fields associated with + * DCN queue level table indices 0 to 7. + */ + uint32_t dcn_qlevel_tbl_act[8]; + /* DCN queue level current rate. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK UINT32_C(0x3fff) + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0 + /* DCN queue level increment CNP count. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP UINT32_C(0x4000) + /* DCN queue level update CR and TR immediately. */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM UINT32_C(0x8000) + /* DCN queue level target rate */ + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK UINT32_C(0x3fff0000) + #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_SFT 16 +} creq_query_roce_cc_gen2_resp_sb_tlv_t, *pcreq_query_roce_cc_gen2_resp_sb_tlv_t; + /*********************** * cmdq_modify_roce_cc * ***********************/ @@ -68972,7 +75276,10 @@ typedef struct cmdq_modify_roce_cc_tlv { * and it must be an integer multiple of 8B. */ uint16_t length; - /* Size of the tlv encapsulated command, including all tlvs and extension data in 16-byte units. */ + /* + * Size of the tlv encapsulated command, including all tlvs and + * extension data in 16-byte units. + */ uint8_t total_size; uint8_t reserved56[7]; /* Command opcode. */ @@ -69170,7 +75477,10 @@ typedef struct cmdq_modify_roce_cc_gen1_tlv { uint64_t reserved64; /* Modify mask signifies the field that is requesting the change. */ uint64_t modify_mask; - /* Update the number of uS between generation of CNPs for probabilistic marking mode. */ + /* + * Update the number of uS between generation of CNPs for + * probabilistic marking mode. + */ #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS UINT32_C(0x1) /* * Update starting value of Congestion Probability (CP). @@ -69216,7 +75526,10 @@ typedef struct cmdq_modify_roce_cc_gen1_tlv { #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN UINT32_C(0x8000) /* Update number of bytes per usec. */ #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC UINT32_C(0x10000) - /* Update threshold used to reset QPC CC state to its initial state. */ + /* + * Update threshold used to reset QPC CC state to its initial + * state. + */ #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH UINT32_C(0x20000) /* Update number of valid lsbits in CR and TR */ #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH UINT32_C(0x40000) @@ -69304,7 +75617,10 @@ typedef struct cmdq_modify_roce_cc_gen1_tlv { #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES UINT32_C(0x4000000000)L /* Update enable of reduction of CR, TR, and CP to init values. */ #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN UINT32_C(0x8000000000)L - /* Update threshold used for reduction of CR, TR, and CP to init values. */ + /* + * Update threshold used for reduction of CR, TR, and CP to init + * values. + */ #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH UINT32_C(0x10000000000)L /* Update enable of random no reduction of CR. */ #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN UINT32_C(0x20000000000)L @@ -69314,9 +75630,15 @@ typedef struct cmdq_modify_roce_cc_gen1_tlv { #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN UINT32_C(0x80000000000)L /* High order bits of inactivity threshold. */ uint16_t inactivity_th_hi; - /* The number of uS between generation of CNPs when cc_mode is probabilistic marking. */ + /* + * The number of uS between generation of CNPs when cc_mode is + * probabilistic marking. + */ uint16_t min_time_between_cnps; - /* The starting value of congestion probability. Input range is 0 - 1023. */ + /* + * The starting value of congestion probability. Input range + * is 0 - 1023. + */ uint16_t init_cp; /* * In tr_update_mode 0, Target Rate (TR) is updated to @@ -69420,8 +75742,9 @@ typedef struct cmdq_modify_roce_cc_gen1_tlv { uint8_t tr_prob_factor; /* * Threshold to ensure fairness between requester and responder. - * If CR is less than the fairness threshold and a quota period has passed - * priority will be given to the path that did not last transfer data. + * If CR is less than the fairness threshold and a quota period has + * passed priority will be given to the path that did not last + * transfer data. */ uint16_t fairness_cr_th; /* Log based rate reduction divider. */ @@ -69442,9 +75765,15 @@ typedef struct cmdq_modify_roce_cc_gen1_tlv { * updating CP to track CR. */ uint16_t cp_exp_update_th; - /* The threshold on congestion free RTTs above which AI can increase to 16. */ + /* + * The threshold on congestion free RTTs above which AI can increase + * to 16. + */ uint16_t high_exp_ai_rtts_th1; - /* The threshold on congestion free RTTs above which AI can increase to 32. */ + /* + * The threshold on congestion free RTTs above which AI can increase + * to 32. + */ uint16_t high_exp_ai_rtts_th2; /* * The number of congestion free RTTs above which @@ -69479,19 +75808,122 @@ typedef struct cmdq_modify_roce_cc_gen1_tlv { */ uint8_t reduce_init_en; /* - * Minimum threshold value for number of congestion free RTTs before reducing - * to init values for CR, TR, and CP when reduce_init_en is enabled. + * Minimum threshold value for number of congestion free RTTs before + * reducing to init values for CR, TR, and CP when reduce_init_en is + * enabled. */ uint16_t reduce_init_cong_free_rtts_th; /* Enables random no reduction of CR. */ uint8_t random_no_red_en; - /* Enables coarse correction to actual CR when actual RTT is longer than nominal. */ + /* + * Enables coarse correction to actual CR when actual RTT is longer + * than nominal. + */ uint8_t actual_cr_shift_correction_en; /* Enables adjustment to refill quota. */ uint8_t quota_period_adjust_en; uint8_t reserved[5]; } cmdq_modify_roce_cc_gen1_tlv_t, *pcmdq_modify_roce_cc_gen1_tlv_t; +/* cmdq_modify_roce_cc_gen2_tlv (size:256b/32B) */ + +typedef struct cmdq_modify_roce_cc_gen2_tlv { + /* + * The command discriminator is used to differentiate between various + * types of HWRM messages. This includes legacy HWRM and RoCE slowpath + * command messages as well as newer TLV encapsulated HWRM commands. + * + * For TLV encapsulated messages this field must be 0x8000. + */ + uint16_t cmd_discr; + uint8_t reserved_8b; + uint8_t tlv_flags; + /* + * Indicates the presence of additional TLV encapsulated data + * follows this TLV. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE UINT32_C(0x1) + /* Last TLV in a sequence of TLVs. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0) + /* More TLVs follow this TLV. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1) + /* + * When an HWRM receiver detects a TLV type that it does not + * support with the TLV required flag set, the receiver must + * reject the HWRM message with an error code indicating an + * unsupported TLV type. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2) + /* No */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1) + /* Yes */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1) + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_LAST CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES + /* + * This field defines the TLV type value which is divided into + * two ranges to differentiate between global and local TLV types. + * Global TLV types must be unique across all defined TLV types. + * Local TLV types are valid only for extensions to a given + * HWRM message and may be repeated across different HWRM message + * types. There is a direct correlation of each HWRM message type + * to a single global TLV type value. + * + * Global TLV range: `0 - (63k-1)` + * + * Local TLV range: `63k - (64k-1)` + */ + uint16_t tlv_type; + /* + * Length of the message data encapsulated by this TLV in bytes. + * This length does not include the size of the TLV header itself + * and it must be an integer multiple of 8B. + */ + uint16_t length; + uint64_t reserved64; + /* Modify mask signifies the field that is requesting the change. */ + uint64_t modify_mask; + /* + * Modify the specific DCN queue level table index data. + * This must be set, to select the table index that needs an + * update. + */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_IDX UINT32_C(0x1) + /* Modify the DCN queue level threshold. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_THR UINT32_C(0x2) + /* Modify DCN queue level current rate. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_CR UINT32_C(0x4) + /* Modify DCN queue level increment CNP count. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_INC_CNP UINT32_C(0x8) + /* Modify DCN queue level update current & target rate immediately. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_UPD_IMM UINT32_C(0x10) + /* Modify DCN queue level target rate. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_TR UINT32_C(0x20) + /* DCN queue level table index. Valid values are from 0 to 7. */ + uint8_t dcn_qlevel_tbl_idx; + uint8_t reserved8; + /* + * DCN queue level threshold value associated with a DCN queue + * level table index. + */ + uint16_t dcn_qlevel_tbl_thr; + /* + * DCN queue level table action. + * Updates CR, INC_CNP, UPD_IMM & TR fields associated with the + * DCN queue level table index. + */ + uint32_t dcn_qlevel_tbl_act; + /* DCN queue level current rate. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK UINT32_C(0x3fff) + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0 + /* DCN queue level increment CNP count. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP UINT32_C(0x4000) + /* DCN queue level update CR and TR immediately. */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM UINT32_C(0x8000) + /* DCN queue level target rate */ + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK UINT32_C(0x3fff0000) + #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_SFT 16 +} cmdq_modify_roce_cc_gen2_tlv_t, *pcmdq_modify_roce_cc_gen2_tlv_t; + /* creq_modify_roce_cc_resp (size:128b/16B) */ typedef struct creq_modify_roce_cc_resp { @@ -69637,7 +76069,10 @@ typedef struct creq_set_link_aggr_mode_resources_resp { typedef struct cmdq_vf_backchannel_request { /* Command opcode. */ uint8_t opcode; - /* Send a request from VF to pass a command to the PF. VF HSI is suspended until the PF returns the response */ + /* + * Send a request from VF to pass a command to the PF. VF HSI is + * suspended until the PF returns the response. + */ #define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86) #define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_LAST CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST /* Size of the command in 16-byte units. */ @@ -69653,7 +76088,10 @@ typedef struct cmdq_vf_backchannel_request { uint64_t resp_addr; /* Address of command request structure in VF space */ uint64_t command_addr; - /* Command request length (up to 4K). An optional address of the extended response buffer should be provided in the request */ + /* + * Command request length (up to 4K). An optional address of the extended + * response buffer should be provided in the request. + */ uint16_t command_length; uint8_t unused_0[6]; } cmdq_vf_backchannel_request_t, *pcmdq_vf_backchannel_request_t; @@ -69664,7 +76102,10 @@ typedef struct cmdq_vf_backchannel_request { typedef struct cmdq_read_vf_memory { /* Command opcode. */ uint8_t opcode; - /* Read VF memory (primarily to get the backchannel request blob). Can only be issued from a PF. */ + /* + * Read VF memory (primarily to get the backchannel request blob). Can + * only be issued from a PF. + */ #define CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY UINT32_C(0x87) #define CMDQ_READ_VF_MEMORY_OPCODE_LAST CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY /* Size of the command in 16-byte units. */ @@ -69693,7 +76134,11 @@ typedef struct cmdq_read_vf_memory { typedef struct cmdq_complete_vf_request { /* Command opcode. */ uint8_t opcode; - /* Write VF memory (primarily to put the backchannel response blob), and reenable VF HSI (post a CAG completion to it). Can only be issued from a PF. */ + /* + * Write VF memory (primarily to put the backchannel response blob), + * and reenable VF HSI (post a CAG completion to it). Can only be + * issued from a PF. + */ #define CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88) #define CMDQ_COMPLETE_VF_REQUEST_OPCODE_LAST CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST /* Size of the command in 16-byte units. */ @@ -69707,7 +76152,10 @@ typedef struct cmdq_complete_vf_request { uint8_t reserved8; /* Host address of the response. */ uint64_t resp_addr; - /* Optional address of extended response in VF space to write. Length is in resp_size in 16 byte units. */ + /* + * Optional address of extended response in VF space to write. Length is + * in resp_size in 16 byte units. + */ uint64_t addr; /* Completion misc field to VF CREQ */ uint32_t vf_misc; @@ -69721,6 +76169,587 @@ typedef struct cmdq_complete_vf_request { uint32_t unused_1; } cmdq_complete_vf_request_t, *pcmdq_complete_vf_request_t; +/***************************** + * orchestrate_qid_migration * + *****************************/ + + +/* cmdq_orchestrate_qid_migration (size:256b/32B) */ + +typedef struct cmdq_orchestrate_qid_migration { + /* Command opcode. */ + uint8_t opcode; + /* + * This command updates the QP context id ranges on the PF, + * to orchestrate QP context id range migration for devices that + * support the pseudo-static QP allocation feature. + */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93) + #define CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_LAST CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_ORCHESTRATE_QID_MIGRATION + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + uint8_t qid_migration_flags; + /* Flags to orchestrate QP context ID range migration amongst PFs. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_MASK UINT32_C(0xf) + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_SFT 0 + /* Enable the PF's native QP context ID range. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_NATIVE_QID_RANGE UINT32_C(0x0) + /* Enable the PF's extended QP context ID range. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_EXTENDED_QID_RANGE UINT32_C(0x1) + /* Disable the PF's native QP context ID range. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_NATIVE_QID_RANGE UINT32_C(0x2) + /* Disable the PF's extended QP context ID range. */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_EXTENDED_QID_RANGE UINT32_C(0x3) + #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_LAST CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_EXTENDED_QID_RANGE + /* unused4 is 4 b */ + #define CMDQ_ORCHESTRATE_QID_MIGRATION_UNUSED4_MASK UINT32_C(0xf0) + #define CMDQ_ORCHESTRATE_QID_MIGRATION_UNUSED4_SFT 4 + uint8_t reserved56[7]; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_orchestrate_qid_migration_t, *pcmdq_orchestrate_qid_migration_t; + +/* creq_orchestrate_qid_migration_resp (size:128b/16B) */ + +typedef struct creq_orchestrate_qid_migration_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_LAST CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Orchestrate QPID migration command response. */ + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93) + #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_LAST CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_ORCHESTRATE_QID_MIGRATION + uint8_t reserved48[6]; +} creq_orchestrate_qid_migration_resp_t, *pcreq_orchestrate_qid_migration_resp_t; + +/******************* + * create_qp_batch * + *******************/ + + +/* cmdq_create_qp_batch (size:384b/48B) */ + +typedef struct cmdq_create_qp_batch { + /* Command opcode. */ + uint8_t opcode; + /* This command allocates a batch of QPs in a sequential range. */ + #define CMDQ_CREATE_QP_BATCH_OPCODE_CREATE_QP_BATCH UINT32_C(0x94) + #define CMDQ_CREATE_QP_BATCH_OPCODE_LAST CMDQ_CREATE_QP_BATCH_OPCODE_CREATE_QP_BATCH + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Starting QP context id to be used for the sequential range. */ + uint32_t start_xid; + /* Count of QPs to be allocated */ + uint32_t count; + /* Size of an individual element of the qp_params_array. */ + uint32_t per_qp_param_size; + uint32_t reserved32; + /* + * Host DMA address of the array of per-QP parameters. + * Per-QP parameters are identical to those of the + * `create_qp` command and specified by the + * `create_qp_batch_data` structure. + */ + uint64_t qp_params_array; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_create_qp_batch_t, *pcmdq_create_qp_batch_t; + +/* creq_create_qp_batch_resp (size:128b/16B) */ + +typedef struct creq_create_qp_batch_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_CREATE_QP_BATCH_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_CREATE_QP_BATCH_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_CREATE_QP_BATCH_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_CREATE_QP_BATCH_RESP_TYPE_LAST CREQ_CREATE_QP_BATCH_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_CREATE_QP_BATCH_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Create batch QPs command response. */ + #define CREQ_CREATE_QP_BATCH_RESP_EVENT_CREATE_QP_BATCH UINT32_C(0x94) + #define CREQ_CREATE_QP_BATCH_RESP_EVENT_LAST CREQ_CREATE_QP_BATCH_RESP_EVENT_CREATE_QP_BATCH + uint16_t reserved16; + /* Count of QPs successfully created. */ + uint32_t count; +} creq_create_qp_batch_resp_t, *pcreq_create_qp_batch_resp_t; + +/******************** + * destroy_qp_batch * + ********************/ + + +/* cmdq_destroy_qp_batch (size:256b/32B) */ + +typedef struct cmdq_destroy_qp_batch { + /* Command opcode. */ + uint8_t opcode; + /* + * This command deletes the batch of requested count of QPs. + * The starting QP ID can be specified to request a batch deletion + * of a sequential range. + */ + #define CMDQ_DESTROY_QP_BATCH_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95) + #define CMDQ_DESTROY_QP_BATCH_OPCODE_LAST CMDQ_DESTROY_QP_BATCH_OPCODE_DESTROY_QP_BATCH + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Starting QP context id to be used for the sequential range. */ + uint32_t start_xid; + /* + * Count of QPs to be deleted. A value of zero implies all QPs + * are to be deleted. + */ + uint32_t count; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_destroy_qp_batch_t, *pcmdq_destroy_qp_batch_t; + +/* creq_destroy_qp_batch_resp (size:128b/16B) */ + +typedef struct creq_destroy_qp_batch_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_LAST CREQ_DESTROY_QP_BATCH_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + uint32_t reserved32; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DESTROY_QP_BATCH_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Destroy batch QPs command response. */ + #define CREQ_DESTROY_QP_BATCH_RESP_EVENT_DESTROY_QP_BATCH UINT32_C(0x95) + #define CREQ_DESTROY_QP_BATCH_RESP_EVENT_LAST CREQ_DESTROY_QP_BATCH_RESP_EVENT_DESTROY_QP_BATCH + uint16_t reserved16; + /* Count of QPs successfully destroyed. */ + uint32_t count; +} creq_destroy_qp_batch_resp_t, *pcreq_destroy_qp_batch_resp_t; + +/******************************* + * allocate_roce_stats_ext_ctx * + *******************************/ + + +/* cmdq_allocate_roce_stats_ext_ctx (size:256b/32B) */ + +typedef struct cmdq_allocate_roce_stats_ext_ctx { + /* Command opcode. */ + uint8_t opcode; + /* + * This command allocates an extended RoCE statistics context + * that supports periodic DMA to a host address. The extended + * statistics context id can be assigned by the driver, + * via `create_qp`, `create_qp_batch` or `modify_qp` to a + * specific QP, a subset of QPs or to all QPs of a specific function. + * These statistics can be queried via `query_roce_stats_ext_v2`. + */ + #define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96) + #define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_LAST CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* + * This is the address to be programmed in the statistic block + * by the firmware to support periodic DMA of the statistics. + */ + uint64_t stats_dma_addr; + /* + * The statistic block update period in ms. + * e.g. 250ms, 500ms, 750ms, 1000ms. + * If update_period_ms is 0, then the stats update + * shall be never done and the DMA address shall not be used. + * In this case, the statistics can only be read by + * `query_roce_stats_ext_v2` command. + */ + uint32_t update_period_ms; + /* Steering tag to use for memory transactions. */ + uint16_t steering_tag; + uint16_t reserved16; +} cmdq_allocate_roce_stats_ext_ctx_t, *pcmdq_allocate_roce_stats_ext_ctx_t; + +/* creq_allocate_roce_stats_ext_ctx_resp (size:128b/16B) */ + +typedef struct creq_allocate_roce_stats_ext_ctx_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_LAST CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Extended RoCE statistics context id. */ + uint32_t roce_stats_ext_xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Allocate extended RoCE statistics context command response. */ + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96) + #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_LAST CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX + uint8_t reserved48[6]; +} creq_allocate_roce_stats_ext_ctx_resp_t, *pcreq_allocate_roce_stats_ext_ctx_resp_t; + +/********************************* + * deallocate_roce_stats_ext_ctx * + *********************************/ + + +/* cmdq_deallocate_roce_stats_ext_ctx (size:256b/32B) */ + +typedef struct cmdq_deallocate_roce_stats_ext_ctx { + /* Command opcode. */ + uint8_t opcode; + /* This command deallocates an extended RoCE statistics context. */ + #define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97) + #define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_LAST CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Extended RoCE statistics context id. */ + uint32_t roce_stats_ext_xid; + uint32_t reserved32; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_deallocate_roce_stats_ext_ctx_t, *pcmdq_deallocate_roce_stats_ext_ctx_t; + +/* creq_deallocate_roce_stats_ext_ctx_resp (size:128b/16B) */ + +typedef struct creq_deallocate_roce_stats_ext_ctx_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_LAST CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Extended RoCE statistics context id. */ + uint32_t roce_stats_ext_xid; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Deallocate extended RoCE statistics context command response. */ + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97) + #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_LAST CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX + uint8_t reserved48[6]; +} creq_deallocate_roce_stats_ext_ctx_resp_t, *pcreq_deallocate_roce_stats_ext_ctx_resp_t; + +/*************************** + * query_roce_stats_ext_v2 * + ***************************/ + + +/* cmdq_query_roce_stats_ext_v2 (size:256b/32B) */ + +typedef struct cmdq_query_roce_stats_ext_v2 { + /* Command opcode. */ + uint8_t opcode; + /* + * Query extended RoCE statistics for devices that support + * `roce_stats_ext_ctx_supported` feature. + */ + #define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 + /* Size of the command in 16-byte units. */ + uint8_t cmd_size; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t reserved8; + /* Host address of the response. */ + uint64_t resp_addr; + /* Extended RoCE statistics context id. */ + uint32_t roce_stats_ext_xid; + uint32_t reserved32; + /* reserved64 is 64 b */ + uint64_t reserved64; +} cmdq_query_roce_stats_ext_v2_t, *pcmdq_query_roce_stats_ext_v2_t; + +/* creq_query_roce_stats_ext_v2_resp (size:128b/16B) */ + +typedef struct creq_query_roce_stats_ext_v2_resp { + uint8_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_MASK UINT32_C(0x3f) + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_SFT 0 + /* QP Async Notification */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT UINT32_C(0x38) + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Side buffer size in 16-byte units */ + uint32_t size; + uint8_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_V UINT32_C(0x1) + /* Event or command opcode. */ + uint8_t event; + /* Query extended RoCE statistics v2. */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 + uint8_t reserved48[6]; +} creq_query_roce_stats_ext_v2_resp_t, *pcreq_query_roce_stats_ext_v2_resp_t; + +/* Query extended RoCE Stats command response side buffer structure. */ +/* creq_query_roce_stats_ext_v2_resp_sb (size:1920b/240B) */ + +typedef struct creq_query_roce_stats_ext_v2_resp_sb { + /* Command opcode. */ + uint8_t opcode; + /* Query extended RoCE statistics v2. */ + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98) + #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_LAST CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 + /* Status of the response. */ + uint8_t status; + /* Driver supplied handle to associate the command and the response. */ + uint16_t cookie; + /* Flags and attribs of the command. */ + uint16_t flags; + /* Size of the response buffer in 16-byte units. */ + uint8_t resp_size; + uint8_t rsvd; + /* Number of transmitted Atomic request packets without errors. */ + uint64_t tx_atomic_req_pkts; + /* Number of transmitted Read request packets without errors. */ + uint64_t tx_read_req_pkts; + /* Number of transmitted Read response packets without errors. */ + uint64_t tx_read_res_pkts; + /* Number of transmitted Write request packets without errors. */ + uint64_t tx_write_req_pkts; + /* Number of transmitted RC Send packets without errors. */ + uint64_t tx_rc_send_req_pkts; + /* + * Number of transmitted UD Send (including QP1) packets + * without errors. + */ + uint64_t tx_ud_send_req_pkts; + /* Number of transmitted CNPs. Includes DCN_CNPs. */ + uint64_t tx_cnp_pkts; + /* + * Number of transmitted RoCE packets. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t tx_roce_pkts; + /* + * Number of transmitted RoCE header and payload bytes. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t tx_roce_bytes; + /* + * Number of drops that occurred to lack of buffers. + * This count includes RC sends, RC writes with immediate, + * UD sends, RawEth, and QP1 packets dropped due to lack of buffers. + */ + uint64_t rx_out_of_buffer_pkts; + /* Number of packets that were received out of sequence. */ + uint64_t rx_out_of_sequence_pkts; + /* + * Number of duplicate read/atomic requests resulting in responder + * hardware retransmission. + */ + uint64_t dup_req; + /* + * Number of missing response packets resulting in hardware + * retransmission. + */ + uint64_t missing_resp; + /* + * Number of sequence error NAKs received resulting in hardware + * retransmission. + */ + uint64_t seq_err_naks_rcvd; + /* Number of RNR NAKs received resulting in hardware retransmission. */ + uint64_t rnr_naks_rcvd; + /* Number of timeouts resulting in hardware retransmission. */ + uint64_t to_retransmits; + /* Number of received Atomic request packets without errors. */ + uint64_t rx_atomic_req_pkts; + /* Number of received Read request packets without errors. */ + uint64_t rx_read_req_pkts; + /* Number of received Read response packets without errors. */ + uint64_t rx_read_res_pkts; + /* Number of received Write request packets without errors. */ + uint64_t rx_write_req_pkts; + /* Number of received RC Send packets without errors. */ + uint64_t rx_rc_send_pkts; + /* Number of received UD Send packets without errors. */ + uint64_t rx_ud_send_pkts; + /* Number of received DCN payload cut packets. */ + uint64_t rx_dcn_payload_cut; + /* Number of received ECN-marked packets. */ + uint64_t rx_ecn_marked_pkts; + /* Number of received CNP packets. Includes DCN_CNPs. */ + uint64_t rx_cnp_pkts; + /* + * Number of received RoCE packets including RoCE packets with errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_pkts; + /* + * Number of received RoCE header and payload bytes including RoCE + * packets with errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_bytes; + /* + * Number of received RoCE packets without errors. + * This includes RC, UD, RawEth, and QP1 packets + */ + uint64_t rx_roce_good_pkts; + /* + * Number of received RoCE header and payload bytes without errors. + * This includes RC, UD, RawEth, and QP1 packets. + */ + uint64_t rx_roce_good_bytes; +} creq_query_roce_stats_ext_v2_resp_sb_t, *pcreq_query_roce_stats_ext_v2_resp_sb_t; + /* RoCE function async event notifications. */ /* creq_func_event (size:128b/16B) */ @@ -69791,7 +76820,10 @@ typedef struct creq_func_event { #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR UINT32_C(0xb) /* A VF sent a backchannel command request */ #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST UINT32_C(0x80) - /* Communication resource (QPC, CQ, SRQ, MRW) exhausted, and resource array extension is enabled */ + /* + * Communication resource (QPC, CQ, SRQ, MRW) exhausted, and resource + * array extension is enabled. + */ #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED UINT32_C(0x81) #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED uint8_t reserved48[6]; @@ -69899,7 +76931,10 @@ typedef struct creq_qp_event { #define CREQ_QP_EVENT_EVENT_QUERY_FUNC UINT32_C(0x83) /* Set function resources command response. */ #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84) - /* Read the current state of any internal resource context. Can only be issued from a PF. */ + /* + * Read the current state of any internal resource context. Can only be + * issued from a PF. + */ #define CREQ_QP_EVENT_EVENT_READ_CONTEXT UINT32_C(0x85) /* Map TC to COS response. */ #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS UINT32_C(0x8a) @@ -69914,8 +76949,8 @@ typedef struct creq_qp_event { /* Set LAG mode. */ #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f) /* - * Query QP for a PF other than the requesting PF. Also can query for more - * than one QP. + * Query QP for a PF other than the requesting PF. Also can query for + * more than one QP. */ #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND UINT32_C(0x91) /* QP error notification event. */ @@ -69949,6 +76984,236 @@ typedef struct creq_qp_error_notification { uint8_t req_slow_path_state; /* requestor error reason */ uint8_t req_err_state_reason; + /* No error. */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR UINT32_C(0x0) + /* + * Requester detected opcode error. + * * First, only, middle, last for incoming RDMA read + * responses are improperly ordered with respect to previous + * (PSN) packet. + * * First or middle packet is not full MTU size. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR UINT32_C(0x1) + /* + * Transport timeout retry limit exceeded. + * The requestor retried the same unacked PSN request packet + * too many times. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT UINT32_C(0x2) + /* + * RNR NAK retry limit exceeded. + * The requestor received an RNR NAK with the same NAK PSN + * too many times. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT UINT32_C(0x3) + /* + * NAK arrival, When NAK code is 1, Invalid Request. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 UINT32_C(0x4) + /* + * NAK arrival, When NAK code is 2, Remote Access Error. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 UINT32_C(0x5) + /* + * NAK arrival, When NAK code is 3, Remote Operational Error. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 UINT32_C(0x6) + /* + * NAK arrival. When NAK code is 4, Invalid RD Request. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 UINT32_C(0x7) + /* + * Local memory error. + * An SGE described an inaccessible memory. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR UINT32_C(0x8) + /* + * Local memory error. + * An SGE described an inaccessible memory. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR UINT32_C(0x9) + /* + * Read response length error. + * The read response payload size does not match the read + * length of the request. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH UINT32_C(0xa) + /* + * Invalid read response. + * A read response arrived and had a PSN that was not in the + * reply range of any outstanding read request on the ORRQ. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP UINT32_C(0xb) + /* + * Illegal bind. + * * No MW with the specified R_Key exists. + * * No MR with the specified L_Key exists. + * * A bind request was performed on a window that was already + * bound. + * * A bind request was performed for an underlying MR that + * is not registered. + * * A bind request was performed for a memory area that exceeds + * the range of the underlying MR. + * * A bind request was performed with a set of permissions + * that are looser than the permissions of the underlying MR. + * * Domain error MW - When QP's PD does not match MW PD. + * * Domain error MR - When QP's PD does not match parent MR's + * PD. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND UINT32_C(0xc) + /* + * Illegal fast register. + * * No MR with the specified L_Key exists. + * * A fast register request was performed on a non- + * physical MR. + * * A fast register request was performed on a physical MR + * that is already registered. + * * A fast register request was performed on a physical MR + * that does not have a page list allocated (has not been + * initialized). + * * The number of pages being registered exceeds the capacity + * of the physical MR. + * * The length of the registration is not possible with the + * actual number of pages provided. + * * Domain error - when QP's PD does not match PMR PD. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG UINT32_C(0xd) + /* + * Illegal invalidate. + * * No MR with the specified L_Key exists. + * * No MW with the specified R_Key exists. + * * An invalidate was performed against a non-physical MR. + * * An invalidate was performed against a physical MR that + * is not registered. + * * An invalidate was performed against a MW that is not + * bound. + * * The PD of the MR/MW being invalidated does not match the PD + * of the QP. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE UINT32_C(0xe) + /* + * Completion Error. + * No CQE space available on queue, or CQ not in VALID state. + * This is a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR UINT32_C(0xf) + /* + * Local memory error while retransmitting WQE. + * An SQ SGE described an inaccessible memory. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR UINT32_C(0x10) + /* + * Problem found in the format of a WQE in the SQ. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR UINT32_C(0x11) + /* + * Problem was found in the format of an ORRQ entry. + * This is a RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR UINT32_C(0x12) + /* + * A UD send attempted to use an invalid AVID. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR UINT32_C(0x13) + /* + * A UD send attempted to use an AVID that is outside of its + * QP's protection domain. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR UINT32_C(0x14) + /* + * A load error occurred on an attempt to load the CQ Context. + * This is a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR UINT32_C(0x15) + /* + * There was an attempt to process a WQE from the SQ that + * corresponds to an operation that is unsupported for the + * corresponding QP. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR UINT32_C(0x16) + /* + * There was an attempt to process a WQE from the SQ that + * corresponds to an operation that is unsupported for the + * corresponding QP, according to the supported_operations QPC + * field. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR UINT32_C(0x17) + /* + * A fatal error was detected on an attempt to read from + * or write to PCIe on the transmit side. This error is + * detected by the TX side (or CAGR), but has the priority + * of a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR UINT32_C(0x18) + /* + * A fatal error was detected on an attempt to read from + * or write to PCIe on the receive side. This error is detected + * by the RX side (or CAGR), but has the priority of a + * Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR UINT32_C(0x19) + /* + * When processing a WQE from the SQ, TWE detected an error + * such that the wqe_size given in the header is larger than + * the delta between sq_work_idx and sq_prod_idx. This error + * has priority over the non-error case that occurs when TWE + * detects that it simply doesn't have enough slots fetched + * to execute the WQE during the current residency. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR UINT32_C(0x1a) + /* + * When reading the MSN table to initiate HW retransmit, RWE + * found that to_retransmit_psn was not within the range defined + * by start_psn and next_psn in the corresponding MSN table + * entry. To_retransmit_psn must be greater than or equal to + * start_psn and less than next_psn in order for the range check + * to succeed. + * This is a RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR UINT32_C(0x1b) + /* + * While retransmitting, TWE detected one of several possible + * error detection scenarios related to the improper setup of + * retransmission. These include a category or errors known as + * retx_end_error where the retransmission end does not line up + * sequentially with the WQE index and PSN upon continuing on + * with the regular transmission that follows the + * retransmission. It also includes the error condition in which + * the retransmission Work Request has gen_dup_read_request set + * and the WQE fetched by TWE is not an RDMA Read or Atomic WQE. + * Please see TWE requirements for a full list of the various + * possible retransmit setup error cases. These error cases + * apply to H/W and F/W retransmission, alike. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR UINT32_C(0x1c) + /* + * An express doorbell was posted that overflowed the SQ. The + * doorbell is dropped, along with all subsequent doorbells for + * this SQ. This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW UINT32_C(0x1d) + #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_LAST CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW /* QP context id */ uint32_t xid; uint8_t v; @@ -69966,6 +77231,211 @@ typedef struct creq_qp_error_notification { /* responder slow path state */ uint8_t res_slow_path_state; uint8_t res_err_state_reason; + /* No error. */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR UINT32_C(0x0) + /* + * Incoming Send, RDMA write, or RDMA read exceeds the maximum + * transfer length. Detected on RX first and only packets for + * write. Detected on RX request for read. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX UINT32_C(0x1) + /* + * RDMA write payload size does not match write length. Detected + * when total write payload is not equal to the RDMA write + * length that was given in the first or only packet of the + * request. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH UINT32_C(0x2) + /* + * Send payload exceeds RQ/SRQ WQE buffer capacity. The total + * send payload that arrived is more than the size of the WQE + * buffer that was fetched from the RQ/SRQ. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE UINT32_C(0x3) + /* + * Responder detected opcode error. + * * First, only, middle, last or incoming requests are + * improperly ordered with respect to previous (PSN) packet. + * * First or middle packet is not full MTU size. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR UINT32_C(0x4) + /* + * PSN sequence error retry limit exceeded. + * The responder encountered a PSN sequence error for the + * same PSN too many times. This can occur via implicit or + * explicit NAK. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT UINT32_C(0x5) + /* + * Invalid R_Key. + * An incoming request contained an R_Key that did not reference + * a valid MR/MW. This error may be detected by the RX engine + * for RDMA write or by the TX engine for RDMA read + * (detected while servicing IRRQ). + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY UINT32_C(0x6) + /* + * Domain error. + * An incoming request specified an R_Key which + * referenced a MR/MW that was not in the same PD as the QP on + * which the request arrived. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR UINT32_C(0x7) + /* + * No permission. + * An incoming request contained an R_Key that referenced a + * MR/MW which did not have the access permission needed for + * the operation. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION UINT32_C(0x8) + /* + * Range error. + * An incoming request had a combination of R_Key,VA, and + * length that was out of bounds of the associated MR/MW. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR UINT32_C(0x9) + /* + * Invalid R_Key. + * An incoming request contained an R_Key that did not + * reference a valid MR/MW. This error may be detected + * by the RX engine for RDMA write or by the TX engine + * for RDMA read (detected while servicing IRRQ). + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY UINT32_C(0xa) + /* + * Domain error. + * An incoming request specified an R_Key which referenced + * a MR/MW that was not in the same PD as the QP on + * which the request arrived. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR UINT32_C(0xb) + /* + * No permission. + * An incoming request contained an R_Key that referenced a + * MR/MW which did not have the access permission needed for + * the operation. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION UINT32_C(0xc) + /* + * Range error. + * An incoming request had a combination of R_Key, VA, and + * length that was out of bounds of the associated MR/MW. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR UINT32_C(0xd) + /* + * IRRQ overflow. + * The peer sent us more RDMA read or atomic requests than + * the negotiated maximum. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW UINT32_C(0xe) + /* + * Unsupported opcode. + * The peer sent us a request with an opcode for a request + * type that is not supported on this QP. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE UINT32_C(0xf) + /* + * Unaligned atomic operation. The VA of an atomic request + * is on a memory boundary that prevents atomic execution. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC UINT32_C(0x10) + /* + * Remote invalidate error. + * A send with invalidate request arrived in which the + * R_Key to invalidate did not describe a MR/MW which could + * be invalidated. RQ WQE completes with error status. + * This error is only reported if the send operation did + * not fail. If the send operation failed then the remote + * invalidate error is not reported. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE UINT32_C(0x11) + /* + * Local memory error. An RQ/SRQ SGE described an inaccessible + * memory. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR UINT32_C(0x12) + /* + * SRQ in error. The QP is moving to error state because it + * found SRQ it uses in error. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR UINT32_C(0x13) + /* + * Completion error. No CQE space available on queue or CQ not + * in VALID state. + * This is a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR UINT32_C(0x14) + /* + * Invalid R_Key while resending responses to duplicate request. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY UINT32_C(0x15) + /* + * Problem was found in the format of a WQE in the RQ/SRQ. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR UINT32_C(0x16) + /* + * Problem was found in the format of an IRRQ entry. + * This is a TX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR UINT32_C(0x17) + /* + * A load error occurred on an attempt to load the CQ Context. + * This is a Completion Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR UINT32_C(0x18) + /* + * A load error occurred on an attempt to load the SRQ Context. + * This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR UINT32_C(0x19) + /* + * A fatal error was detected on an attempt to read from or + * write to PCIe on the transmit side. This error is detected + * by the TX side, but has the priority of a Completion + * Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR UINT32_C(0x1b) + /* + * A fatal error was detected on an attempt to read from or + * write to PCIe on the receive side. This error is detected + * by the RX side (or CAGR), but has the priority of a Completion + * Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR UINT32_C(0x1c) + /* + * When searching the IRRQ to respond to a duplicate request, + * RWE could not find the duplicate request in the entire IRRQ. + * This is a RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND UINT32_C(0x1d) + /* + * An express doorbell was posted that overflowed the RQ. The + * doorbell is dropped, along with all subsequent doorbells for + * this RQ. This is an RX Detected Error. + */ + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW UINT32_C(0x1e) + #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_LAST CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW /* * Final SQ Consumer Index value. Any additional SQ WQEs will * have to be completed by the user provider. @@ -70036,78 +77506,165 @@ typedef struct sq_base { /* This field defines the type of SQ WQE. */ uint8_t wqe_type; /* Send */ - #define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0) + #define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0) /* * Send with Immediate * * Allowed only on reliable connection (RC) and * unreliable datagram (UD) SQs. */ - #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1) + #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1) /* * Send with Invalidate. * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2) + #define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2) /* * RDMA Write. * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4) + #define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4) /* * RDMA Write with Immediate. * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5) + #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5) /* * RDMA Read. * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6) + #define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6) /* * Atomic Compare/Swap. * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8) + #define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8) /* * Atomic Fetch/Add. * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb) + #define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb) /* * Local Invalidate. * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc) + #define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc) /* * FR-PMR (Fast Register Physical Memory Region) * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd) + #define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd) /* * Memory Bind * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe) + #define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe) /* * FR-PPMR (Fast Register Proxy Physical Memory Region) * * Allowed only on reliable connection (RC) SQs. */ - #define SQ_BASE_WQE_TYPE_FR_PPMR UINT32_C(0xf) - #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR + #define SQ_BASE_WQE_TYPE_FR_PPMR UINT32_C(0xf) + /* Send V3 */ + #define SQ_BASE_WQE_TYPE_SEND_V3 UINT32_C(0x10) + /* + * Send with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11) + /* + * Send with Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12) + /* + * UD Send V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_BASE_WQE_TYPE_UDSEND_V3 UINT32_C(0x13) + /* + * UD Send with Immediate V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_BASE_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14) + /* + * RDMA Write V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15) + /* + * RDMA Write with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16) + /* + * RDMA Read V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17) + /* + * Atomic Compare/Swap V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18) + /* + * Atomic Fetch/Add V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19) + /* + * Local Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a) + /* + * FR-PMR (Fast Register Physical Memory Region) V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b) + /* + * Memory Bind V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BASE_WQE_TYPE_BIND_V3 UINT32_C(0x1c) + /* RawEth/QP1 Send V3 */ + #define SQ_BASE_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d) + /* Change UDP Source Port V3 */ + #define SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e) + #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 uint8_t unused_0[7]; } sq_base_t, *psq_base_t; +/* + * Most SQ WQEs contain SGEs used to define the SGL used to map payload + * data in host memory. The number of SGE structures is defined by the + * wqe_size field. SGE structures are aligned to 16B boundaries. + * + * In backward-compatible modes there can be 2, 4 or 6 SGEs (based on + * the mode). In variable-sized WQE mode there can be 0-30 SGE + * structures. + */ /* sq_sge (size:128b/16B) */ typedef struct sq_sge { @@ -70281,7 +77838,7 @@ typedef struct sq_send { * valid 16 bytes units other than the WQE structure can be * SGEs (Scatter Gather Elements) OR inline data. * - * While this field defines the valid WQE size. The actual + * While this field defines the valid WQE size. The actual * total WQE size is always 128B. */ uint8_t wqe_size; @@ -70297,7 +77854,7 @@ typedef struct sq_send { uint32_t length; /* * When in the SQ of a UD QP, indicates the q_key to be used in - * the transmitted packet. However, if the most significant bit + * the transmitted packet. However, if the most significant bit * of this field is set, then the q_key will be taken from QP * context, rather than from this field. * @@ -70336,7 +77893,7 @@ typedef struct sq_send { * SGEs based on the wqe_size field. * * When inline=1, this area is filled with payload data for the - * send based on the length_or_AVID field. Bits [7:0] of word 0 + * send based on the length_or_AVID field. Bits [7:0] of word 0 * hold the first byte to go out on the wire. */ uint32_t data[24]; @@ -70417,7 +77974,7 @@ typedef struct sq_send_hdr { * valid 16 bytes units other than the WQE structure can be * SGEs (Scatter Gather Elements) OR inline data. * - * While this field defines the valid WQE size. The actual + * While this field defines the valid WQE size. The actual * total WQE size is always 128B. */ uint8_t wqe_size; @@ -70433,7 +77990,7 @@ typedef struct sq_send_hdr { uint32_t length; /* * When in the SQ of a UD QP, indicates the q_key to be used in - * the transmitted packet. However, if the most significant bit + * the transmitted packet. However, if the most significant bit * of this field is set, then the q_key will be taken from QP * context, rather than from this field. * @@ -70516,7 +78073,7 @@ typedef struct sq_send_raweth_qp1 { * valid 16 bytes units other than the WQE structure can be * SGEs (Scatter Gather Elements) OR inline data. * - * While this field defines the valid WQE size. The actual + * While this field defines the valid WQE size. The actual * total WQE size is always 128B. */ uint8_t wqe_size; @@ -70537,7 +78094,7 @@ typedef struct sq_send_raweth_qp1 { */ #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) /* - * If set to 1, the controller replaces the IP checksum of the + * If set to 1, the controller replaces the IP checksum of the * normal packets, or the inner IP checksum of the encapsulated * packets with the hardware calculated IP checksum for the * packet associated with this descriptor. @@ -70551,9 +78108,9 @@ typedef struct sq_send_raweth_qp1 { * * This bit must be valid on the first BD of a packet. * - * Packet must be 64B or longer when this flag is set. It is not - * usefull to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already * has a valid Ethernet CRC on the packet. */ #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC UINT32_C(0x4) @@ -70567,7 +78124,7 @@ typedef struct sq_send_raweth_qp1 { /* * If set to 1, The controller replaces the tunnel IP checksum * field with hardware calculated IP checksum for the IP header - * of the packet associated with this descriptor. In case of + * of the packet associated with this descriptor. In case of * VXLAN, the controller also replaces the outer header UDP * checksum with hardware calculated UDP checksum for the packet * associated with this descriptor. @@ -70575,12 +78132,12 @@ typedef struct sq_send_raweth_qp1 { #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC UINT32_C(0x200) /* @@ -70660,7 +78217,7 @@ typedef struct sq_send_raweth_qp1 { * SGEs based on the wqe_size field. * * When inline=1, this area is filled with payload data for the - * send based on the length_or_AVID field. Bits [7:0] of word 0 + * send based on the length_or_AVID field. Bits [7:0] of word 0 * hold the first byte to go out on the wire. */ uint32_t data[24]; @@ -70713,7 +78270,7 @@ typedef struct sq_send_raweth_qp1_hdr { * valid 16 bytes units other than the WQE structure can be * SGEs (Scatter Gather Elements) OR inline data. * - * While this field defines the valid WQE size. The actual + * While this field defines the valid WQE size. The actual * total WQE size is always 128B. */ uint8_t wqe_size; @@ -70734,7 +78291,7 @@ typedef struct sq_send_raweth_qp1_hdr { */ #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) /* - * If set to 1, the controller replaces the IP checksum of the + * If set to 1, the controller replaces the IP checksum of the * normal packets, or the inner IP checksum of the encapsulated * packets with the hardware calculated IP checksum for the * packet associated with this descriptor. @@ -70748,9 +78305,9 @@ typedef struct sq_send_raweth_qp1_hdr { * * This bit must be valid on the first BD of a packet. * - * Packet must be 64B or longer when this flag is set. It is not - * usefull to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already * has a valid Ethernet CRC on the packet. */ #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC UINT32_C(0x4) @@ -70764,7 +78321,7 @@ typedef struct sq_send_raweth_qp1_hdr { /* * If set to 1, The controller replaces the tunnel IP checksum * field with hardware calculated IP checksum for the IP header - * of the packet associated with this descriptor. In case of + * of the packet associated with this descriptor. In case of * VXLAN, the controller also replaces the outer header UDP * checksum with hardware calculated UDP checksum for the packet * associated with this descriptor. @@ -70772,12 +78329,12 @@ typedef struct sq_send_raweth_qp1_hdr { #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC UINT32_C(0x200) /* @@ -70909,7 +78466,7 @@ typedef struct sq_rdma { #define SQ_RDMA_FLAGS_SE UINT32_C(0x8) /* * Indicate that inline data is posted to the SQ following - * this WQE. This bit may be 1 only for write operations. + * this WQE. This bit may be 1 only for write operations. */ #define SQ_RDMA_FLAGS_INLINE UINT32_C(0x10) /* @@ -70928,7 +78485,7 @@ typedef struct sq_rdma { * valid 16 bytes units other than the WQE structure can be * SGEs (Scatter Gather Elements) OR inline data. * - * While this field defines the valid WQE size. The actual + * While this field defines the valid WQE size. The actual * total WQE size is always 128B. */ uint8_t wqe_size; @@ -70962,7 +78519,7 @@ typedef struct sq_rdma { * SGEs based on the wqe_size field. * * When inline=1, this area is filled with payload data for the - * write based on the length field. Bits [7:0] of word 0 + * write based on the length field. Bits [7:0] of word 0 * hold the first byte to go out on the wire. */ uint32_t data[24]; @@ -71023,7 +78580,7 @@ typedef struct sq_rdma_hdr { #define SQ_RDMA_HDR_FLAGS_SE UINT32_C(0x8) /* * Indicate that inline data is posted to the SQ following - * this WQE. This bit may be 1 only for write operations. + * this WQE. This bit may be 1 only for write operations. */ #define SQ_RDMA_HDR_FLAGS_INLINE UINT32_C(0x10) /* @@ -71042,7 +78599,7 @@ typedef struct sq_rdma_hdr { * valid 16 bytes units other than the WQE structure can be * SGEs (Scatter Gather Elements) OR inline data. * - * While this field defines the valid WQE size. The actual + * While this field defines the valid WQE size. The actual * total WQE size is always 128B. */ uint8_t wqe_size; @@ -71151,7 +78708,7 @@ typedef struct sq_atomic { /* * The first 16B of the data field must be filled with a single * SGE. This will be used to store the return value from the - * Atomic Ack response. The size of the single SGE must be 8B. + * Atomic Ack response. The size of the single SGE must be 8B. */ uint32_t data[24]; } sq_atomic_t, *psq_atomic_t; @@ -71410,8 +78967,8 @@ typedef struct sq_fr_pmr { */ #define SQ_FR_PMR_FLAGS_DEBUG_TRACE UINT32_C(0x40) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is * not allowed. */ uint8_t access_cntl; @@ -71580,20 +79137,21 @@ typedef struct sq_fr_pmr { #define SQ_FR_PMR_NUMLEVELS_SFT 6 /* * A zero level PBL means that the VA is the physical address used - * for the operation. No translation is done by the PTU. + * for the operation. No translation is done by the PTU. */ #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) /* * A one layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PBE values that point to actual pg_size physical pages. + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical pages. */ #define SQ_FR_PMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) /* * A two layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PDE values that in turn point to pbl_pg_size physical pages that contain - * PBE values that point to actual physical pages. + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size physical + * pages that contain PBE values that point to actual physical + * pages. */ #define SQ_FR_PMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2 @@ -71652,8 +79210,8 @@ typedef struct sq_fr_pmr_hdr { */ #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is * not allowed. */ uint8_t access_cntl; @@ -71822,20 +79380,21 @@ typedef struct sq_fr_pmr_hdr { #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6 /* * A zero level PBL means that the VA is the physical address used - * for the operation. No translation is done by the PTU. + * for the operation. No translation is done by the PTU. */ #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) /* * A one layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PBE values that point to actual pg_size physical pages. + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical pages. */ #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) /* * A two layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PDE values that in turn point to pbl_pg_size physical pages that contain - * PBE values that point to actual physical pages. + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size physical + * pages that contain PBE values that point to actual physical + * pages. */ #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 @@ -71892,8 +79451,8 @@ typedef struct sq_fr_ppmr { */ #define SQ_FR_PPMR_FLAGS_DEBUG_TRACE UINT32_C(0x40) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is * not allowed. */ uint8_t access_cntl; @@ -72066,20 +79625,21 @@ typedef struct sq_fr_ppmr { #define SQ_FR_PPMR_NUMLEVELS_SFT 6 /* * A zero level PBL means that the VA is the physical address used - * for the operation. No translation is done by the PTU. + * for the operation. No translation is done by the PTU. */ #define SQ_FR_PPMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) /* * A one layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PBE values that point to actual pg_size physical pages. + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical pages. */ #define SQ_FR_PPMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) /* * A two layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PDE values that in turn point to pbl_pg_size physical pages that contain - * PBE values that point to actual physical pages. + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size physical + * pages that contain PBE values that point to actual physical + * pages. */ #define SQ_FR_PPMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) #define SQ_FR_PPMR_NUMLEVELS_LAST SQ_FR_PPMR_NUMLEVELS_LAYER2 @@ -72138,8 +79698,8 @@ typedef struct sq_fr_ppmr_hdr { */ #define SQ_FR_PPMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is * not allowed. */ uint8_t access_cntl; @@ -72312,20 +79872,21 @@ typedef struct sq_fr_ppmr_hdr { #define SQ_FR_PPMR_HDR_NUMLEVELS_SFT 6 /* * A zero level PBL means that the VA is the physical address used - * for the operation. No translation is done by the PTU. + * for the operation. No translation is done by the PTU. */ #define SQ_FR_PPMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6) /* * A one layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PBE values that point to actual pg_size physical pages. + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical pages. */ #define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6) /* * A two layer translation is provided between the logical and - * physical address. The PBL points to a physical page that contains - * PDE values that in turn point to pbl_pg_size physical pages that contain - * PBE values that point to actual physical pages. + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size physical + * pages that contain PBE values that point to actual physical + * pages. */ #define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6) #define SQ_FR_PPMR_HDR_NUMLEVELS_LAST SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2 @@ -72388,8 +79949,8 @@ typedef struct sq_bind { */ #define SQ_BIND_FLAGS_DEBUG_TRACE UINT32_C(0x40) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is * not allowed. */ uint8_t access_cntl; @@ -72399,7 +79960,7 @@ typedef struct sq_bind { * Local Write Access. * * Local accesses are never allowed for memory windows, so this - * bit must always be zero in a bind WQE. If this bit is ever + * bit must always be zero in a bind WQE. If this bit is ever * set, the bind will fail with an errored completion. */ #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) @@ -72409,23 +79970,25 @@ typedef struct sq_bind { * Remote Write Access. * * Note that, if this bit is set, then the parent region to which - * the window is being bound must allow local writes. If this is not - * the case, then the bind will fail with an errored completion. + * the window is being bound must allow local writes. If this is + * not the case, then the bind will fail with an errored + * completion. */ #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) /* * Remote Atomic Access. * * Note that, if this bit is set, then the parent region to which - * the window is being bound must allow local writes. If this is not - * the case, then the bind will fail with an errored completion. + * the window is being bound must allow local writes. If this is + * not the case, then the bind will fail with an errored + * completion. */ #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) /* * Window Binding Allowed. * * It is never allowed to bind windows to windows, so this bit - * must always be zero in a bind WQE. If this bit is ever set, + * must always be zero in a bind WQE. If this bit is ever set, * the bind will fail with an errored completion. */ #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) @@ -72434,27 +79997,28 @@ typedef struct sq_bind { uint8_t mw_type_zero_based; /* * If this bit is set, then the newly-bound memory window will be - * zero-based. If clear, then the newly-bound memory window will be + * zero-based. If clear, then the newly-bound memory window will be * non-zero-based. */ #define SQ_BIND_ZERO_BASED UINT32_C(0x1) /* - * If type1 is specified, then this WQE performs a "bind memory window" - * operation on a type1 window. If type2 is specified, then this WQE - * performs a "post send bind memory window" operation on a type2 + * If type1 is specified, then this WQE performs a "bind memory + * window" operation on a type1 window. If type2 is specified, then + * this WQE performs a "post send bind memory window" operation on a + * type2 window. + * + * Note that the bind WQE cannot change the type of the memory * window. * - * Note that the bind WQE cannot change the type of the memory window. + * If a "bind memory window" operation is attempted on a memory + * window that was allocated as type2, then the bind will fail with + * an errored completion, as "bind memory window" is allowed only on + * type1 memory windows. * - * If a "bind memory window" operation is attempted on a memory window - * that was allocated as type2, then the bind will fail with an errored - * completion, as "bind memory window" is allowed only on type1 memory - * windows. - * - * Similarly, if a "post send bind memory window" operation is attempted - * on a memory window that was allocated as type1, then the bind will fail - * with an errored completions, as "post send bind memory window" is allowed - * only on type2 memory windows. + * Similarly, if a "post send bind memory window" operation is + * attempted on a memory window that was allocated as type1, then the + * bind will fail with an errored completions, as "post send bind + * memory window" is allowed only on type2 memory windows. */ #define SQ_BIND_MW_TYPE UINT32_C(0x2) /* Type 1 Bind Memory Window */ @@ -72541,8 +80105,8 @@ typedef struct sq_bind_hdr { */ #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40) /* - * This is the new access control for the MR. '1' means - * the operation is allowed. '0' means operation is + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is * not allowed. */ uint8_t access_cntl; @@ -72552,7 +80116,7 @@ typedef struct sq_bind_hdr { * Local Write Access. * * Local accesses are never allowed for memory windows, so this - * bit must always be zero in a bind WQE. If this bit is ever + * bit must always be zero in a bind WQE. If this bit is ever * set, the bind will fail with an errored completion. */ #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) @@ -72562,23 +80126,25 @@ typedef struct sq_bind_hdr { * Remote Write Access. * * Note that, if this bit is set, then the parent region to which - * the window is being bound must allow local writes. If this is not - * the case, then the bind will fail with an errored completion. + * the window is being bound must allow local writes. If this is + * not the case, then the bind will fail with an errored + * completion. */ #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) /* * Remote Atomic Access. * * Note that, if this bit is set, then the parent region to which - * the window is being bound must allow local writes. If this is not - * the case, then the bind will fail with an errored completion. + * the window is being bound must allow local writes. If this is + * not the case, then the bind will fail with an errored + * completion. */ #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) /* * Window Binding Allowed. * * It is never allowed to bind windows to windows, so this bit - * must always be zero in a bind WQE. If this bit is ever set, + * must always be zero in a bind WQE. If this bit is ever set, * the bind will fail with an errored completion. */ #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) @@ -72587,27 +80153,28 @@ typedef struct sq_bind_hdr { uint8_t mw_type_zero_based; /* * If this bit is set, then the newly-bound memory window will be - * zero-based. If clear, then the newly-bound memory window will be + * zero-based. If clear, then the newly-bound memory window will be * non-zero-based. */ #define SQ_BIND_HDR_ZERO_BASED UINT32_C(0x1) /* - * If type1 is specified, then this WQE performs a "bind memory window" - * operation on a type1 window. If type2 is specified, then this WQE - * performs a "post send bind memory window" operation on a type2 + * If type1 is specified, then this WQE performs a "bind memory + * window" operation on a type1 window. If type2 is specified, then + * this WQE performs a "post send bind memory window" operation on a + * type2 window. + * + * Note that the bind WQE cannot change the type of the memory * window. * - * Note that the bind WQE cannot change the type of the memory window. + * If a "bind memory window" operation is attempted on a memory + * window that was allocated as type2, then the bind will fail with + * an errored completion, as "bind memory window" is allowed only on + * type1 memory windows. * - * If a "bind memory window" operation is attempted on a memory window - * that was allocated as type2, then the bind will fail with an errored - * completion, as "bind memory window" is allowed only on type1 memory - * windows. - * - * Similarly, if a "post send bind memory window" operation is attempted - * on a memory window that was allocated as type1, then the bind will fail - * with an errored completions, as "post send bind memory window" is allowed - * only on type2 memory windows. + * Similarly, if a "post send bind memory window" operation is + * attempted on a memory window that was allocated as type1, then the + * bind will fail with an errored completions, as "post send bind + * memory window" is allowed only on type2 memory windows. */ #define SQ_BIND_HDR_MW_TYPE UINT32_C(0x2) /* Type 1 Bind Memory Window */ @@ -72639,6 +80206,2736 @@ typedef struct sq_bind_hdr { uint8_t reserved24[3]; } sq_bind_hdr_t, *psq_bind_hdr_t; +/* + * This V3 version of structure is not accessible from host software, but is documented here (in the SW section) anyway. + * This is the MSN Table (located in IQM). The table is written by the RoCE transmitter when sending wire operation WQEs. It is used to provide the RoCE receiver with information about the SQ WQEs in order to make requester completions and to perform requester HW retransmission. The number of entries in the table is configured in the QPC and must be equal to the maximum number of WQEs that can be present in the SQ at one time, rounded up to the nearest power of two. + */ +/* sq_msn_search_v3 (size:128b/16B) */ + +typedef struct sq_msn_search_v3 { + uint64_t idx_psn; + /* Start PSN of the WQE. */ + #define SQ_MSN_SEARCH_V3_START_PSN_MASK UINT32_C(0xffffff) + #define SQ_MSN_SEARCH_V3_START_PSN_SFT 0 + /* Next PSN. Equal to the start PSN of the next WQE. */ + #define SQ_MSN_SEARCH_V3_NEXT_PSN_MASK UINT32_C(0xffffff000000)L + #define SQ_MSN_SEARCH_V3_NEXT_PSN_SFT 24 + /* + * Start index. For variable-size WQEs, this field indicates the + * starting slot index that corresponds to the WQE. In + * backward-compatible mode, this is the starting WQE index. + */ + #define SQ_MSN_SEARCH_V3_START_IDX_MASK UINT32_C(0xffff000000000000)L + #define SQ_MSN_SEARCH_V3_START_IDX_SFT 48 + /* + * This value will be returned in the completion if the completion + * is signaled. + */ + uint32_t wqe_opaque; + /* The size of the WQE in units of 16B chunks. */ + uint8_t wqe_size; + uint8_t signal; + /* Set if completion signaling is requested. */ + #define SQ_MSN_SEARCH_V3_SGNLD UINT32_C(0x1) + /* + * Set if at least one signaled local memory operation WQE is + * present in the SQ between the previous wire-operation WQE + * and this WQE. + */ + #define SQ_MSN_SEARCH_V3_PREV_SGNLD_LOCAL_MEM_WQE UINT32_C(0x2) + uint16_t reserved; +} sq_msn_search_v3_t, *psq_msn_search_v3_t; + +/* SQ Send WQE V3 for RC SQs. */ +/* sq_send_v3 (size:1024b/128B) */ + +typedef struct sq_send_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send V3 */ + #define SQ_SEND_V3_WQE_TYPE_SEND_V3 UINT32_C(0x10) + /* + * Send with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_V3_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11) + /* + * Send with Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12) + #define SQ_SEND_V3_WQE_TYPE_LAST SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_SEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + */ + #define SQ_SEND_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_SEND_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_SEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_SEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * Note: Since the WQE header consumes only one slot (16 bytes) + * for this type of WQE, and the maximum number of SGEs supported + * by the device is 30, this field must never exceed 31. + */ + #define SQ_SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_SEND_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_SEND_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Either invalidate key (R_Key of the remote host) that will + * be send with IETH (Invalidate ETH) if wqe_type is of Send + * with Invalidate, or immediate value that will be sent with + * ImmDt header if wqe_type is Send with Immediate. + */ + uint32_t inv_key_or_imm_data; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_SEND_V3_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 30 SGEs + * based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * send. Length of data is described in the inline_length field. + * Bits [7:0] of word 0 hold the first byte to go out on the wire. + */ + uint32_t data[28]; +} sq_send_v3_t, *psq_send_v3_t; + +/* Send SQ WQE V3 header. */ +/* sq_send_hdr_v3 (size:128b/16B) */ + +typedef struct sq_send_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Send V3 */ + #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_V3 UINT32_C(0x10) + /* + * Send with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11) + /* + * Send with Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12) + #define SQ_SEND_HDR_V3_WQE_TYPE_LAST SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_SEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_SEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + */ + #define SQ_SEND_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_SEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_SEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_SEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * Note: Since the WQE header consumes only one slot (16 bytes) + * for this type of WQE, and the maximum number of SGEs supported + * by the device is 30, this field must never exceed 31. + */ + #define SQ_SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_SEND_HDR_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_SEND_HDR_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Either invalidate key (R_Key of the remote host) that will + * be send with IETH (Invalidate ETH) if wqe_type is of Send + * with Invalidate, or immediate value that will be sent with + * ImmDt header if wqe_type is Send with Immediate. + */ + uint32_t inv_key_or_imm_data; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_SEND_HDR_V3_TIMESTAMP_SFT 0 +} sq_send_hdr_v3_t, *psq_send_hdr_v3_t; + +/* SQ WQE V3 for Raw Ethernet and QP1 */ +/* sq_rawqp1send_v3 (size:1024b/128B) */ + +typedef struct sq_rawqp1send_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* RawEth/QP1 Send V3 */ + #define SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d) + #define SQ_RAWQP1SEND_V3_WQE_TYPE_LAST SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_RAWQP1SEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RAWQP1SEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_RAWQP1SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_RAWQP1SEND_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_RAWQP1SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_RAWQP1SEND_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet will be ignored. + */ + uint16_t lflags; + /* + * If set to 1, the controller replaces the TCP/UPD checksum + * fields of normal TCP/UPD checksum, or the inner TCP/UDP + * checksum field of the encapsulated TCP/UDP packets with the + * hardware calculated TCP/UDP checksum for the packet associated + * with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the + * normal packets, or the inner IP checksum of the encapsulated + * packets with the hardware calculated IP checksum for the + * packet associated with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC + * to the end of the frame. + * + * This bit must be valid on the first BD of a packet. + * + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already + * has a valid Ethernet CRC on the packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, The controller replaces the tunnel IP checksum + * field with hardware calculated IP checksum for the IP header + * of the packet associated with this descriptor. In case of + * VXLAN, the controller also replaces the outer header UDP + * checksum with hardware calculated UDP checksum for the packet + * associated with this descriptor. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * If set to 1, The controller replaces the Outer-tunnel IP + * checksum field with hardware calculated IP checksum for the IP + * header of the packet associated with this descriptor. + * + * For outer UDP checksum, it will be the following behavior for + * all cases independent of settings of inner LSO and checksum + * offload BD flags: + * + * - If outer UDP checksum is 0, then do not update it. + * - If outer UDP checksum is non zero, then the hardware should + * compute and update it. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_OT_IP_CHKSUM UINT32_C(0x20) + /* + * If set to '1', then the RoCE ICRC will be appended to the + * packet. Packet must be a valid RoCE format packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the + * packet. Packet must be a valid FCoE format packet. + */ + #define SQ_RAWQP1SEND_V3_LFLAGS_FCOE_CRC UINT32_C(0x200) + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action; + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action_high; + /* + * This value selects bits 25:16 of the CFA action to perform on + * the packet. See the cfa_action field for more information. + */ + #define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff) + #define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_SFT 0 + uint16_t reserved_2; + /* + * This value is action meta-data that defines CFA edit operations + * that are done in addition to any action editing. + */ + uint32_t cfa_meta; + /* When key=1, This is the VLAN tag VID value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_SFT 0 + /* When key=1, This is the VLAN tag DE value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key=1, This is the VLAN tag PRI value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_SFT 13 + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_LAST SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed + * on the packet. + * + * This value must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_SFT 28 + /* No editing */ + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). + * - meta[15:12] - PRI/DE value. + * - meta[11:0] - VID value. + */ + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define SQ_RAWQP1SEND_V3_CFA_META_KEY_LAST SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RAWQP1SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RAWQP1SEND_V3_TIMESTAMP_SFT 0 + uint64_t reserved_3; + /* + * When inline=0, then this area is filled with from 1 to 6 SGEs + * based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * send. Length of data is described in the inline_length field. + * Bits [7:0] of word 0 hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_rawqp1send_v3_t, *psq_rawqp1send_v3_t; + +/* SQ WQE V3 structure for Raw Ethernet and QP1 SQs. */ +/* sq_rawqp1send_hdr_v3 (size:256b/32B) */ + +typedef struct sq_rawqp1send_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* RawEth/QP1 Send V3 */ + #define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d) + #define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_LAST SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + * + * This flag must be zero for a QP1 send. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RAWQP1SEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet will be ignored. + */ + uint16_t lflags; + /* + * If set to 1, the controller replaces the TCP/UPD checksum + * fields of normal TCP/UPD checksum, or the inner TCP/UDP + * checksum field of the encapsulated TCP/UDP packets with the + * hardware calculated TCP/UDP checksum for the packet associated + * with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the + * normal packets, or the inner IP checksum of the encapsulated + * packets with the hardware calculated IP checksum for the + * packet associated with this descriptor. + * + * This bit must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC + * to the end of the frame. + * + * This bit must be valid on the first BD of a packet. + * + * Packet must be 64B or longer when this flag is set. It is not + * useful to use this bit with any form of TX offload such as + * CSO or LSO. The intent is that the packet from the host already + * has a valid Ethernet CRC on the packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, The controller replaces the tunnel IP checksum + * field with hardware calculated IP checksum for the IP header + * of the packet associated with this descriptor. In case of + * VXLAN, the controller also replaces the outer header UDP + * checksum with hardware calculated UDP checksum for the packet + * associated with this descriptor. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * If set to 1, The controller replaces the Outer-tunnel IP + * checksum field with hardware calculated IP checksum for the IP + * header of the packet associated with this descriptor. + * + * For outer UDP checksum, it will be the following behavior for + * all cases independent of settings of inner LSO and checksum + * offload BD flags: + * + * - If outer UDP checksum is 0, then do not update it. + * - If outer UDP checksum is non zero, then the hardware should + * compute and update it. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_OT_IP_CHKSUM UINT32_C(0x20) + /* + * If set to '1', then the RoCE ICRC will be appended to the + * packet. Packet must be a valid RoCE format packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the + * packet. Packet must be a valid FCoE format packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_FCOE_CRC UINT32_C(0x200) + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action; + /* + * This value selects a CFA action to perform on the packet. + * Set this value to zero if no CFA action is desired. + * + * This value must be valid on the first BD of a packet. + */ + uint16_t cfa_action_high; + /* + * This value selects bits 25:16 of the CFA action to perform on + * the packet. See the cfa_action field for more information. + */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff) + #define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_SFT 0 + uint16_t reserved_2; + /* + * This value is action meta-data that defines CFA edit operations + * that are done in addition to any action editing. + */ + uint32_t cfa_meta; + /* When key=1, This is the VLAN tag VID value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_SFT 0 + /* When key=1, This is the VLAN tag DE value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key=1, This is the VLAN tag PRI value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_SFT 13 + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_LAST SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG + /* When key=1, This is the VLAN tag TPID select value. */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed + * on the packet. + * + * This value must be valid on the first BD of a packet. + */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_SFT 28 + /* No editing */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). + * - meta[15:12] - PRI/DE value. + * - meta[11:0] - VID value. + */ + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_LAST SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_SFT 0 + uint64_t reserved_3; +} sq_rawqp1send_hdr_v3_t, *psq_rawqp1send_hdr_v3_t; + +/* SQ Send WQE V3 for UD SQs. */ +/* sq_udsend_v3 (size:1024b/128B) */ + +typedef struct sq_udsend_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * UD Send V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_UDSEND_V3_WQE_TYPE_UDSEND_V3 UINT32_C(0x13) + /* + * UD Send with Immediate V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14) + #define SQ_UDSEND_V3_WQE_TYPE_LAST SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_UDSEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_UDSEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_UDSEND_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + */ + #define SQ_UDSEND_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_UDSEND_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_UDSEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_UDSEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_UDSEND_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_UDSEND_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_UDSEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_UDSEND_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Immediate value that will be sent with ImmDt header if wqe_type is + * UD Send with Immediate. + */ + uint32_t imm_data; + /* + * When in the SQ of a UD QP, indicates the q_key to be used in + * the transmitted packet. However, if the most significant bit + * of this field is set, then the q_key will be taken from QP + * context, rather than from this field. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t q_key; + /* + * When in the SQ of a UD QP, indicates the destination QP to be + * used in the transmitted packet. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t dst_qp; + #define SQ_UDSEND_V3_DST_QP_MASK UINT32_C(0xffffff) + #define SQ_UDSEND_V3_DST_QP_SFT 0 + uint32_t avid; + /* + * If the serv_type is 'UD', then this field supplies the AVID + * (Address Vector ID). + */ + #define SQ_UDSEND_V3_AVID_MASK UINT32_C(0x3ff) + #define SQ_UDSEND_V3_AVID_SFT 0 + uint32_t reserved2; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_UDSEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_UDSEND_V3_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 30 SGEs + * based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the + * send. Length of data is described in the inline_length field. + * Bits [7:0] of word 0 hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_udsend_v3_t, *psq_udsend_v3_t; + +/* SQ WQE V3 header for UD SQs. */ +/* sq_udsend_hdr_v3 (size:256b/32B) */ + +typedef struct sq_udsend_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * UD Send V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_V3 UINT32_C(0x13) + /* + * UD Send with Immediate V3 + * + * Allowed only on unreliable datagram (UD) SQs. + */ + #define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14) + #define SQ_UDSEND_HDR_V3_WQE_TYPE_LAST SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled completion + * the controller should not generate a CQE unless there was + * an error. This refers to the CQE on the sender side. (The se + * flag refers to the receiver side). + */ + #define SQ_UDSEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic WQEs + * on the SQ before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_UDSEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all + * previous SQ's WQEs before executing this WQE. + * + * This flag must be zero for a UD send. + */ + #define SQ_UDSEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event flag. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, i.e. + * CNQE. + */ + #define SQ_UDSEND_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ in the data + * area of this WQE. + */ + #define SQ_UDSEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_UDSEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_UDSEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_UDSEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_UDSEND_HDR_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_UDSEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_UDSEND_HDR_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Immediate value that will be sent with ImmDt header if wqe_type is + * UD Send with Immediate. + */ + uint32_t imm_data; + /* + * When in the SQ of a UD QP, indicates the q_key to be used in + * the transmitted packet. However, if the most significant bit + * of this field is set, then the q_key will be taken from QP + * context, rather than from this field. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t q_key; + /* + * When in the SQ of a UD QP, indicates the destination QP to be + * used in the transmitted packet. + * + * When in the SQ of a non-UD QP, this field is reserved and + * should be filled with zeros. + */ + uint32_t dst_qp; + #define SQ_UDSEND_HDR_V3_DST_QP_MASK UINT32_C(0xffffff) + #define SQ_UDSEND_HDR_V3_DST_QP_SFT 0 + uint32_t avid; + /* + * If the serv_type is 'UD', then this field supplies the AVID + * (Address Vector ID). + */ + #define SQ_UDSEND_HDR_V3_AVID_MASK UINT32_C(0x3ff) + #define SQ_UDSEND_HDR_V3_AVID_SFT 0 + uint32_t reserved2; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_UDSEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_UDSEND_HDR_V3_TIMESTAMP_SFT 0 +} sq_udsend_hdr_v3_t, *psq_udsend_hdr_v3_t; + +/* SQ RDMA WQE V3 for RC SQs. */ +/* sq_rdma_v3 (size:1024b/128B) */ + +typedef struct sq_rdma_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * RDMA Write V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_V3_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15) + /* + * RDMA Write with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16) + /* + * RDMA Read V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17) + #define SQ_RDMA_V3_WQE_TYPE_LAST SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_RDMA_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_RDMA_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_RDMA_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. + */ + #define SQ_RDMA_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ following + * this WQE. This bit may be 1 only for write operations. + */ + #define SQ_RDMA_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RDMA_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RDMA_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_RDMA_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_RDMA_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_RDMA_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_RDMA_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Immediate data - valid for RDMA Write with immediate and + * causes the controller to add immDt header with this value + */ + uint32_t imm_data; + uint32_t reserved2; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* + * R_Key provided by remote node when the connection was + * established and placed in the RETH header. It identify the + * MRW on the remote host + */ + uint32_t remote_key; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RDMA_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RDMA_V3_TIMESTAMP_SFT 0 + /* + * When inline=0, then this area is filled with from 1 to 30 SGEs + * based on the wqe_size field. + * + * When inline=1, this area is filled with payload data for the send. + * Length of data is described in the inline_length field. Bits [7:0] + * of word 0 hold the first byte to go out on the wire. + */ + uint32_t data[24]; +} sq_rdma_v3_t, *psq_rdma_v3_t; + +/* SQ RDMA WQE V3 header for RC SQs. */ +/* sq_rdma_hdr_v3 (size:256b/32B) */ + +typedef struct sq_rdma_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * RDMA Write V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15) + /* + * RDMA Write with Immediate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16) + /* + * RDMA Read V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17) + #define SQ_RDMA_HDR_V3_WQE_TYPE_LAST SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_RDMA_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_RDMA_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_RDMA_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. + */ + #define SQ_RDMA_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * Indicate that inline data is posted to the SQ following + * this WQE. This bit may be 1 only for write operations. + */ + #define SQ_RDMA_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * If set to 1, then the timestamp from the WQE is used. If + * cleared to 0, then TWE provides the timestamp. + */ + #define SQ_RDMA_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_RDMA_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The number of 16 bytes chunks of data including this first + * word of the request that are a valid part of the request. The + * valid 16 bytes units other than the WQE structure can be + * SGEs (Scatter Gather Elements) OR inline data. + * + * This field shall never exceed 32 for WQEs of this type. + */ + #define SQ_RDMA_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_RDMA_HDR_V3_WQE_SIZE_SFT 0 + uint8_t inline_length; + /* + * When inline flag is '1', this field determines the number of + * bytes that are valid in the last 16B unit of the inline WQE. + * Zero means all 16 bytes are valid. One means only bits 7:0 of + * the last 16B unit are valid. This means the total size of the + * inline data is determined by a combination of the wqe_size field + * and this inline_length field. + * + * `inline_size = ((wqe_size - 1) * 16) - data_offset_in_bytes + + * ((inline_length == 0 ) ? 16 : inline_length) + * + * Where data_offset_in_bytes is the offset within the WQE where + * the data field starts. + * + * Note that this field is not applicable for zero-length inline + * WQEs. + */ + #define SQ_RDMA_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf) + #define SQ_RDMA_HDR_V3_INLINE_LENGTH_SFT 0 + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Immediate data - valid for RDMA Write with immediate and + * causes the controller to add immDt header with this value + */ + uint32_t imm_data; + uint32_t reserved2; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* + * R_Key provided by remote node when the connection was + * established and placed in the RETH header. It identify the + * MRW on the remote host + */ + uint32_t remote_key; + uint32_t timestamp; + /* + * This field specifies a 24-bit timestamp that can be passed + * down the TX path and optionally logged in the TXP timestamp + * histogram. + */ + #define SQ_RDMA_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff) + #define SQ_RDMA_HDR_V3_TIMESTAMP_SFT 0 +} sq_rdma_hdr_v3_t, *psq_rdma_hdr_v3_t; + +/* SQ Atomic V3 WQE for RC SQs. */ +/* sq_atomic_v3 (size:448b/56B) */ + +typedef struct sq_atomic_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Atomic Compare/Swap V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18) + /* + * Atomic Fetch/Add V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19) + #define SQ_ATOMIC_V3_WQE_TYPE_LAST SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_ATOMIC_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_ATOMIC_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_ATOMIC_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. + */ + #define SQ_ATOMIC_V3_FLAGS_SE UINT32_C(0x8) + /* NA for this WQE */ + #define SQ_ATOMIC_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * The atomic WQE does not have a timestamp field, so this field is + * ignored and should be zero. + */ + #define SQ_ATOMIC_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_ATOMIC_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The size of the WQE in units of 16B chunks. + * + * For the Atomic WQE, this field will always have a value of 4. + */ + #define SQ_ATOMIC_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_ATOMIC_V3_WQE_SIZE_SFT 0 + uint8_t reserved1; + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * R_Key provided by remote node when the connection was + * established and placed in the AETH header. It identifies the + * MRW on the remote host. + */ + uint32_t remote_key; + uint32_t reserved2; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* + * For compare/swap, this is the data value to be placed in the + * remote host at the specified remote_VA if the comparison succeeds. + * + * For fetch/add, this is the value to be added to the data in the + * remote host at the specified remote_VA. + */ + uint64_t swap_data; + /* + * For compare/swap, this is the data value to be compared with the + * value in the remote host at the specified remote_VA. + * + * This field is not used for fetch/add. + */ + uint64_t cmp_data; + /* + * The virtual address in local memory or a physical address when + * l_key value is a reserved value of a physical address. Driver + * configures this value in the chip and the chip compares l_key in + * SGEs with that reserved value, if equal it access the physical + * address specified. The chip however MUST verify that the QP allows + * the use reserved key. + */ + uint64_t va_or_pa; + /* + * Local Key associated with this registered MR; The 24 msb of the + * key used to index the MRW Table and the 8 lsb are compared with + * the 8 bits key part stored in the MRWC. The PBL in the MRW Context + * is used to translate the above VA to physical address. + */ + uint32_t l_key; + /* + * Size of SGE in bytes; Based on page size of the system the chip + * knows how many entries are in the PBL + * + * This field must have a value of 8 for an Atomic WQE. + */ + uint32_t size; +} sq_atomic_v3_t, *psq_atomic_v3_t; + +/* SQ Atomic WQE V3 header for RC SQs. */ +/* sq_atomic_hdr_v3 (size:320b/40B) */ + +typedef struct sq_atomic_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Atomic Compare/Swap V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18) + /* + * Atomic Fetch/Add V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19) + #define SQ_ATOMIC_HDR_V3_WQE_TYPE_LAST SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_ATOMIC_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_ATOMIC_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_ATOMIC_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * Solicit event. Indication sent in BTH header to the + * receiver to generate a Completion Event Notification, + * i.e. CNQE. + */ + #define SQ_ATOMIC_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* NA for this WQE */ + #define SQ_ATOMIC_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * The atomic WQE does not have a timestamp field, so this field is + * ignored and should be zero. + */ + #define SQ_ATOMIC_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_ATOMIC_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The size of the WQE in units of 16B chunks. + * + * For the Atomic WQE, this field will always have a value of 4. + */ + #define SQ_ATOMIC_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_ATOMIC_HDR_V3_WQE_SIZE_SFT 0 + uint8_t reserved1; + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * R_Key provided by remote node when the connection was + * established and placed in the AETH header. It identifies the + * MRW on the remote host. + */ + uint32_t remote_key; + uint32_t reserved2; + /* Remote VA sent to the destination QP */ + uint64_t remote_va; + /* + * For compare/swap, this is the data value to be placed in the + * remote host at the specified remote_VA if the comparison succeeds. + * + * For fetch/add, this is the value to be added to the data in the + * remote host at the specified remote_VA. + */ + uint64_t swap_data; + /* + * For compare/swap, this is the data value to be compared with the + * value in the remote host at the specified remote_VA. + * + * This field is not used for fetch/add. + */ + uint64_t cmp_data; +} sq_atomic_hdr_v3_t, *psq_atomic_hdr_v3_t; + +/* SQ Local Invalidate WQE V3 for RC SQs. */ +/* sq_localinvalidate_v3 (size:128b/16B) */ + +typedef struct sq_localinvalidate_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Local Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a) + #define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LAST SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_LOCALINVALIDATE_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_LOCALINVALIDATE_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_LOCALINVALIDATE_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_LOCALINVALIDATE_V3_FLAGS_SE UINT32_C(0x8) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_LOCALINVALIDATE_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_LOCALINVALIDATE_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_LOCALINVALIDATE_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The size of the WQE in units of 16B chunks. + * + * For the Local Invalidate WQE, this field will always have + * a value of 1. + */ + #define SQ_LOCALINVALIDATE_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_LOCALINVALIDATE_V3_WQE_SIZE_SFT 0 + uint8_t reserved1; + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * The local key for the MR/W to invalidate; 24 msb of the key + * are used to index the MRW table, 8 lsb are compared with the + * 8 bit key in the MRWC + */ + uint32_t inv_l_key; + uint32_t reserved2; +} sq_localinvalidate_v3_t, *psq_localinvalidate_v3_t; + +/* SQ Local Invalidate WQE V3 header for RC SQs. */ +/* sq_localinvalidate_hdr_v3 (size:128b/16B) */ + +typedef struct sq_localinvalidate_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Local Invalidate V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a) + #define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size; + /* + * The size of the WQE in units of 16B chunks. + * + * For the Local Invalidate WQE, this field will always have + * a value of 1. + */ + #define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_SFT 0 + uint8_t reserved1; + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * The local key for the MR/W to invalidate; 24 msb of the key + * are used to index the MRW table, 8 lsb are compared with the + * 8 bit key in the MRWC + */ + uint32_t inv_l_key; + uint32_t reserved2; +} sq_localinvalidate_hdr_v3_t, *psq_localinvalidate_hdr_v3_t; + +/* + * SQ FR-PMR WQE V3 for RC SQs. + * + * The FR-PMR WQE must be padded to 3 slots (48 bytes) in the SQ, even + * though the final 8 bytes are not shown here. + */ +/* sq_fr_pmr_v3 (size:320b/40B) */ + +typedef struct sq_fr_pmr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * FR-PMR (Fast Register Physical Memory Region) V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b) + #define SQ_FR_PMR_V3_WQE_TYPE_LAST SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_FR_PMR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_FR_PMR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_FR_PMR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_V3_FLAGS_SE UINT32_C(0x8) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_FR_PMR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size_zero_based; + /* + * The size of the WQE in units of 16B chunks. + * + * For the FR-PMR WQE, this field will always have a value of 3. + */ + #define SQ_FR_PMR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_FR_PMR_V3_WQE_SIZE_SFT 0 + /* + * If this is set, the PMR will be zero-based. If clear, the PMR + * will be non-zero-based. + */ + #define SQ_FR_PMR_V3_ZERO_BASED UINT32_C(0x40) + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + /* Local Write Access */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* Remote Write Access */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* Remote Atomic Access */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* Window Binding Allowed */ + #define SQ_FR_PMR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Local Key; 24 msb of the key are used to index the MRW + * table, 8 lsb are assigned to the 8 bit key_lsb field in + * the MRWC. + */ + uint32_t l_key; + uint16_t page_size_log; + /* + * This value controls the page size for leaf memory pages in + * a PBL. While many page sizes are supported only the following + * should be tested - 4k, 8k, 64k, 256k, 1m, 2m, 4m, 1g + */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_LAST SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T + /* + * This value controls the page size for page table elements + * within a PBL. While many page sizes are supported only the + * following should be tested - 4k, 8k, 64k, 256k, 1m, 2m, 4m, 1g + */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x3e0) + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_SFT 5 + /* Page size is 4KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (UINT32_C(0x0) << 5) + /* Page size is 8KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (UINT32_C(0x1) << 5) + /* Page size is 16KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (UINT32_C(0x2) << 5) + /* Page size is 32KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (UINT32_C(0x3) << 5) + /* Page size is 64KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (UINT32_C(0x4) << 5) + /* Page size is 128KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (UINT32_C(0x5) << 5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (UINT32_C(0x6) << 5) + /* Page size is 512KB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (UINT32_C(0x7) << 5) + /* Page size is 1MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (UINT32_C(0x8) << 5) + /* Page size is 2MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (UINT32_C(0x9) << 5) + /* Page size is 4MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (UINT32_C(0xa) << 5) + /* Page size is 8MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (UINT32_C(0xb) << 5) + /* Page size is 16MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (UINT32_C(0xc) << 5) + /* Page size is 32MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (UINT32_C(0xd) << 5) + /* Page size is 64MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (UINT32_C(0xe) << 5) + /* Page size is 128MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (UINT32_C(0xf) << 5) + /* Page size is 256MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (UINT32_C(0x10) << 5) + /* Page size is 512MB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (UINT32_C(0x11) << 5) + /* Page size is 1GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (UINT32_C(0x12) << 5) + /* Page size is 2GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (UINT32_C(0x13) << 5) + /* Page size is 4GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (UINT32_C(0x14) << 5) + /* Page size is 8GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (UINT32_C(0x15) << 5) + /* Page size is 16GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (UINT32_C(0x16) << 5) + /* Page size is 32GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (UINT32_C(0x17) << 5) + /* Page size is 64GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (UINT32_C(0x18) << 5) + /* Page size is 128GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (UINT32_C(0x19) << 5) + /* Page size is 256GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (UINT32_C(0x1a) << 5) + /* Page size is 512GB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (UINT32_C(0x1b) << 5) + /* Page size is 1TB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (UINT32_C(0x1c) << 5) + /* Page size is 2TB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (UINT32_C(0x1d) << 5) + /* Page size is 4TB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (UINT32_C(0x1e) << 5) + /* Page size is 8TB. */ + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (UINT32_C(0x1f) << 5) + #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T + /* Number of levels of PBL for translation */ + #define SQ_FR_PMR_V3_NUMLEVELS_MASK UINT32_C(0xc00) + #define SQ_FR_PMR_V3_NUMLEVELS_SFT 10 + /* + * A zero level PBL means that the VA is the physical address + * used for the operation. No translation is done by the PTU. + */ + #define SQ_FR_PMR_V3_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 10) + /* + * A one layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical + * pages. + */ + #define SQ_FR_PMR_V3_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 10) + /* + * A two layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size + * physical pages that contain PBE values that point to actual + * physical pages. + */ + #define SQ_FR_PMR_V3_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 10) + #define SQ_FR_PMR_V3_NUMLEVELS_LAST SQ_FR_PMR_V3_NUMLEVELS_LAYER2 + uint16_t reserved; + /* Local Virtual Address */ + uint64_t va; + /* Length in bytes of registered MR */ + uint64_t length; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t pbl_ptr; +} sq_fr_pmr_v3_t, *psq_fr_pmr_v3_t; + +/* SQ FR-PMR WQE V3 header for RC SQs. */ +/* sq_fr_pmr_hdr_v3 (size:320b/40B) */ + +typedef struct sq_fr_pmr_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * FR-PMR (Fast Register Physical Memory Region) V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b) + #define SQ_FR_PMR_HDR_V3_WQE_TYPE_LAST SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_FR_PMR_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_FR_PMR_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_FR_PMR_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_FR_PMR_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_FR_PMR_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + /* */ + uint8_t wqe_size_zero_based; + /* + * The size of the WQE in units of 16B chunks. + * + * For the FR-PMR WQE, this field will always have a value of 3. + */ + #define SQ_FR_PMR_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_FR_PMR_HDR_V3_WQE_SIZE_SFT 0 + /* + * If this is set, the PMR will be zero-based. If clear, the PMR + * will be non-zero-based. + */ + #define SQ_FR_PMR_HDR_V3_ZERO_BASED UINT32_C(0x40) + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + /* Local Write Access */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* Remote Write Access */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* Remote Atomic Access */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* Window Binding Allowed */ + #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * Local Key; 24 msb of the key are used to index the MRW + * table, 8 lsb are assigned to the 8 bit key_lsb field in + * the MRWC. + */ + uint32_t l_key; + uint16_t page_size_log; + /* + * This value controls the page size for leaf memory pages in + * a PBL. While many page sizes are supported only the following + * should be tested - 4k, 8k, 64k, 256k, 1m, 2m, 4m, 1g + */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_MASK UINT32_C(0x1f) + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_SFT 0 + /* Page size is 4KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0) + /* Page size is 8KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1) + /* Page size is 16KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2) + /* Page size is 32KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3) + /* Page size is 64KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4) + /* Page size is 128KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6) + /* Page size is 512KB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7) + /* Page size is 1MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8) + /* Page size is 2MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9) + /* Page size is 4MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa) + /* Page size is 8MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb) + /* Page size is 16MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc) + /* Page size is 32MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd) + /* Page size is 64MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe) + /* Page size is 128MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf) + /* Page size is 256MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10) + /* Page size is 512MB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11) + /* Page size is 1GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12) + /* Page size is 2GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13) + /* Page size is 4GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14) + /* Page size is 8GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15) + /* Page size is 16GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16) + /* Page size is 32GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17) + /* Page size is 64GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18) + /* Page size is 128GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19) + /* Page size is 256GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a) + /* Page size is 512GB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b) + /* Page size is 1TB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c) + /* Page size is 2TB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d) + /* Page size is 4TB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e) + /* Page size is 8TB. */ + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f) + #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T + /* + * This value controls the page size for page table elements + * within a PBL. While many page sizes are supported only the + * following should be tested - 4k, 8k, 64k, 256k, 1m, 2m, 4m, 1g + */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x3e0) + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_SFT 5 + /* Page size is 4KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (UINT32_C(0x0) << 5) + /* Page size is 8KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (UINT32_C(0x1) << 5) + /* Page size is 16KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (UINT32_C(0x2) << 5) + /* Page size is 32KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (UINT32_C(0x3) << 5) + /* Page size is 64KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (UINT32_C(0x4) << 5) + /* Page size is 128KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (UINT32_C(0x5) << 5) + /* Page size is 256KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (UINT32_C(0x6) << 5) + /* Page size is 512KB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (UINT32_C(0x7) << 5) + /* Page size is 1MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (UINT32_C(0x8) << 5) + /* Page size is 2MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (UINT32_C(0x9) << 5) + /* Page size is 4MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (UINT32_C(0xa) << 5) + /* Page size is 8MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (UINT32_C(0xb) << 5) + /* Page size is 16MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (UINT32_C(0xc) << 5) + /* Page size is 32MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (UINT32_C(0xd) << 5) + /* Page size is 64MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (UINT32_C(0xe) << 5) + /* Page size is 128MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (UINT32_C(0xf) << 5) + /* Page size is 256MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (UINT32_C(0x10) << 5) + /* Page size is 512MB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (UINT32_C(0x11) << 5) + /* Page size is 1GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (UINT32_C(0x12) << 5) + /* Page size is 2GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (UINT32_C(0x13) << 5) + /* Page size is 4GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (UINT32_C(0x14) << 5) + /* Page size is 8GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (UINT32_C(0x15) << 5) + /* Page size is 16GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (UINT32_C(0x16) << 5) + /* Page size is 32GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (UINT32_C(0x17) << 5) + /* Page size is 64GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (UINT32_C(0x18) << 5) + /* Page size is 128GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (UINT32_C(0x19) << 5) + /* Page size is 256GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (UINT32_C(0x1a) << 5) + /* Page size is 512GB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (UINT32_C(0x1b) << 5) + /* Page size is 1TB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (UINT32_C(0x1c) << 5) + /* Page size is 2TB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (UINT32_C(0x1d) << 5) + /* Page size is 4TB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (UINT32_C(0x1e) << 5) + /* Page size is 8TB. */ + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (UINT32_C(0x1f) << 5) + #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T + /* Number of levels of PBL for translation */ + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_MASK UINT32_C(0xc00) + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_SFT 10 + /* + * A zero level PBL means that the VA is the physical address + * used for the operation. No translation is done by the PTU. + */ + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 10) + /* + * A one layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PBE values that point to actual pg_size physical + * pages. + */ + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 10) + /* + * A two layer translation is provided between the logical and + * physical address. The PBL points to a physical page that + * contains PDE values that in turn point to pbl_pg_size + * physical pages that contain PBE values that point to actual + * physical pages. + */ + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 10) + #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAST SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 + uint16_t reserved; + /* Local Virtual Address */ + uint64_t va; + /* Length in bytes of registered MR */ + uint64_t length; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t pbl_ptr; +} sq_fr_pmr_hdr_v3_t, *psq_fr_pmr_hdr_v3_t; + +/* + * SQ Bind WQE V3. This WQE can perform either: + * * type1 "bind memory window", if mw_type==Type1 + * * type2 "post send bind memory window", if mw_type==Type2 + */ +/* sq_bind_v3 (size:256b/32B) */ + +typedef struct sq_bind_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Memory Bind V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BIND_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c) + #define SQ_BIND_V3_WQE_TYPE_LAST SQ_BIND_V3_WQE_TYPE_BIND_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_BIND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_BIND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_BIND_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_BIND_V3_FLAGS_SE UINT32_C(0x8) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_BIND_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_BIND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_BIND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint8_t wqe_size_zero_based_mw_type; + /* + * The size of the WQE in units of 16B chunks. + * + * For the Bind WQE, this field will always have a value of 2. + */ + #define SQ_BIND_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_BIND_V3_WQE_SIZE_SFT 0 + /* + * If this bit is set, then the newly-bound memory window will be + * zero-based. If clear, then the newly-bound memory window will be + * non-zero-based. + */ + #define SQ_BIND_V3_ZERO_BASED UINT32_C(0x40) + /* + * If type1 is specified, then this WQE performs a "bind memory + * window" operation on a type1 window. If type2 is specified, then + * this WQE performs a "post send bind memory window" operation on a + * type2 window. + * + * Note that the bind WQE cannot change the type of the memory + * window. + * + * If a "bind memory window" operation is attempted on a memory + * window that was allocated as type2, then the bind will fail with + * an errored completion, as "bind memory window" is allowed only on + * type1 memory windows. + * + * Similarly, if a "post send bind memory window" operation is + * attempted on a memory window that was allocated as type1, then the + * bind will fail with an errored completions, as "post send bind + * memory window" is allowed only on type2 memory windows. + */ + #define SQ_BIND_V3_MW_TYPE UINT32_C(0x80) + /* Type 1 Bind Memory Window */ + #define SQ_BIND_V3__TYPE1 (UINT32_C(0x0) << 7) + /* Type 2 Post Send Bind Memory Window */ + #define SQ_BIND_V3__TYPE2 (UINT32_C(0x1) << 7) + #define SQ_BIND_V3__LAST SQ_BIND_V3__TYPE2 + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + /* + * Local Write Access. + * + * Local accesses are never allowed for memory windows, so this + * bit must always be zero in a bind WQE. If this bit is ever + * set, the bind will fail with an errored completion. + */ + #define SQ_BIND_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* + * Remote Write Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is not + * the case, then the bind will fail with an errored completion. + */ + #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* + * Remote Atomic Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is not + * the case, then the bind will fail with an errored completion. + */ + #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* + * Window Binding Allowed. + * + * It is never allowed to bind windows to windows, so this bit + * must always be zero in a bind WQE. If this bit is ever set, + * the bind will fail with an errored completion. + */ + #define SQ_BIND_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * The L_Key of the parent MR; 24 msb of the key are used to + * index the MRW table, 8 lsb are compared with the 8 bit key + * in the MRWC. + */ + uint32_t parent_l_key; + /* + * Local Key; 24 msb of the key are used to index the memory + * window being bound in the MRW table, 8 lsb are assign to the + * 8 bit key_lsb field in the MRWC. + */ + uint32_t l_key; + /* Local Virtual Address */ + uint64_t va; + /* + * Length in bytes of registered MW; 40 bits as this is the max + * size of an MR/W + */ + uint64_t length; +} sq_bind_v3_t, *psq_bind_v3_t; + +/* + * SQ Bind WQE V3 header. This WQE can perform either: + * * type1 "bind memory window", if mw_type==Type1 + * * type2 "post send bind memory window", if mw_type==Type2 + */ +/* sq_bind_hdr_v3 (size:256b/32B) */ + +typedef struct sq_bind_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* + * Memory Bind V3 + * + * Allowed only on reliable connection (RC) SQs. + */ + #define SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c) + #define SQ_BIND_HDR_V3_WQE_TYPE_LAST SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_BIND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_BIND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + */ + #define SQ_BIND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_BIND_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_BIND_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_BIND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_BIND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint8_t wqe_size_zero_based_mw_type; + /* + * The size of the WQE in units of 16B chunks. + * + * For the Bind WQE, this field will always have a value of 2. + */ + #define SQ_BIND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_BIND_HDR_V3_WQE_SIZE_SFT 0 + /* + * If this bit is set, then the newly-bound memory window will be + * zero-based. If clear, then the newly-bound memory window will be + * non-zero-based. + */ + #define SQ_BIND_HDR_V3_ZERO_BASED UINT32_C(0x40) + /* + * If type1 is specified, then this WQE performs a "bind memory + * window" operation on a type1 window. If type2 is specified, then + * this WQE performs a "post send bind memory window" operation on a + * type2 window. + * + * Note that the bind WQE cannot change the type of the memory + * window. + * + * If a "bind memory window" operation is attempted on a memory + * window that was allocated as type2, then the bind will fail with + * an errored completion, as "bind memory window" is allowed only on + * type1 memory windows. + * + * Similarly, if a "post send bind memory window" operation is + * attempted on a memory window that was allocated as type1, then the + * bind will fail with an errored completions, as "post send bind + * memory window" is allowed only on type2 memory windows. + */ + #define SQ_BIND_HDR_V3_MW_TYPE UINT32_C(0x80) + /* Type 1 Bind Memory Window */ + #define SQ_BIND_HDR_V3__TYPE1 (UINT32_C(0x0) << 7) + /* Type 2 Post Send Bind Memory Window */ + #define SQ_BIND_HDR_V3__TYPE2 (UINT32_C(0x1) << 7) + #define SQ_BIND_HDR_V3__LAST SQ_BIND_HDR_V3__TYPE2 + /* + * This is the new access control for the MR. '1' means + * the operation is allowed. '0' means operation is + * not allowed. + */ + uint8_t access_cntl; + /* + * Local Write Access. + * + * Local accesses are never allowed for memory windows, so this + * bit must always be zero in a bind WQE. If this bit is ever + * set, the bind will fail with an errored completion. + */ + #define SQ_BIND_HDR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1) + /* Remote Read Access */ + #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2) + /* + * Remote Write Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is not + * the case, then the bind will fail with an errored completion. + */ + #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4) + /* + * Remote Atomic Access. + * + * Note that, if this bit is set, then the parent region to which + * the window is being bound must allow local writes. If this is not + * the case, then the bind will fail with an errored completion. + */ + #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8) + /* + * Window Binding Allowed. + * + * It is never allowed to bind windows to windows, so this bit + * must always be zero in a bind WQE. If this bit is ever set, + * the bind will fail with an errored completion. + */ + #define SQ_BIND_HDR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10) + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* + * The L_Key of the parent MR; 24 msb of the key are used to + * index the MRW table, 8 lsb are compared with the 8 bit key + * in the MRWC. + */ + uint32_t parent_l_key; + /* + * Local Key; 24 msb of the key are used to index the memory + * window being bound in the MRW table, 8 lsb are assign to the + * 8 bit key_lsb field in the MRWC. + */ + uint32_t l_key; + /* Local Virtual Address */ + uint64_t va; + /* + * Length in bytes of registered MW; 40 bits as this is the max + * size of an MR/W + */ + uint64_t length; +} sq_bind_hdr_v3_t, *psq_bind_hdr_v3_t; + +/* + * This is the Change UDP Source Port WQE V3 structure. It is supported + * for both RC and UD QP's. + * + * It is recommended to set the uc_fence flag for this WQE, so that the + * source port does not change while there are unacknowledged packets. + */ +/* sq_change_udpsrcport_v3 (size:128b/16B) */ + +typedef struct sq_change_udpsrcport_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Change UDP Source Port V3 */ + #define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e) + #define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_LAST SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + * + * It is recommended to set this flag for Change UDP Source Port + * WQE's. + */ + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SE UINT32_C(0x8) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint8_t wqe_size; + /* + * The size of the WQE in units of 16B chunks. + * + * For the Change UDP Source Port WQE, this field will always have + * a value of 1. + */ + #define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_SFT 0 + uint8_t reserved_1; + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* The new value for the QP's UDP source port. */ + uint16_t udp_src_port; + uint16_t reserved_2; + uint32_t reserved_3; +} sq_change_udpsrcport_v3_t, *psq_change_udpsrcport_v3_t; + +/* SQ Change UDP Source Port WQE V3 header */ +/* sq_change_udpsrcport_hdr_v3 (size:128b/16B) */ + +typedef struct sq_change_udpsrcport_hdr_v3 { + /* This field defines the type of SQ WQE. */ + uint8_t wqe_type; + /* Change UDP Source Port V3 */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_LAST SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 + uint8_t flags; + /* + * Set if completion signaling is requested. If this bit is + * 0, and the SQ is configured to support Unsignaled + * completion the controller should not generate a CQE + * unless there was an error. This refers to CQE on the + * sender side (The se flag refers to the receiver side). + */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1) + /* + * Indication to complete all previous RDMA Read or Atomic + * WQEs on the SQ before executing this WQE + */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2) + /* + * Unconditional fence. Indication to complete all previous + * SQ's WQEs before executing this WQE. + * + * It is recommended to set this flag for Change UDP Source Port + * WQE's. + */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SE UINT32_C(0x8) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_INLINE UINT32_C(0x10) + /* + * This flag is not applicable and should be 0 for a local memory + * operation WQE. + */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20) + /* + * When set to '1', this operation will cause a trace capture in + * each block it passes through. + */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40) + uint8_t wqe_size; + /* + * The size of the WQE in units of 16B chunks. + * + * For the Change UDP Source Port WQE, this field will always have + * a value of 1. + */ + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f) + #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_SFT 0 + uint8_t reserved_1; + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; + /* The new value for the QP's UDP source port. */ + uint16_t udp_src_port; + uint16_t reserved_2; + uint32_t reserved_3; +} sq_change_udpsrcport_hdr_v3_t, *psq_change_udpsrcport_hdr_v3_t; + /* RQ/SRQ WQE */ /* rq_wqe (size:1024b/128B) */ @@ -72646,7 +82943,7 @@ typedef struct rq_wqe { /* wqe_type is 8 b */ uint8_t wqe_type; /* - * RQ/SRQ WQE. This WQE is used for posting buffers on + * RQ/SRQ WQE. This WQE is used for posting buffers on * an RQ or SRQ. */ #define RQ_WQE_WQE_TYPE_RCV UINT32_C(0x80) @@ -72655,7 +82952,7 @@ typedef struct rq_wqe { uint8_t flags; /* * Specify the total number 16B chunks that make up the valid - * portion of the WQE. This includes the first chunk that is the + * portion of the WQE. This includes the first chunk that is the * WQE structure and up to 6 SGE structures. * * While the valid area is defined by the wqe_size field, the @@ -72687,7 +82984,7 @@ typedef struct rq_wqe_hdr { /* wqe_type is 8 b */ uint8_t wqe_type; /* - * RQ/SRQ WQE. This WQE is used for posting buffers on + * RQ/SRQ WQE. This WQE is used for posting buffers on * an RQ or SRQ. */ #define RQ_WQE_HDR_WQE_TYPE_RCV UINT32_C(0x80) @@ -72696,7 +82993,7 @@ typedef struct rq_wqe_hdr { uint8_t flags; /* * Specify the total number 16B chunks that make up the valid - * portion of the WQE. This includes the first chunk that is the + * portion of the WQE. This includes the first chunk that is the * WQE structure and up to 6 SGE structures. * * While the valid area is defined by the wqe_size field, the @@ -72716,6 +83013,65 @@ typedef struct rq_wqe_hdr { uint8_t reserved128[16]; } rq_wqe_hdr_t, *prq_wqe_hdr_t; +/* RQ/SRQ WQE V3 */ +/* rq_wqe_v3 (size:4096b/512B) */ + +typedef struct rq_wqe_v3 { + /* wqe_type is 8 b */ + uint8_t wqe_type; + /* + * RQ/SRQ WQE V3. This WQE is used for posting buffers on + * an RQ or SRQ. + */ + #define RQ_WQE_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90) + #define RQ_WQE_V3_WQE_TYPE_LAST RQ_WQE_V3_WQE_TYPE_RCV_V3 + /* No flags supported for this WQE type. */ + uint8_t flags; + /* + * Specify the total number 16B chunks that make up the valid portion + * of the WQE. This includes the first chunk that is the WQE + * structure and up to 30 SGE structures. The maximum value for this + * field is 32, representing a maximum-sized WQE of 512B. + */ + uint8_t wqe_size; + uint8_t reserved1; + /* This value will be returned in the completion. */ + uint32_t opaque; + uint64_t reserved2; + /* + * The data field for RQ WQE is filled with from 1 to 30 SGE + * structures as defined by the wqe_size field. + */ + uint32_t data[124]; +} rq_wqe_v3_t, *prq_wqe_v3_t; + +/* RQ/SRQ WQE V3 header. */ +/* rq_wqe_hdr_v3 (size:128b/16B) */ + +typedef struct rq_wqe_hdr_v3 { + /* wqe_type is 8 b */ + uint8_t wqe_type; + /* + * RQ/SRQ WQE V3. This WQE is used for posting buffers on + * an RQ or SRQ. + */ + #define RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90) + #define RQ_WQE_HDR_V3_WQE_TYPE_LAST RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 + /* No flags supported for this WQE type. */ + uint8_t flags; + /* + * Specify the total number 16B chunks that make up the valid portion + * of the WQE. This includes the first chunk that is the WQE + * structure and up to 30 SGE structures. The maximum value for this + * field is 32, representing a maximum-sized WQE of 512B. + */ + uint8_t wqe_size; + uint8_t reserved1; + /* This value will be returned in the completion. */ + uint32_t opaque; + uint64_t reserved2; +} rq_wqe_hdr_v3_t, *prq_wqe_hdr_v3_t; + /* cq_base (size:256b/32B) */ typedef struct cq_base { @@ -72724,14 +83080,14 @@ typedef struct cq_base { uint64_t reserved64_3; uint8_t cqe_type_toggle; /* - * Indicate valid completion - written by the chip. Cumulus + * Indicate valid completion - written by the chip. The NIC * toggle this bit each time it finished consuming all PBL - * entries + * entries. */ - #define CQ_BASE_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ - #define CQ_BASE_CQE_TYPE_MASK UINT32_C(0x1e) - #define CQ_BASE_CQE_TYPE_SFT 1 + #define CQ_BASE_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_BASE_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_BASE_CQE_TYPE_SFT 1 /* * Requester completion - This is used for both RC and UD SQ * completions. @@ -72741,17 +83097,17 @@ typedef struct cq_base { * Responder RC Completion - This is used for both RQ and SRQ * completions for RC service QPs. */ - #define CQ_BASE_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1) + #define CQ_BASE_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1) /* * Responder UD Completion - This is used for both RQ and SRQ * completion for UD service QPs. */ - #define CQ_BASE_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1) + #define CQ_BASE_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1) /* * Responder RawEth and QP1 Completion - This is used for RQ * completion for RawEth service and QP1 service QPs. */ - #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1) + #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1) /* * Responder UD completion with CFA. This is used for both RQ * and SQ completion for UD service QPs. It includes cfa fields @@ -72759,22 +83115,188 @@ typedef struct cq_base { */ #define CQ_BASE_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1) /* - * NO_OP completion - This is used to indicate that no - * operation completion. + * Requester completion V3 - This is used for both RC and UD SQ + * completions. */ - #define CQ_BASE_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1) + #define CQ_BASE_CQE_TYPE_REQ_V3 (UINT32_C(0x8) << 1) + /* + * Responder RC Completion V3 - This is used for both RQ and SRQ + * completions for RC service QPs. + */ + #define CQ_BASE_CQE_TYPE_RES_RC_V3 (UINT32_C(0x9) << 1) + /* + * Responder UD Completion V3 - This is used for both RQ and SRQ + * completion for UD service QPs. It is also used for QP1 QPs + * that are treated as UD. + */ + #define CQ_BASE_CQE_TYPE_RES_UD_V3 (UINT32_C(0xa) << 1) + /* + * Responder RawEth and QP1 Completion V3 - This is used for RQ and + * SRQ completion for RawEth service. It is also used for QP1 QPs + * that are treated as RawEth. + */ + #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (UINT32_C(0xb) << 1) + /* + * Responder UD Completion with CFA V3 - This is used for both RQ + * and SRQ completion for UD service QPs. It includes CFA fields + * (some of which carry VLAN information), in place of the QP + * handle. It is also used for QP1 QPs that are treated as UD. + */ + #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (UINT32_C(0xc) << 1) + /* + * NO_OP completion - This is used to indicate that no + * operation completed. + */ + #define CQ_BASE_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1) /* * Terminal completion - This is used to indicate that no * further completions will be made for this QP on this CQ. */ #define CQ_BASE_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1) - /* Cut off CQE; for CQ resize see CQ and SRQ Resize */ - #define CQ_BASE_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1) - #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF + /* + * Cut off CQE; for CQ resize. This CQE is written to the "old" + * CQ as the last CQE written. SW may use this to know when the + * "old" CQ can be destroyed. + */ + #define CQ_BASE_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1) + #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF /* This field indicates the status for the CQE. */ uint8_t status; + /* The operation completed successfully. */ + #define CQ_BASE_STATUS_OK UINT32_C(0x0) + /* + * An unexpected BTH opcode or a First/Middle packet that is not + * the full MTU size was returned by the responder. + * + * This is a fatal error detected by the requester Rx. + */ + #define CQ_BASE_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1) + /* + * Generated for a WQE posted to the local SQ when the sum of the + * lengths of the SGEs in the WQE exceeds the maximum message + * length of 2^31 bytes. + * + * Generated for a WQE posted to the local RQ/SRQ when the sum of + * the lengths of the SGEs in the WQE is too small to receive the + * (valid) incoming message or the length of the incoming message + * is greater than the maximum message size supported. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* + * This indicates that the packet was too long for the WQE provided + * on the SRQ/RQ. + * + * This is not a fatal error. All the fields in the CQE are valid. + */ + #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3) + /* + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * A protection error occurred on a local data buffer during the + * processing of a RDMA Write with Immediate Data operation sent + * from the remote node. + * + * This is a fatal error detected by the responder Rx. Only the + * opaque field in the CQE is valid. + */ + #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x6) + /* + * The SSC detected an error on a local memory operation from the + * SQ (fast-register, local invalidate, or bind). + * + * This is a fatal error detected by the requester Tx. + */ + #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x7) + /* + * An invalid message was received by the responder. This could be + * an operation that is not supported by this QP, an IRRQ overflow + * error, or the length in an RDMA operation is greater than the + * maximum message size (2^31 bytes). + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Invalid Request. For responder + * CQEs, only the opaque field is valid. + */ + #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8) + /* + * A protection error occurred on a remote data buffer to be read + * by an RDMA Read, written by an RDMA Write or accessed by an + * atomic operation. This error is reported only on RDMA operations + * or atomic operations. + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Remote Access Violation. + */ + #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x9) + /* + * The operation could not be completed successfully by the + * responder. Possible causes include an RQ/SRQ WQE format error, + * an SSC error when validating an SGE from an RQ/SRQ WQE, or the + * message received was too long for the RQ/SRQ WQE. + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Remote Operation Error. + */ + #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR UINT32_C(0xa) + /* + * The RNR NAK retry count was exceeded while trying to send this + * message. + * + * This is a fatal error detected by the requester. + */ + #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0xb) + /* + * The local transport timeout retry counter was exceeded while + * trying to send this message. + * + * This is a fatal error detected by the requester. + */ + #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xc) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. + */ + #define CQ_BASE_STATUS_HW_FLUSH_ERR UINT32_C(0xe) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_BASE_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR uint16_t reserved16; - uint32_t reserved32; + /* + * This value is from the WQE that is being completed. This field is + * only applicable to V3 version of CQEs. + */ + uint32_t opaque; } cq_base_t, *pcq_base_t; /* Requester CQ CQE */ @@ -72788,7 +83310,7 @@ typedef struct cq_req { uint64_t qp_handle; /* * SQ Consumer Index - points to the entry just past the last WQE - * that has been completed by the chip. Wraps around at + * that has been completed by the chip. Wraps around at * QPC.sq_size (i.e. the valid range of the SQ Consumer Index is 0 * to (QPC.sq_size - 1)). */ @@ -72803,7 +83325,7 @@ typedef struct cq_req { * entries */ #define CQ_REQ_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_REQ_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_REQ_CQE_TYPE_SFT 1 /* @@ -72888,7 +83410,7 @@ typedef struct cq_res_rc { * entries */ #define CQ_RES_RC_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_RES_RC_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_RES_RC_CQE_TYPE_SFT 1 /* @@ -72994,7 +83516,7 @@ typedef struct cq_res_ud { * entries */ #define CQ_RES_UD_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_RES_UD_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_RES_UD_CQE_TYPE_SFT 1 /* @@ -73014,7 +83536,7 @@ typedef struct cq_res_ud { * This indicates that write access was not allowed for * at least one of the SGEs in the WQE. * - * This is a fatal error. Only the srq_or_rq_wr_id is field + * This is a fatal error. Only the srq_or_rq_wr_id is field * is valid. */ #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) @@ -73022,7 +83544,7 @@ typedef struct cq_res_ud { * This indicates that the packet was too long for the WQE * provided on the SRQ/RQ. * - * This is not a fatal error. All the fields are valid. + * This is not a fatal error. All the fields are valid. */ #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) /* LOCAL_PROTECTION_ERR is 3 */ @@ -73066,7 +83588,7 @@ typedef struct cq_res_ud { */ #define CQ_RES_UD_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6 - /* No metadata information. Value is zero. */ + /* No metadata information. Value is zero. */ #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) /* * The metadata field contains the VLAN tag and TPID value. @@ -73164,7 +83686,7 @@ typedef struct cq_res_ud_v2 { * entries */ #define CQ_RES_UD_V2_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_RES_UD_V2_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_RES_UD_V2_CQE_TYPE_SFT 1 /* @@ -73184,7 +83706,7 @@ typedef struct cq_res_ud_v2 { * This indicates that write access was not allowed for * at least one of the SGEs in the WQE. * - * This is a fatal error. Only the srq_or_rq_wr_id is field + * This is a fatal error. Only the srq_or_rq_wr_id is field * is valid. */ #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) @@ -73192,7 +83714,7 @@ typedef struct cq_res_ud_v2 { * This indicates that the packet was too long for the WQE * provided on the SRQ/RQ. * - * This is not a fatal error. All the fields are valid. + * This is not a fatal error. All the fields are valid. */ #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) /* LOCAL_PROTECTION_ERR is 3 */ @@ -73233,7 +83755,7 @@ typedef struct cq_res_ud_v2 { /* The field indicates what format the metadata field is. */ #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6 - /* No metadata information. Value is zero. */ + /* No metadata information. Value is zero. */ #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) /* * The {metadata1, metadata0} fields contain the vtag @@ -73331,7 +83853,7 @@ typedef struct cq_res_ud_cfa { uint32_t qid; /* * This value indicates the QPID associated with this operation. - * The driver will use the qid from thie CQE to map a QP handle + * The driver will use the qid from this CQE to map a QP handle * in the completion record returned to the application. */ #define CQ_RES_UD_CFA_QID_MASK UINT32_C(0xfffff) @@ -73366,7 +83888,7 @@ typedef struct cq_res_ud_cfa { * entries */ #define CQ_RES_UD_CFA_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_RES_UD_CFA_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1 /* @@ -73529,7 +84051,7 @@ typedef struct cq_res_ud_cfa_v2 { uint32_t qid; /* * This value indicates the QPID associated with this operation. - * The driver will use the qid from thie CQE to map a QP handle + * The driver will use the qid from this CQE to map a QP handle * in the completion record returned to the application. */ #define CQ_RES_UD_CFA_V2_QID_MASK UINT32_C(0xfffff) @@ -73561,7 +84083,7 @@ typedef struct cq_res_ud_cfa_v2 { * entries */ #define CQ_RES_UD_CFA_V2_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1 /* @@ -73632,7 +84154,7 @@ typedef struct cq_res_ud_cfa_v2 { /* The field indicates what format the metadata field is. */ #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6 - /* No metadata information. Value is zero. */ + /* No metadata information. Value is zero. */ #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) /* * The {metadata1, metadata0} fields contain the vtag @@ -73725,7 +84247,7 @@ typedef struct cq_res_raweth_qp1 { #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * raweth_qp1_errors. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1) @@ -73749,31 +84271,36 @@ typedef struct cq_res_raweth_qp1 { /* * TCP Packet: * Indicates that the packet was IP and TCP. - * This indicates that the raweth_qp1_payload_offset field is valid. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6) /* * UDP Packet: * Indicates that the packet was IP and UDP. - * This indicates that the raweth_qp1_payload_offset field is valid. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6) /* * FCoE Packet: * Indicates that the packet was recognized as a FCoE. - * This also indicates that the raweth_qp1_payload_offset field is valid. + * This also indicates that the raweth_qp1_payload_offset field + * is valid. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6) /* * RoCE Packet: * Indicates that the packet was recognized as a RoCE. - * This also indicates that the raweth_qp1_payload_offset field is valid. + * This also indicates that the raweth_qp1_payload_offset field + * is valid. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6) /* * ICMP Packet: * Indicates that the packet was recognized as ICMP. - * This indicates that the raweth_qp1_payload_offset field is valid. + * This indicates that the raweth_qp1_payload_offset field is + * valid. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6) /* @@ -73812,7 +84339,7 @@ typedef struct cq_res_raweth_qp1 { #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) /* * This indicates that there was a CRC error on either an FCoE - * or RoCE packet. The itype indicates the packet type. + * or RoCE packet. The itype indicates the packet type. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100) /* @@ -73944,23 +84471,27 @@ typedef struct cq_res_raweth_qp1 { #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2) /* * This indicates that the ip checksum was calculated for the - * tunnel header and that the t_ip_cs_error field indicates if there - * was an error. + * tunnel header and that the t_ip_cs_error field indicates if + * there was an error. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) /* * This indicates that the UDP checksum was - * calculated for the tunnel packet and that the t_l4_cs_error field - * indicates if there was an error. + * calculated for the tunnel packet and that the t_l4_cs_error + * field indicates if there was an error. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) - /* This value indicates what format the raweth_qp1_metadata field is. */ + /* + * This value indicates what format the raweth_qp1_metadata field + * is. + */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 - /* No metadata information. Value is zero. */ + /* No metadata information. Value is zero. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) /* - * The raweth_qp1_metadata field contains the VLAN tag and TPID value. + * The raweth_qp1_metadata field contains the VLAN tag and TPID + * value. * - raweth_qp1_metadata[11:0] contains the vlan VID value. * - raweth_qp1_metadata[12] contains the vlan DE value. * - raweth_qp1_metadata[15:13] contains the vlan PRI value. @@ -73997,7 +84528,7 @@ typedef struct cq_res_raweth_qp1 { #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. * This value is only valid if itype indicates a packet * with an IP header. */ @@ -74014,9 +84545,9 @@ typedef struct cq_res_raweth_qp1 { #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00) #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10 /* - * This value is the complete 1's complement checksum calculated from - * the start of the outer L3 header to the end of the packet (not - * including the ethernet crc). It is valid when the + * This value is the complete 1's complement checksum calculated + * from the start of the outer L3 header to the end of the packet + * (not including the ethernet crc). It is valid when the * 'complete_checksum_calc' flag is set. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000) @@ -74046,7 +84577,7 @@ typedef struct cq_res_raweth_qp1 { * entries */ #define CQ_RES_RAWETH_QP1_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1 /* @@ -74066,7 +84597,7 @@ typedef struct cq_res_raweth_qp1 { * This indicates that write access was not allowed for * at least one of the SGEs in the WQE. * - * This is a fatal error. Only the srq_or_rq_wr_id is field + * This is a fatal error. Only the srq_or_rq_wr_id is field * is valid. */ #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) @@ -74074,7 +84605,7 @@ typedef struct cq_res_raweth_qp1 { * This indicates that the packet was too long for the WQE * provided on the RQ. * - * This is not a fatal error. All the fields are valid. + * This is not a fatal error. All the fields are valid. */ #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) /* LOCAL_PROTECTION_ERR is 3 */ @@ -74108,10 +84639,9 @@ typedef struct cq_res_raweth_qp1 { #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff) #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0 /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. - * + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for + * TCP, UDP, FCoE, and RoCE packets. * A value of zero indicates an offset of 256 bytes. */ #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000) @@ -74134,7 +84664,7 @@ typedef struct cq_res_raweth_qp1_v2 { #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * raweth_qp1_errors. */ #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1) @@ -74226,7 +84756,7 @@ typedef struct cq_res_raweth_qp1_v2 { #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) /* * This indicates that there was a CRC error on either an FCoE - * or RoCE packet. The itype indicates the packet type. + * or RoCE packet. The itype indicates the packet type. */ #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100) /* @@ -74420,7 +84950,7 @@ typedef struct cq_res_raweth_qp1_v2 { #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. * This value is only valid if itype indicates a packet * with an IP header. */ @@ -74465,7 +84995,7 @@ typedef struct cq_res_raweth_qp1_v2 { * entries */ #define CQ_RES_RAWETH_QP1_V2_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1 /* @@ -74485,7 +85015,7 @@ typedef struct cq_res_raweth_qp1_v2 { * This indicates that write access was not allowed for * at least one of the SGEs in the WQE. * - * This is a fatal error. Only the srq_or_rq_wr_id is field + * This is a fatal error. Only the srq_or_rq_wr_id is field * is valid. */ #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1) @@ -74493,7 +85023,7 @@ typedef struct cq_res_raweth_qp1_v2 { * This indicates that the packet was too long for the WQE * provided on the RQ. * - * This is not a fatal error. All the fields are valid. + * This is not a fatal error. All the fields are valid. */ #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2) /* LOCAL_PROTECTION_ERR is 3 */ @@ -74548,7 +85078,7 @@ typedef struct cq_res_raweth_qp1_v2 { #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID UINT32_C(0x800000) /* * This value indicates the offset in bytes from the beginning of - * the packet where the inner payload starts. This value is valid + * the packet where the inner payload starts. This value is valid * for TCP, UDP, FCoE, and RoCE packets. * * A value of zero indicates an offset of 256 bytes. @@ -74557,7 +85087,10 @@ typedef struct cq_res_raweth_qp1_v2 { #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24 } cq_res_raweth_qp1_v2_t, *pcq_res_raweth_qp1_v2_t; -/* Terminal CQE */ +/* + * This is the terminal CQE structure. This CQE is generated to + * indicate that no further completions will be generated for this QP. + */ /* cq_terminal (size:256b/32B) */ typedef struct cq_terminal { @@ -74567,12 +85100,12 @@ typedef struct cq_terminal { */ uint64_t qp_handle; /* - * Final SQ Consumer Index value. Any additional SQ WQEs will + * Final SQ Consumer Index value. Any additional SQ WQEs will * have to be completed by the user provider. */ uint16_t sq_cons_idx; /* - * Final RQ Consumer Index value. Any additional RQ WQEs will + * Final RQ Consumer Index value. Any additional RQ WQEs will * have to be completed by the user provider. */ uint16_t rq_cons_idx; @@ -74585,7 +85118,7 @@ typedef struct cq_terminal { * entries */ #define CQ_TERMINAL_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_TERMINAL_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_TERMINAL_CQE_TYPE_SFT 1 /* @@ -74596,7 +85129,7 @@ typedef struct cq_terminal { #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL /* This field indicates the status for the CQE. */ uint8_t status; - /* OK is 0 */ + /* The operation completed successfully. */ #define CQ_TERMINAL_STATUS_OK UINT32_C(0x0) #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK uint16_t reserved16; @@ -74612,12 +85145,12 @@ typedef struct cq_cutoff { uint64_t reserved64_3; uint8_t cqe_type_toggle; /* - * Indicate valid completion - written by the chip. Cumulus - * toggle this bit each time it finished consuming all PBL + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL * entries */ #define CQ_CUTOFF_TOGGLE UINT32_C(0x1) - /* This field defines the type of SQ WQE. */ + /* This field defines the type of CQE. */ #define CQ_CUTOFF_CQE_TYPE_MASK UINT32_C(0x1e) #define CQ_CUTOFF_CQE_TYPE_SFT 1 /* Cut off CQE; for CQ resize see CQ and SRQ Resize */ @@ -74628,7 +85161,9 @@ typedef struct cq_cutoff { * acknowledge this CQ resize operation. When this CQE is * processed, the driver should send a CQ_CUTOFF_ACK doorbell * to the chip to let the chip know that the resize operation - * is complete. This value is used by HW to detect old and + * is complete. + * + * This value is used by HW to detect old and * stale CQ_CUTOFF_ACK doorbells that are caused by having * a backup doorbell location or by PCI or other reordering * problems. Only doorbells with the latest value will be honored. @@ -74639,13 +85174,1227 @@ typedef struct cq_cutoff { #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5 /* This field indicates the status for the CQE. */ uint8_t status; - /* OK is 0 */ + /* The operation completed successfully. */ #define CQ_CUTOFF_STATUS_OK UINT32_C(0x0) #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK uint16_t reserved16; uint32_t reserved32; } cq_cutoff_t, *pcq_cutoff_t; +/* No-Op CQE */ +/* cq_no_op (size:256b/32B) */ + +typedef struct cq_no_op { + uint64_t reserved64_1; + uint64_t reserved64_2; + uint64_t reserved64_3; + uint8_t cqe_type_toggle; + /* + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. + */ + #define CQ_NO_OP_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_NO_OP_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_NO_OP_CQE_TYPE_SFT 1 + /* + * NO-OP completion - This is used to indicate that no operation + * completed. + */ + #define CQ_NO_OP_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1) + #define CQ_NO_OP_CQE_TYPE_LAST CQ_NO_OP_CQE_TYPE_NO_OP + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_NO_OP_STATUS_OK UINT32_C(0x0) + #define CQ_NO_OP_STATUS_LAST CQ_NO_OP_STATUS_OK + uint16_t reserved16; + uint32_t reserved32; +} cq_no_op_t, *pcq_no_op_t; + +/* + * This is the Requester CQE V3 structure. This is used to complete each + * signaled SQ WQE. The sq_cons_idx and opaque is used to indicate + * which WQE has been completed. When a WQE is completed, it indicates + * that all WQEs before it in the SQ are also completed without error. + * Space freed by completed WQEs can be used for new WQEs. + */ +/* cq_req_v3 (size:256b/32B) */ + +typedef struct cq_req_v3 { + /* + * This is an application level ID used to identify the + * QP and its SQ and RQ. + */ + uint64_t qp_handle; + /* + * SQ Consumer Index - points to the entry just past the last WQE + * that has been completed by the chip. Wraps around at QPC.sq_size + * (i.e. the valid range of the SQ Consumer Index is 0 to + * (QPC.sq_size - 1)). The sq_cons_idx is in 16B units (as is + * QPC.sq_size). + * + * User can determine available space in the SQ by comparing + * sq_cons_idx to a sq_prod_idx maintained by the user. When the two + * values are equal, the SQ is empty. When + * (sq_prod_idx+1)%QPC.sq_size==sq_cons_idx, the queue is full. + */ + uint16_t sq_cons_idx; + uint16_t reserved1; + uint32_t reserved2; + uint64_t reserved3; + uint8_t cqe_type_toggle; + /* + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. + */ + #define CQ_REQ_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_REQ_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_REQ_V3_CQE_TYPE_SFT 1 + /* + * Requester completion V3 - This is used for both RC and UD SQ + * completions. + */ + #define CQ_REQ_V3_CQE_TYPE_REQ_V3 (UINT32_C(0x8) << 1) + #define CQ_REQ_V3_CQE_TYPE_LAST CQ_REQ_V3_CQE_TYPE_REQ_V3 + /* + * When this bit is '1', it indicates that the packet completed + * was transmitted using the push accelerated data provided by + * the driver. When this bit is '0', it indicates that the packet + * had not push acceleration data written or was executed as a + * normal packet even though push data was provided. + * + * Note: This field is intended to be used for driver-generated push + * statistics. As such, It is not applicable for RC since not all + * RC packets return a CQE. + */ + #define CQ_REQ_V3_PUSH UINT32_C(0x20) + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_REQ_V3_STATUS_OK UINT32_C(0x0) + /* + * An unexpected BTH opcode or a First/Middle packet that is not + * the full MTU size was returned by the responder. + * + * This is a fatal error detected by the requester Rx. + */ + #define CQ_REQ_V3_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1) + /* + * Generated for a WQE posted to the local SQ when the sum of the + * lengths of the SGEs in the WQE exceeds the maximum message + * length of 2^31 bytes. + * + * Generated for a WQE posted to the local RQ/SRQ when the sum of + * the lengths of the SGEs in the WQE is too small to receive the + * (valid) incoming message or the length of the incoming message + * is greater than the maximum message size supported. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_REQ_V3_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_REQ_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_REQ_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * The SSC detected an error on a local memory operation from the + * SQ (fast-register, local invalidate, or bind). + * + * This is a fatal error detected by the requester Tx. + */ + #define CQ_REQ_V3_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x7) + /* + * An invalid message was received by the responder. This could be + * an operation that is not supported by this QP, an IRRQ overflow + * error, or the length in an RDMA operation is greater than the + * maximum message size (2^31 bytes). + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Invalid Request. For responder + * CQEs, only the opaque field is valid. + */ + #define CQ_REQ_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8) + /* + * A protection error occurred on a remote data buffer to be read + * by an RDMA Read, written by an RDMA Write or accessed by an + * atomic operation. This error is reported only on RDMA operations + * or atomic operations. + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Remote Access Violation. + */ + #define CQ_REQ_V3_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x9) + /* + * The operation could not be completed successfully by the + * responder. Possible causes include an RQ/SRQ WQE format error, + * an SSC error when validating an SGE from an RQ/SRQ WQE, or the + * message received was too long for the RQ/SRQ WQE. + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Remote Operation Error. + */ + #define CQ_REQ_V3_STATUS_REMOTE_OPERATION_ERR UINT32_C(0xa) + /* + * The RNR NAK retry count was exceeded while trying to send this + * message. + * + * This is a fatal error detected by the requester. + */ + #define CQ_REQ_V3_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0xb) + /* + * The local transport timeout retry counter was exceeded while + * trying to send this message. + * + * This is a fatal error detected by the requester. + */ + #define CQ_REQ_V3_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xc) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_REQ_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_REQ_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_REQ_V3_STATUS_LAST CQ_REQ_V3_STATUS_OVERFLOW_ERR + uint16_t reserved4; + /* This value is from the WQE that is being completed. */ + uint32_t opaque; +} cq_req_v3_t, *pcq_req_v3_t; + +/* + * This is the Responder RQ/SRQ CQE V3 structure for RC QPs. This is + * used to complete each RQ/SRQ WQE. When the WQE is completed, it + * indicates that there is room for one more WQE on the corresponding + * RQ/SRQ. + * + * User can determine available space in the RQ/SRQ by comparing + * a rq_cons_idx to a rq_prod_idx, both maintained by the user. The + * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The + * rq_prod_idx value increments by one for each WQE that is added to + * the RQ/SRQ by the user. Value must be wrapped at rq_size. The + * rq_cons_idx value increments by one for each WQE that is completed + * from that particular RQ/SRQ. The qp_handle can be used by the user + * to determine what RQ/SRQ to increment. Value must also be wrapped at + * rq_size. When the two values are equal, the RQ/SRQ is empty. When + * (rq_prod_idx+1)%QPC.rq_size==rq_cons_idx, the queue is full. + */ +/* cq_res_rc_v3 (size:256b/32B) */ + +typedef struct cq_res_rc_v3 { + /* + * The length of the message's payload in bytes, stored in + * the SGEs + */ + uint32_t length; + /* + * Immediate data in case the imm_flag set, R_Key to be + * invalidated in case inv_flag is set. + */ + uint32_t imm_data_or_inv_r_key; + /* + * This is an application level ID used to identify the + * QP and its SQ and RQ. + */ + uint64_t qp_handle; + /* + * Opaque value - valid when inv_flag is set. Used by driver + * to reference the buffer used to store PBL when the MR was + * fast registered. The driver can reclaim this buffer after + * an MR was remotely invalidated. The controller take that + * value from the MR referenced by R_Key + */ + uint64_t mr_handle; + uint8_t cqe_type_toggle; + /* + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. + */ + #define CQ_RES_RC_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_RC_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_RC_V3_CQE_TYPE_SFT 1 + /* + * Responder RC Completion - This is used for both RQ and SRQ + * completions for RC service QPs. + */ + #define CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 (UINT32_C(0x9) << 1) + #define CQ_RES_RC_V3_CQE_TYPE_LAST CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_RES_RC_V3_STATUS_OK UINT32_C(0x0) + /* + * Generated for a WQE posted to the local SQ when the sum of the + * lengths of the SGEs in the WQE exceeds the maximum message + * length of 2^31 bytes. + * + * Generated for a WQE posted to the local RQ/SRQ when the sum of + * the lengths of the SGEs in the WQE is too small to receive the + * (valid) incoming message or the length of the incoming message + * is greater than the maximum message size supported. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_RC_V3_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2) + /* + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_RC_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_RC_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * A protection error occurred on a local data buffer during the + * processing of a RDMA Write with Immediate Data operation sent + * from the remote node. + * + * This is a fatal error detected by the responder Rx. Only the + * opaque field in the CQE is valid. + */ + #define CQ_RES_RC_V3_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x6) + /* + * An invalid message was received by the responder. This could be + * an operation that is not supported by this QP, an IRRQ overflow + * error, or the length in an RDMA operation is greater than the + * maximum message size (2^31 bytes). + * + * This is a fatal error detected by the responder and communicated + * back to the requester using a NAK-Invalid Request. For responder + * CQEs, only the opaque field is valid. + */ + #define CQ_RES_RC_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_RES_RC_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. + */ + #define CQ_RES_RC_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_RES_RC_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_RES_RC_V3_STATUS_LAST CQ_RES_RC_V3_STATUS_OVERFLOW_ERR + uint16_t flags; + /* + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. + */ + #define CQ_RES_RC_V3_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_RC_V3_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_RC_V3_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_RC_V3_FLAGS_SRQ_LAST CQ_RES_RC_V3_FLAGS_SRQ_SRQ + /* Immediate data indicator */ + #define CQ_RES_RC_V3_FLAGS_IMM UINT32_C(0x2) + /* R_Key invalidate indicator */ + #define CQ_RES_RC_V3_FLAGS_INV UINT32_C(0x4) + #define CQ_RES_RC_V3_FLAGS_RDMA UINT32_C(0x8) + /* CQE relates to an incoming Send request */ + #define CQ_RES_RC_V3_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3) + /* CQE relates to incoming RDMA Write request */ + #define CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3) + #define CQ_RES_RC_V3_FLAGS_RDMA_LAST CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE + /* This value is from the WQE that is being completed. */ + uint32_t opaque; +} cq_res_rc_v3_t, *pcq_res_rc_v3_t; + +/* + * This is the Responder RQ/SRQ CQE V3 structure for UD QPs and QP1 QPs + * that are treated as UD. This is used to complete RQ/SRQ WQE's. When + * the WQE is completed, it indicates that there is room for one more + * WQE on the corresponding RQ/SRQ. + * + * User can determine available space in the RQ/SRQ by comparing + * a rq_cons_idx to a rq_prod_idx, both maintained by the user. The + * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The + * rq_prod_idx value increments by one for each WQE that is added to + * the RQ/SRQ by the user. Value must be wrapped at rq_size. The + * rq_cons_idx value increments by one for each WQE that is completed + * from that particular RQ/SRQ. The qp_handle can be used by the user + * to determine what RQ/SRQ to increment. Value must also be wrapped at + * rq_size. When the two values are equal, the RQ/SRQ is empty. When + * (rq_prod_idx+1)%QPC.rq_size==rq_cons_idx, the queue is full. + */ +/* cq_res_ud_v3 (size:256b/32B) */ + +typedef struct cq_res_ud_v3 { + uint16_t length; + /* + * The length of the message's payload in bytes, stored in + * the SGEs + */ + #define CQ_RES_UD_V3_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_UD_V3_LENGTH_SFT 0 + uint8_t reserved1; + /* Upper 8b of the Source QP value from the DETH header. */ + uint8_t src_qp_high; + /* Immediate data in case the imm_flag set. */ + uint32_t imm_data; + /* + * This is an application level ID used to identify the + * QP and its SQ and RQ. + */ + uint64_t qp_handle; + /* + * Source MAC address for the UD message placed in the WQE + * that is completed by this CQE. + */ + uint16_t src_mac[3]; + /* Lower 16b of the Source QP value from the DETH header. */ + uint16_t src_qp_low; + uint8_t cqe_type_toggle; + /* + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. + */ + #define CQ_RES_UD_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_UD_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_UD_V3_CQE_TYPE_SFT 1 + /* + * Responder UD Completion - This is used for both RQ and SRQ + * completion for UD service QPs. It is also used for QP1 QPs + * that are treated as UD. + */ + #define CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 (UINT32_C(0xa) << 1) + #define CQ_RES_UD_V3_CQE_TYPE_LAST CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_RES_UD_V3_STATUS_OK UINT32_C(0x0) + /* + * This indicates that the packet was too long for the WQE provided + * on the SRQ/RQ. + * + * This is not a fatal error. All the fields in the CQE are valid. + */ + #define CQ_RES_UD_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3) + /* + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_UD_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_UD_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_RES_UD_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. + */ + #define CQ_RES_UD_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_RES_UD_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_RES_UD_V3_STATUS_LAST CQ_RES_UD_V3_STATUS_OVERFLOW_ERR + uint16_t flags; + /* + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. + */ + #define CQ_RES_UD_V3_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_UD_V3_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_UD_V3_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_UD_V3_FLAGS_SRQ_LAST CQ_RES_UD_V3_FLAGS_SRQ_SRQ + /* Immediate data indicator */ + #define CQ_RES_UD_V3_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_UD_V3_FLAGS_UNUSED_MASK UINT32_C(0xc) + #define CQ_RES_UD_V3_FLAGS_UNUSED_SFT 2 + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_SFT 4 + /* RoCEv1 Message */ + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) + /* RoCEv2 IPv4 Message */ + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) + /* RoCEv2 IPv6 Message */ + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) + #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 + /* This value is from the WQE that is being completed. */ + uint32_t opaque; +} cq_res_ud_v3_t, *pcq_res_ud_v3_t; + +/* + * This is the Responder RQ/SRQ CQE V3 structure for RawEth. This is + * used to complete RQ/SRQ WQE's. When the WQE is completed, it + * indicates that there is room for one more WQE on the corresponding + * RQ/SRQ. + * + * User can determine available space in the RQ/SRQ by comparing + * a rq_cons_idx to a rq_prod_idx, both maintained by the user. The + * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The + * rq_prod_idx value increments by one for each WQE that is added to + * the RQ/SRQ by the user. Value must be wrapped at rq_size. The + * rq_cons_idx value increments by one for each WQE that is completed + * from that particular RQ/SRQ. The qp_handle can be used by the user + * to determine what RQ/SRQ to increment. Value must also be wrapped at + * rq_size. When the two values are equal, the RQ/SRQ is empty. When + * (rq_prod_idx+1)%QPC.rq_size==rq_cons_idx, the queue is full. + */ +/* cq_res_raweth_qp1_v3 (size:256b/32B) */ + +typedef struct cq_res_raweth_qp1_v3 { + uint16_t length; + /* + * The length of the message's payload in bytes, stored in + * the SGEs + */ + #define CQ_RES_RAWETH_QP1_V3_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_RAWETH_QP1_V3_LENGTH_SFT 0 + uint16_t raweth_qp1_flags_cfa_metadata1; + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * raweth_qp1_errors. + */ + #define CQ_RES_RAWETH_QP1_V3_ERROR UINT32_C(0x1) + /* + * This value indicates what the inner packet determined for the + * packet was. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_MASK UINT32_C(0x3c0) + #define CQ_RES_RAWETH_QP1_V3_ITYPE_SFT 6 + /* + * Not Known: + * Indicates that the packet type was not known. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6) + /* + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_IP (UINT32_C(0x1) << 6) + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_TCP (UINT32_C(0x2) << 6) + /* + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_UDP (UINT32_C(0x3) << 6) + /* + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the raweth_qp1_payload_offset field is + * valid. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_FCOE (UINT32_C(0x4) << 6) + /* + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the raweth_qp1_payload_offset field is + * valid. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_ROCE (UINT32_C(0x5) << 6) + /* + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the raweth_qp1_payload_offset field is + * valid. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_ICMP (UINT32_C(0x7) << 6) + /* + * PtP packet wo/timestamp: + * Indicates that the packet was recognized as a PtP + * packet. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6) + /* + * PtP packet w/timestamp: + * Indicates that the packet was recognized as a PtP + * packet and that a timestamp was taken for the packet. + */ + #define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6) + #define CQ_RES_RAWETH_QP1_V3_ITYPE_LAST CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_MASK UINT32_C(0xf000) + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_SFT 12 + /* When meta_format != 0, this value is the VLAN valid. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_VALID UINT32_C(0x8000) + uint16_t raweth_qp1_errors; + /* + * This indicates that there was an error in the IP header + * checksum. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10) + /* + * This indicates that there was an error in the TCP, UDP + * or ICMP checksum. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20) + /* + * This indicates that there was an error in the tunnel + * IP header checksum. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40) + /* + * This indicates that there was an error in the tunnel + * UDP checksum. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) + /* + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100) + /* + * This indicates that there was an error in the tunnel + * portion of the packet when this + * field is non-zero. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9 + /* + * No additional error occurred on the tunnel portion + * of the packet of the packet does not have a tunnel. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9) + /* + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 + * in the tunnel header. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9) + /* + * Indicates that header length is out of range in the + * tunnel header. Valid for + * IPv4. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9) + /* + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 + * tunnel packet packets. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 9) + /* + * Indicates that the physical packet is shorter than that + * claimed by the tunnel UDP header length for a tunnel + * UDP packet that is not fragmented. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 9) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0) in the tunnel header. Valid + * for IPv4, and IPv6. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9) + /* + * Indicates that the physical packet is shorter than that + * claimed by the tunnel header length. Valid for GTPv1-U + * packets. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (UINT32_C(0x6) << 9) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR + /* + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12 + /* + * No additional error occurred on the tunnel portion + * of the packet of the packet does not have a tunnel. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12) + /* + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12) + /* + * indicates that header length is out of range. Valid for + * IPv4 and RoCE + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12) + /* + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12) + /* + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12) + /* + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN + /* This is data from the CFA as indicated by the meta_format field. */ + uint16_t cfa_metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff) + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_SFT 13 + /* + * This is an application level ID used to identify the + * QP and its SQ and RQ. + */ + uint64_t qp_handle; + uint32_t raweth_qp1_flags2; + /* + * This indicates that the ip checksum was calculated for the + * inner packet and that the ip_cs_error field indicates if there + * was an error. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1) + /* + * This indicates that the TCP, UDP or ICMP checksum was + * calculated for the inner packet and that the l4_cs_error field + * indicates if there was an error. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2) + /* + * This indicates that the ip checksum was calculated for the + * tunnel header and that the t_ip_cs_error field indicates if + * there was an error. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + /* + * This indicates that the UDP checksum was + * calculated for the tunnel packet and that the t_l4_cs_error + * field indicates if there was an error. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) + /* The field indicates what format the metadata field is. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4 + /* No metadata information. Values are zero. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the table scope + * and action record pointer. + * + * - metadata2[25:0] contains the action record pointer. + * - metadata2[31:26] contains the table scope. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the Tunnel ID value, justified + * to LSB. + * + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * + * The metadata2 field contains the 32b metadata from the + * prepended header (chdr_data). + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE UINT32_C(0x400) + /* Indicates that the Tunnel IP type was IPv4. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 10) + /* Indicates that the Tunnel IP type was IPv6. */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 10) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_LAST CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 + /* + * This value is the complete 1's complement checksum calculated + * from the start of the outer L3 header to the end of the packet + * (not including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. + */ + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000) + #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + * + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + */ + uint32_t cfa_metadata2; + uint8_t cqe_type_toggle; + /* + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries. + */ + #define CQ_RES_RAWETH_QP1_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_SFT 1 + /* + * Responder RawEth and QP1 Completion - This is used for RQ and + * SRQ completion for RawEth service. It is also used for QP1 QPs + * that are treated as RawEth. + */ + #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 (UINT32_C(0xb) << 1) + #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_RES_RAWETH_QP1_V3_STATUS_OK UINT32_C(0x0) + /* + * This indicates that the packet was too long for the WQE provided + * on the SRQ/RQ. + * + * This is not a fatal error. All the fields in the CQE are valid. + */ + #define CQ_RES_RAWETH_QP1_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3) + /* + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_RES_RAWETH_QP1_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. + */ + #define CQ_RES_RAWETH_QP1_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_RES_RAWETH_QP1_V3_STATUS_LAST CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR + uint8_t flags; + /* + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. + */ + #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ + /* + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for + * TCP, UDP, FCoE, and RoCE packets. + * + * A value of zero indicates an offset of 256 bytes. + */ + uint8_t raweth_qp1_payload_offset; + /* This value is from the WQE that is being completed. */ + uint32_t opaque; +} cq_res_raweth_qp1_v3_t, *pcq_res_raweth_qp1_v3_t; + +/* + * This is the Responder RQ/SRQ CQE V3 structure for UD QPs and QP1 QPs + * treated as UD. This is used to complete RQ/SRQ WQE's. It differs + * from the Res_UD CQE in that it carries additional CFA fields, in + * place of the QP handle. (Instead of the QP handle, this CQE carries + * the QID. It is up to the user to map the QID back to a QP handle.) + * When the WQE is completed, it indicates that there is room for one + * more WQE on the corresponding RQ/SRQ. + * + * User can determine available space in the RQ/SRQ by comparing + * a rq_cons_idx to a rq_prod_idx, both maintained by the user. The + * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The + * rq_prod_idx value increments by one for each WQE that is added to + * the RQ/SRQ by the user. Value must be wrapped at rq_size. The + * rq_cons_idx value increments by one for each WQE that is completed + * from that particular RQ/SRQ. The qp_handle can be used by the user + * to determine what RQ/SRQ to increment. Value must also be wrapped at + * rq_size. When the two values are equal, the RQ/SRQ is empty. When + * (rq_prod_idx+1)%QPC.rq_size==rq_cons_idx, the queue is full. + */ +/* cq_res_ud_cfa_v3 (size:256b/32B) */ + +typedef struct cq_res_ud_cfa_v3 { + uint16_t length; + /* + * The length of the message's payload in bytes, stored in + * the SGEs + */ + #define CQ_RES_UD_CFA_V3_LENGTH_MASK UINT32_C(0x3fff) + #define CQ_RES_UD_CFA_V3_LENGTH_SFT 0 + /* This is data from the CFA as indicated by the meta_format field. */ + uint16_t cfa_metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff) + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000) + #define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_SFT 13 + /* Immediate data in case the imm_flag set. */ + uint32_t imm_data; + uint32_t qid_cfa_metadata1_src_qp_high; + /* + * This value indicates the QPID associated with this operation. + * + * The driver will use the qid from this CQE to map a QP handle + * in the completion record returned to the application. + */ + #define CQ_RES_UD_CFA_V3_QID_MASK UINT32_C(0x7ff) + #define CQ_RES_UD_CFA_V3_QID_SFT 0 + #define CQ_RES_UD_CFA_V3_UNUSED_MASK UINT32_C(0xff800) + #define CQ_RES_UD_CFA_V3_UNUSED_SFT 11 + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_MASK UINT32_C(0xf00000) + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_SFT 20 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000) + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_SFT 20 + /* When meta_format != 0, this value is the VLAN valid. */ + #define CQ_RES_UD_CFA_V3_CFA_METADATA1_VALID UINT32_C(0x800000) + /* Upper 8b of the Source QP value from the DETH header. */ + #define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_MASK UINT32_C(0xff000000) + #define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_SFT 24 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + * + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + */ + uint32_t cfa_metadata2; + /* + * Source MAC address for the UD message placed in the WQE + * that is completed by this CQE. + */ + uint16_t src_mac[3]; + /* Lower 16b of the Source QP value from the DETH header. */ + uint16_t src_qp_low; + uint8_t cqe_type_toggle; + /* + * Indicate valid completion - written by the chip. The NIC + * toggles this bit each time it finished consuming all PBL + * entries + */ + #define CQ_RES_UD_CFA_V3_TOGGLE UINT32_C(0x1) + /* This field defines the type of CQE. */ + #define CQ_RES_UD_CFA_V3_CQE_TYPE_MASK UINT32_C(0x1e) + #define CQ_RES_UD_CFA_V3_CQE_TYPE_SFT 1 + /* + * Responder UD Completion with CFA - This is used for both RQ + * and SRQ completion for UD service QPs. It includes cfa fields + * (some of which carry VLAN information), in place of the QP + * handle. It is also used for QP1 QPs that are treated as UD. + */ + #define CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 (UINT32_C(0xc) << 1) + #define CQ_RES_UD_CFA_V3_CQE_TYPE_LAST CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 + /* This field indicates the status for the CQE. */ + uint8_t status; + /* The operation completed successfully. */ + #define CQ_RES_UD_CFA_V3_STATUS_OK UINT32_C(0x0) + /* + * This indicates that the packet was too long for the WQE provided + * on the SRQ/RQ. + * + * This is not a fatal error. All the fields in the CQE are valid. + */ + #define CQ_RES_UD_CFA_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3) + /* + * An internal QP consistency error was detected while processing + * this Work Request. For requester, this could be an SQ WQE format + * error or an operation specified in the WQE that is not supported + * for the QP. For responder, this is an RQ/SRQ WQE format error. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_UD_CFA_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4) + /* + * An SGE in the locally posted WQE does not reference a Memory + * Region that is valid for the requested operation. If this error + * is generated for an SGE using the reserved l_key, this means + * that the reserved l_key is not enabled. + * + * This is a fatal error detected by the requester Tx or responder + * Rx. For responder CQEs, only the opaque field is valid. + */ + #define CQ_RES_UD_CFA_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5) + /* + * A WQE was in process or outstanding when the QP transitioned + * into the Error State. + */ + #define CQ_RES_UD_CFA_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd) + /* + * A WQE had already been taken off the RQ/SRQ when a fatal error + * was detected on responder Rx. Only the opaque field in the CQE + * is valid. + */ + #define CQ_RES_UD_CFA_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe) + /* + * A WQE was posted to the SQ/RQ that caused it to overflow. For + * requester CQEs, it was the SQ that overflowed. For responder + * CQEs, it was the RQ that overflowed. + */ + #define CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf) + #define CQ_RES_UD_CFA_V3_STATUS_LAST CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR + uint16_t flags; + /* + * This flag indicates that the completion is for a SRQ entry + * rather than for an RQ entry. + */ + #define CQ_RES_UD_CFA_V3_FLAGS_SRQ UINT32_C(0x1) + /* CQE relates to RQ WQE. */ + #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_RQ UINT32_C(0x0) + /* CQE relates to SRQ WQE. */ + #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ UINT32_C(0x1) + #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ + /* Immediate data indicator */ + #define CQ_RES_UD_CFA_V3_FLAGS_IMM UINT32_C(0x2) + #define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_MASK UINT32_C(0xc) + #define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_SFT 2 + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30) + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_SFT 4 + /* RoCEv1 Message */ + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4) + /* RoCEv2 IPv4 Message */ + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4) + /* RoCEv2 IPv6 Message */ + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4) + #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 + /* The field indicates what format the metadata field is. */ + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0) + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_SFT 6 + /* No metadata information. Value is zero. */ + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the table scope + * and action record pointer. + * + * - metadata2[25:0] contains the action record pointer. + * - metadata2[31:26] contains the table scope. + */ + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. + * + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * + * The metadata2 field contains the 32b metadata from the + * prepended header (chdr_data). + */ + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6) + #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET + /* + * This value will be returned in the completion if the completion is + * signaled. + */ + uint32_t opaque; +} cq_res_ud_cfa_v3_t, *pcq_res_ud_cfa_v3_t; + /* nq_base (size:128b/16B) */ typedef struct nq_base { @@ -74653,8 +86402,8 @@ typedef struct nq_base { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define NQ_BASE_TYPE_MASK UINT32_C(0x3f) @@ -74669,7 +86418,9 @@ typedef struct nq_base { #define NQ_BASE_TYPE_QP_EVENT UINT32_C(0x38) /* Function Async Notification */ #define NQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a) - #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT + /* NQ Reassign Notification */ + #define NQ_BASE_TYPE_NQ_REASSIGN UINT32_C(0x3c) + #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_NQ_REASSIGN /* info10 is 10 b */ #define NQ_BASE_INFO10_MASK UINT32_C(0xffc0) #define NQ_BASE_INFO10_SFT 6 @@ -74681,8 +86432,8 @@ typedef struct nq_base { uint64_t info63_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define NQ_BASE_V UINT32_C(0x1) /* info63 is 63 b */ @@ -74698,8 +86449,8 @@ typedef struct nq_cn { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define NQ_CN_TYPE_MASK UINT32_C(0x3f) @@ -74711,25 +86462,31 @@ typedef struct nq_cn { * This field carries the toggle value that must be used to * re-arm this CQ. The toggle value should be copied into the * doorbell used to CQ_ARMENA, CQ_ARMALL or CQ_ARMSE doorbells. + * + * This value is used by HW to detect old and stale CQ_ARMENA, + * CQ_ARMALL, or CQ_ARMSE doorbells that are caused by having + * a backup doorbell location or by PCI or other reordering + * problems. Only the doorbells that match the latest value of + * toggle will be honored. */ #define NQ_CN_TOGGLE_MASK UINT32_C(0xc0) #define NQ_CN_TOGGLE_SFT 6 uint16_t reserved16; /* * This is an application level ID used to identify the - * CQ. This field carries the lower 32b of the value. + * CQ. This field carries the lower 32b of the value. */ uint32_t cq_handle_low; uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define NQ_CN_V UINT32_C(0x1) /* * This is an application level ID used to identify the - * CQ. This field carries the upper 32b of the value. + * CQ. This field carries the upper 32b of the value. */ uint32_t cq_handle_high; } nq_cn_t, *pnq_cn_t; @@ -74742,9 +86499,8 @@ typedef struct nq_srq_event { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B records. */ #define NQ_SRQ_EVENT_TYPE_MASK UINT32_C(0x3f) #define NQ_SRQ_EVENT_TYPE_SFT 0 @@ -74769,20 +86525,20 @@ typedef struct nq_srq_event { uint16_t reserved16; /* * This is the SRQ handle value for the queue that has - * reached it's event threshold. This field carries the + * reached it's event threshold. This field carries the * lower 32b of the value. */ uint32_t srq_handle_low; uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define NQ_SRQ_EVENT_V UINT32_C(0x1) /* * This is the SRQ handle value for the queue that has - * reached it's event threshold. This field carries the + * reached it's event threshold. This field carries the * upper 32b of the value. */ uint32_t srq_handle_high; @@ -74796,8 +86552,8 @@ typedef struct nq_dbq_event { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define NQ_DBQ_EVENT_TYPE_MASK UINT32_C(0x3f) @@ -74831,14 +86587,14 @@ typedef struct nq_dbq_event { uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define NQ_DBQ_EVENT_V UINT32_C(0x1) uint32_t db_type_db_xid; /* * DB 'XID' field from doorbell that crossed the async event - * threshold. This is a QPID, SID, or CID, depending on + * threshold. This is a QPID, SID, or CID, depending on * the db_type field. */ #define NQ_DBQ_EVENT_DB_XID_MASK UINT32_C(0xfffff) @@ -74851,6 +86607,46 @@ typedef struct nq_dbq_event { #define NQ_DBQ_EVENT_DB_TYPE_SFT 28 } nq_dbq_event_t, *pnq_dbq_event_t; +/* + * This completion indicates that the NQ Reassign doorbell has been + * executed by the CQ processing block and no further NQE will arrive + * for this CQ on this NQ. + */ +/* nq_reassign (size:128b/16B) */ + +typedef struct nq_reassign { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B records. + */ + #define NQ_REASSIGN_TYPE_MASK UINT32_C(0x3f) + #define NQ_REASSIGN_TYPE_SFT 0 + /* NQ Reassign Notification */ + #define NQ_REASSIGN_TYPE_NQ_REASSIGN UINT32_C(0x3c) + #define NQ_REASSIGN_TYPE_LAST NQ_REASSIGN_TYPE_NQ_REASSIGN + uint16_t reserved16; + /* + * This is an application level ID used to identify the + * CQ. This field carries the lower 32b of the value. + */ + uint32_t cq_handle_low; + uint32_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define NQ_REASSIGN_V UINT32_C(0x1) + /* + * This is an application level ID used to identify the + * CQ. This field carries the upper 32b of the value. + */ + uint32_t cq_handle_high; +} nq_reassign_t, *pnq_reassign_t; + /* Input Read Request Queue (IRRQ) Message */ /* xrrq_irrq (size:256b/32B) */ @@ -74879,9 +86675,9 @@ typedef struct xrrq_irrq { uint32_t msn; /* * The value of QPC.pending_ack_msn after it is incremented as a - * result of receiving the read/atomic request. IRRQ.msn-1 will be - * placed in the MSN field of the first response and IRRQ.msn will - * placed in the MSN field of the last or only response. + * result of receiving the read/atomic request. IRRQ.msn-1 will + * be placed in the MSN field of the first response and IRRQ.msn + * will placed in the MSN field of the last or only response. */ #define XRRQ_IRRQ_MSN_MASK UINT32_C(0xffffff) #define XRRQ_IRRQ_MSN_SFT 0 @@ -74897,7 +86693,10 @@ typedef struct xrrq_irrq { uint64_t va_or_atomic_result; /* The key to the MR/W in the request */ uint32_t rdma_r_key; - /* Length in bytes of the data requested. Length must be 8 if type is atomic. */ + /* + * Length in bytes of the data requested. Length must be 8 if type is + * atomic. + */ uint32_t length; } xrrq_irrq_t, *pxrrq_irrq_t; @@ -74926,18 +86725,21 @@ typedef struct xrrq_orrq { * If num_sges is 2 or more for an RDMA Read request, then * the first_sge_phy_or_sing_sge_va field carries the * physical address in host memory where the first sge is - * stored. The single_sge_l_key and single_sge_size fields + * stored. The single_sge_l_key and single_sge_size fields * are unused in this case. * * A special case is a zero-length, zero-sge RDMA read request - * WQE. In this situation, num_sges will be 1. However, + * WQE. In this situation, num_sges will be 1. However, * first_sge_phy_or_sing_sge_va, single_sge_l_key, and * single_sge_size will all be populated with zeros. */ #define XRRQ_ORRQ_NUM_SGES_MASK UINT32_C(0xf800) #define XRRQ_ORRQ_NUM_SGES_SFT 11 uint16_t reserved16; - /* Length in bytes of the data requested. Length must be 8 if type is atomic. */ + /* + * Length in bytes of the data requested. Length must be 8 if type is + * atomic. + */ uint32_t length; uint32_t psn; /* The PSN of the outstanding outgoing request */ @@ -74973,25 +86775,25 @@ typedef struct xrrq_orrq { typedef struct ptu_pte { uint64_t page_next_to_last_last_valid; /* - * This field indicates if the PTE is valid. A value of '0' - * indicates that the page is not valid. A value of '1' - * indicates that the page is valid. A reference to an + * This field indicates if the PTE is valid. A value of '0' + * indicates that the page is not valid. A value of '1' + * indicates that the page is valid. A reference to an * invalid page will return a PTU error. */ #define PTU_PTE_VALID UINT32_C(0x1) /* * This field is used only for "ring" PBLs that are used for - * SQ, RQ, SRQ, or CQ structures. For all other PBL structures, - * this bit should be zero. When this bit is '1', it indicates + * SQ, RQ, SRQ, or CQ structures. For all other PBL structures, + * this bit should be zero. When this bit is '1', it indicates * that the page pointed to by this PTE is the last page in the - * ring. A prefetch for the ring should use the first PTE in + * ring. A prefetch for the ring should use the first PTE in * the PBL. */ #define PTU_PTE_LAST UINT32_C(0x2) /* * This field is used only for "ring" PBLs that are used for - * SQ, RQ, SRQ, or CQ structures. For all other PBL structures, - * this bit should be zero. When this bit is '1', it indicates + * SQ, RQ, SRQ, or CQ structures. For all other PBL structures, + * this bit should be zero. When this bit is '1', it indicates * that this is the next-to-last page of the PBL. */ #define PTU_PTE_NEXT_TO_LAST UINT32_C(0x4) @@ -75000,10 +86802,10 @@ typedef struct ptu_pte { #define PTU_PTE_UNUSED_SFT 3 /* * This is the upper bits of the physical page controlled by - * this PTE. If the page is larger than 4KB, then the unused + * this PTE. If the page is larger than 4KB, then the unused * lower bits of the page address should be zero. */ - #define PTU_PTE_PAGE_MASK UINT32_C(0xfffff000) + #define PTU_PTE_PAGE_MASK UINT32_C(0xfffffffffffff000)L #define PTU_PTE_PAGE_SFT 12 } ptu_pte_t, *pptu_pte_t; @@ -75013,9 +86815,9 @@ typedef struct ptu_pte { typedef struct ptu_pde { uint64_t page_valid; /* - * This field indicates if the PTE is valid. A value of '0' - * indicates that the page is not valid. A value of '1' - * indicates that the page is valid. A reference to an + * This field indicates if the PTE is valid. A value of '0' + * indicates that the page is not valid. A value of '1' + * indicates that the page is valid. A reference to an * invalid page will return a PTU error. */ #define PTU_PDE_VALID UINT32_C(0x1) @@ -75024,15 +86826,15 @@ typedef struct ptu_pde { #define PTU_PDE_UNUSED_SFT 1 /* * This is the upper bits of the physical page controlled by - * this PTE. If the page is larger than 4KB, then the unused + * this PTE. If the page is larger than 4KB, then the unused * lower bits of the page address should be zero. */ - #define PTU_PDE_PAGE_MASK UINT32_C(0xfffff000) + #define PTU_PDE_PAGE_MASK UINT32_C(0xfffffffffffff000)L #define PTU_PDE_PAGE_SFT 12 } ptu_pde_t, *pptu_pde_t; /* - * This is the 64b doorbell format. The host writes this message + * This is the 64b doorbell format. The host writes this message * format directly to byte offset 0 of the appropriate doorbell page. */ /* dbc_dbc (size:64b/8B) */ @@ -75072,11 +86874,11 @@ typedef struct dbc_dbc { /* * The toggle value is used in CQ_ARMENA, CQ_ARMSE, CQ_ARMALL, * SRQ_ARMENA, SRQ_ARM, and CQ_CUTOFF_ACK doorbells to qualify the - * doorbell as valid. This value should be taken from the latest + * doorbell as valid. This value should be taken from the latest * NQE or cutoff completion. * * Doorbells of the above types with the wrong toggle value will - * be ignored. This is how old values in of backup doorbells + * be ignored. This is how old values in of backup doorbells * are ignored. */ #define DBC_DBC_TOGGLE_MASK UINT32_C(0x6000000) @@ -75086,7 +86888,7 @@ typedef struct dbc_dbc { * This value identifies the resource that the doorbell is intended * to notify. * - * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For + * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For * CQ, this is the CID. For NQ, this is the NID. * * Bits [19:16] of this values must be zero for a SID value. @@ -75124,20 +86926,20 @@ typedef struct dbc_dbc { #define DBC_DBC_TYPE_MASK UINT32_C(0xf0000000) #define DBC_DBC_TYPE_SFT 28 /* - * This is a SQ producer index update. It indicates one or more + * This is a SQ producer index update. It indicates one or more * new entries have been written to the SQ for the QPID indicated * on the xID field. This type is valid for L2, RoCE and Engine * path. */ #define DBC_DBC_TYPE_SQ (UINT32_C(0x0) << 28) /* - * This is a RQ producer index update. It indicates one or more + * This is a RQ producer index update. It indicates one or more * new entries have been written to the RQ for the QPID indicated * on the xID field. This type is valid for RoCE path. */ #define DBC_DBC_TYPE_RQ (UINT32_C(0x1) << 28) /* - * This is a SRQ producer index update. It indicates one or more + * This is a SRQ producer index update. It indicates one or more * new entries have been written to the SRQ for the SID indicated * on the xID field. This type is valid for L2 and RoCE path. */ @@ -75151,7 +86953,7 @@ typedef struct dbc_dbc { */ #define DBC_DBC_TYPE_SRQ_ARM (UINT32_C(0x3) << 28) /* - * This is a CQ consumer index update. It indicates one or more + * This is a CQ consumer index update. It indicates one or more * entries have been processed off the CQ indicated on the xID * field.This type is valid for L2, RoCE and Engine path. */ @@ -75168,7 +86970,7 @@ typedef struct dbc_dbc { */ #define DBC_DBC_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) /* - * This is a CQ arm enable message. This message must be sent + * This is a CQ arm enable message. This message must be sent * from the privileged driver before a new CQ_ARMSE or CQ_ARMALL * message will be accepted. * @@ -75178,7 +86980,7 @@ typedef struct dbc_dbc { #define DBC_DBC_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28) /* * This doorbell command enables the SRQ async event - * to be armed. This message must be sent from the privileged + * to be armed. This message must be sent from the privileged * driver before a new SRQ_ARM message will be accepted. * The xID field must identify the SID that is begin enabled * for arm. @@ -75227,7 +87029,7 @@ typedef struct dbc_dbc { } dbc_dbc_t, *pdbc_dbc_t; /* - * This is the 32b doorbell format. The host writes this message + * This is the 32b doorbell format. The host writes this message * format directly to byte offset 8 of the appropriate doorbell page. */ /* dbc_dbc32 (size:32b/4B) */ @@ -75238,7 +87040,7 @@ typedef struct dbc_dbc32 { * This value identifies the resource that the doorbell is intended * to notify. * - * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For + * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For * CQ, this is the CID. * * Bits [19:16] of this values must be zero for a SID value. @@ -75260,8 +87062,8 @@ typedef struct dbc_dbc32 { * When abs=0, this value is the value to add to the appropriate * index value. * - * When abs=1, this value is the new value for the index. Absolute - * value is used when the queue is being wrapped. When abs=1, + * When abs=1, this value is the new value for the index. Absolute + * value is used when the queue is being wrapped. When abs=1, * the incr value follows the same rules as the index value * in the 64b doorbell. */ @@ -75273,46 +87075,47 @@ typedef struct dbc_dbc32 { #define DBC_DBC32_TYPE_MASK UINT32_C(0xe0000000) #define DBC_DBC32_TYPE_SFT 29 /* - * This is a SQ producer index update. It indicates one or more - * new entries have been written to the SQ for the QPID indicated - * on the xID field. + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID + * indicated on the xID field. */ #define DBC_DBC32_TYPE_SQ (UINT32_C(0x0) << 29) #define DBC_DBC32_TYPE_LAST DBC_DBC32_TYPE_SQ } dbc_dbc32_t, *pdbc_dbc32_t; /* - * This is the 64b Push Start doorbell format. The host writes this message - * format directly to offset of each push associated WCB (write combine - * buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = offset 24, - * WCB#2 = offset 32, ... The start doorbell is followed by write combining - * data to the WCB and then that is followed by a end doorbell. + * This is the 64b Push Start doorbell format. The host writes this + * message format directly to offset of each push associated WCB (write + * combine buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = + * offset 24, WCB#2 = offset 32, ... The start doorbell is followed by + * write combining data to the WCB and then that is followed by a end + * doorbell. */ /* db_push_start (size:64b/8B) */ typedef struct db_push_start { uint64_t db; /* - * This is the push index and should be the SQ slot index, aligned - * to the start of the corresponding push WQE/packet in the Send - * Queue. + * This is the push index and should be the SQ slot index, + * aligned to the start of the corresponding push WQE/packet in + * the Send Queue. * * The index size is 16b for RoCE path and 24b for L2 and Engine * paths. Any unused bits should be written as zero. * * The index unit is 16B for L2 path. For RoCE there is a legacy - * mode with 128B unit size and a variable size mode with 16B unit - * size. For Engine mode, the unit size is 16B, where RQEs are - * always 128B - so it always increments by eight 16B slots per - * RQE. + * mode with 128B unit size and a variable size mode with 16B + * unit size. For Engine mode, the unit size is 16B, where RQEs + * are always 128B - so it always increments by eight 16B slots + * per RQE. * - * > This field is not used by the older versions of the chip, but - * > is used in this and future revisions of the chip. In older - * > versions of the chip, the driver is required to complete the - * > push doorbell operation by following it with a regular doorbell - * > which will be used to properly increment the producer index. - * > This extra doorbell write is not needed on this and future - * > versions of the chip. + * > This field is not used by the older versions of the chip, + * > but is used in this and future revisions of the chip. In + * > older versions of the chip, the driver is required to + * > complete the push doorbell operation by following it with a + * > regular doorbell which will be used to properly increment + * > the producer index. This extra doorbell write is not needed + * > on this and future versions of the chip. */ #define DB_PUSH_START_DB_INDEX_MASK UINT32_C(0xffffff) #define DB_PUSH_START_DB_INDEX_SFT 0 @@ -75324,8 +87127,8 @@ typedef struct db_push_start { #define DB_PUSH_START_DB_PI_LO_MASK UINT32_C(0xff000000) #define DB_PUSH_START_DB_PI_LO_SFT 24 /* - * This value identifies the resource that the doorbell is intended - * to notify. + * This value identifies the resource that the doorbell is + * intended to notify. * * This is the QPID. */ @@ -75343,14 +87146,14 @@ typedef struct db_push_start { #define DB_PUSH_START_DB_TYPE_SFT 60 /* * This is a SQ producer index update for Push. It indicates - * one or more new entries have been written to the SQ for the - * QPID indicated on the `xid` field. + * one or more new entries have been written to the SQ for + * the QPID indicated on the `xid` field. */ #define DB_PUSH_START_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60) /* * This is a SQ producer index update for Push. It indicates - * one or more new entries have been written to the SQ for the - * QPID indicated on the `xid` field. + * one or more new entries have been written to the SQ for + * the QPID indicated on the `xid` field. */ #define DB_PUSH_START_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60) #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END @@ -75360,32 +87163,33 @@ typedef struct db_push_start { * This is the 64b Push End doorbell format. The host writes this message * format directly to offset of each push associated WCB (write combine * buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = offset 24, - * WCB#2 = offset 32, ... The start doorbell is followed by write combining - * data to the WCB and then that is followed by a end doorbell. + * WCB#2 = offset 32, ... The start doorbell is followed by write + * combining data to the WCB and then that is followed by a end doorbell. */ /* db_push_end (size:64b/8B) */ typedef struct db_push_end { uint64_t db; /* - * This is the producer index and should be the queue index of the - * last WQE written plus the length field contained in that WQE. - * For example, if the length is 8 index units and the WQE was - * written to the first location in the queue (zero), this index - * should be written to 8. The index should point to the start of - * the first location that has not been filled in with WQE data. + * This is the producer index and should be the queue index of + * the last WQE written plus the length field contained in that + * WQE. For example, if the length is 8 index units and the WQE + * was written to the first location in the queue (zero), this + * index should be written to 8. The index should point to the + * start of the first location that has not been filled in with + * WQE data. * - * For L2 and Engine SQ, the index unit is 16B. For RoCE there are - * two modes. For Legacy fixed size RQE mode, the unit is 128B. For - * variable size RQE mode, the unit is 16B. + * For L2 and Engine SQ, the index unit is 16B. For RoCE there + * are two modes. For Legacy fixed size RQE mode, the unit is + * 128B. For variable size RQE mode, the unit is 16B. * * The index size is 24b for L2 and engine paths and 16b for the * RoCE path. Unused bits should be written as zero. * - * > In past revisions of this chip, this field was the push index - * > rather than the producer index. For this version of the chip - * > and future versions of the chip, this field must be the - * > producer index, as described above. + * > In past revisions of this chip, this field was the push + * > index rather than the producer index. For this version of + * > the chip and future versions of the chip, this field must be + * > the producer index, as described above. * > * > Also, in past revisions of this chip, an additional * > doorbell write was needed to communicate the producer index. @@ -75402,8 +87206,8 @@ typedef struct db_push_end { #define DB_PUSH_END_DB_PI_LO_MASK UINT32_C(0xff000000) #define DB_PUSH_END_DB_PI_LO_SFT 24 /* - * This value identifies the resource that the doorbell is intended - * to notify. + * This value identifies the resource that the doorbell is + * intended to notify. * * This is the QPID. */ @@ -75440,14 +87244,14 @@ typedef struct db_push_end { #define DB_PUSH_END_DB_TYPE_SFT 60 /* * This is a SQ producer index update for Push. It indicates - * one or more new entries have been written to the SQ for the - * QPID indicated on the `xid` field. + * one or more new entries have been written to the SQ for + * the QPID indicated on the `xid` field. */ #define DB_PUSH_END_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60) /* * This is a SQ producer index update for Push. It indicates - * one or more new entries have been written to the SQ for the - * QPID indicated on the `xid` field. + * one or more new entries have been written to the SQ for + * the QPID indicated on the `xid` field. */ #define DB_PUSH_END_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60) #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END @@ -75545,14 +87349,19 @@ typedef struct dbc_absolute_db_32 { * Out-of-order doorbells occur normally during dropped doorbell * recovery. */ - #define DBC_ABSOLUTE_DB_32_EPOCH UINT32_C(0x10000) + #define DBC_ABSOLUTE_DB_32_EPOCH UINT32_C(0x10000) /* - * The resize_toggle bit tells that the CQ cutoff is done. - * Every time CQ is resized by CQ cutoff, this bit toggles when it - * is done. If this bit toggles, HW can restart to use the resized - * CQ. + * The toggle value is used in CQ_ARMENA, CQ_ARMSE, CQ_ARMALL, + * SRQ_ARMENA, SRQ_ARM, and CQ_CUTOFF_ACK doorbells to qualify the + * doorbell as valid. This value should be taken from the latest NQE + * or cutoff completion. + * + * Doorbells of the above types with the wrong toggle value will be + * ignored. This is how old values in of backup doorbells are + * ignored. */ - #define DBC_ABSOLUTE_DB_32_RESIZE_TOGGLE UINT32_C(0x20000) + #define DBC_ABSOLUTE_DB_32_TOGGLE_MASK UINT32_C(0x60000) + #define DBC_ABSOLUTE_DB_32_TOGGLE_SFT 17 /* * This value identifies the resource that the doorbell is intended * to notify. @@ -75561,18 +87370,18 @@ typedef struct dbc_absolute_db_32 { * value into the full xID value by looking up the base xID for this * particular function and adding the mxID value to that base value. */ - #define DBC_ABSOLUTE_DB_32_MXID_MASK UINT32_C(0xfc0000) - #define DBC_ABSOLUTE_DB_32_MXID_SFT 18 + #define DBC_ABSOLUTE_DB_32_MXID_MASK UINT32_C(0x1f80000) + #define DBC_ABSOLUTE_DB_32_MXID_SFT 19 /* * This value defines the intended doorbell path between RoCE and * L2. */ - #define DBC_ABSOLUTE_DB_32_PATH_MASK UINT32_C(0x3000000) - #define DBC_ABSOLUTE_DB_32_PATH_SFT 24 + #define DBC_ABSOLUTE_DB_32_PATH_MASK UINT32_C(0x6000000) + #define DBC_ABSOLUTE_DB_32_PATH_SFT 25 /* This is a RoCE doorbell message. */ - #define DBC_ABSOLUTE_DB_32_PATH_ROCE (UINT32_C(0x0) << 24) + #define DBC_ABSOLUTE_DB_32_PATH_ROCE (UINT32_C(0x0) << 25) /* This is a L2 doorbell message. */ - #define DBC_ABSOLUTE_DB_32_PATH_L2 (UINT32_C(0x1) << 24) + #define DBC_ABSOLUTE_DB_32_PATH_L2 (UINT32_C(0x1) << 25) #define DBC_ABSOLUTE_DB_32_PATH_LAST DBC_ABSOLUTE_DB_32_PATH_L2 /* * This indicates it is valid doorbell update. It should be set for @@ -75581,35 +87390,29 @@ typedef struct dbc_absolute_db_32 { * in the backup doorbell location at time zero to indicate that the * backup doorbell has not yet been written. */ - #define DBC_ABSOLUTE_DB_32_VALID UINT32_C(0x4000000) - /* - * When this bit is set to one, the chip will capture debug - * information for the doorbell ring. This is intended to only be - * used on SQ doorbell rings. - */ - #define DBC_ABSOLUTE_DB_32_DEBUG_TRACE UINT32_C(0x8000000) + #define DBC_ABSOLUTE_DB_32_VALID UINT32_C(0x8000000) /* This value identifies the type of doorbell being written. */ #define DBC_ABSOLUTE_DB_32_TYPE_MASK UINT32_C(0xf0000000) #define DBC_ABSOLUTE_DB_32_TYPE_SFT 28 /* - * This is a SQ producer index update. It indicates one or more + * This is a SQ producer index update. It indicates one or more * new entries have been written to the SQ for the QPID indicated * on the xID field. This type is valid for L2, RoCE and Engine * path. */ - #define DBC_ABSOLUTE_DB_32_TYPE_SQ (UINT32_C(0x0) << 28) + #define DBC_ABSOLUTE_DB_32_TYPE_SQ (UINT32_C(0x0) << 28) /* - * This is a RQ producer index update. It indicates one or more + * This is a RQ producer index update. It indicates one or more * new entries have been written to the RQ for the QPID indicated * on the xID field. This type is valid for RoCE path. */ - #define DBC_ABSOLUTE_DB_32_TYPE_RQ (UINT32_C(0x1) << 28) + #define DBC_ABSOLUTE_DB_32_TYPE_RQ (UINT32_C(0x1) << 28) /* - * This is a SRQ producer index update. It indicates one or more + * This is a SRQ producer index update. It indicates one or more * new entries have been written to the SRQ for the SID indicated * on the xID field. This type is valid for L2 and RoCE path. */ - #define DBC_ABSOLUTE_DB_32_TYPE_SRQ (UINT32_C(0x2) << 28) + #define DBC_ABSOLUTE_DB_32_TYPE_SRQ (UINT32_C(0x2) << 28) /* * This doorbell command arms the SRQ async event. * The xID field must identify the SID that is begin armed. @@ -75619,11 +87422,11 @@ typedef struct dbc_absolute_db_32 { */ #define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARM (UINT32_C(0x3) << 28) /* - * This is a CQ consumer index update. It indicates one or more + * This is a CQ consumer index update. It indicates one or more * entries have been processed off the CQ indicated on the xID * field.This type is valid for L2, RoCE and Engine path. */ - #define DBC_ABSOLUTE_DB_32_TYPE_CQ (UINT32_C(0x4) << 28) + #define DBC_ABSOLUTE_DB_32_TYPE_CQ (UINT32_C(0x4) << 28) /* * this is a CQ consumer index update that also arms the CQ for * solicited events. This type is valid for RoCE path. @@ -75634,13 +87437,34 @@ typedef struct dbc_absolute_db_32 { * for any new CQE. This type is valid for L2, RoCE and Engine * path. */ - #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) + #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) + /* + * This is a CQ arm enable message. This message must be sent from + * the privileged driver before a new CQ_ARMSE or CQ_ARMALL message + * will be accepted from user space (non-privileged doorbell page). + * The index and epoch for this doorbell type are unused. + * + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. + */ + #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28) + /* + * This doorbell command enables the SRQ async event to be armed. + * This message must be sent from the privileged driver before a + * new SRQ_ARM message will be accepted from user space. + * The xID field must identify the SID that is being enabled for + * arm. The index and epoch for this doorbell type are unused. + * + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. + */ + #define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28) /* * This is a NQ consumer index update. It indicates one or more * entries have been processed off the NQ indicated on the xID * field. This type is valid for L2, RoCE and Engine path. */ - #define DBC_ABSOLUTE_DB_32_TYPE_NQ (UINT32_C(0xa) << 28) + #define DBC_ABSOLUTE_DB_32_TYPE_NQ (UINT32_C(0xa) << 28) /* * This is a NQ consumer index update that also arms the NQ for * any new NQE. This type is valid for L2, RoCE and Engine path. @@ -75712,20 +87536,20 @@ typedef struct dbc_relative_db_32 { #define DBC_RELATIVE_DB_32_TYPE_MASK UINT32_C(0xe0000000) #define DBC_RELATIVE_DB_32_TYPE_SFT 29 /* - * This is a SQ producer index update. It indicates one or more + * This is a SQ producer index update. It indicates one or more * new entries have been written to the SQ for the QPID indicated * on the xID field. This type is valid for L2, RoCE and Engine * path. */ #define DBC_RELATIVE_DB_32_TYPE_SQ (UINT32_C(0x0) << 29) /* - * This is a SRQ producer index update. It indicates one or more + * This is a SRQ producer index update. It indicates one or more * new entries have been written to the SRQ for the SID indicated * on the xID field. This type is valid for L2 and RoCE path. */ #define DBC_RELATIVE_DB_32_TYPE_SRQ (UINT32_C(0x1) << 29) /* - * This is a CQ consumer index update. It indicates one or more + * This is a CQ consumer index update. It indicates one or more * entries have been processed off the CQ indicated on the xID * field.This type is valid for L2, RoCE and Engine path. */ @@ -75764,7 +87588,7 @@ typedef struct dbc_relative_db_32 { /* dbc_drk (size:128b/16B) */ typedef struct dbc_drk { - uint32_t db_format_linked_last_valid; + uint32_t db_format_linked_last_valid_stride_size; /* * This indicates it is valid entry. It should be set for each * doorbell written to the chip. The bit should be cleared at time @@ -75790,11 +87614,55 @@ typedef struct dbc_drk { */ #define DBC_DRK_DB_FORMAT_B32A (UINT32_C(0x1) << 3) #define DBC_DRK_DB_FORMAT_LAST DBC_DRK_DB_FORMAT_B32A + /* + * This field controls the stride feature. The stride feature is + * more bandwidth efficient on the PCIE bus when only a small number + * of doorbells are used in each cache line. + */ + #define DBC_DRK_STRIDE_MASK UINT32_C(0x300) + #define DBC_DRK_STRIDE_SFT 8 + /* + * When stride is off, the DBR will read all the bytes in + * an application page until a NULL doorbell is found or + * the end of the 4K page is reached. + */ + #define DBC_DRK_STRIDE_OFF (UINT32_C(0x0) << 8) + /* + * When stride is 1, the DBR will read the 'size' doorbells, + * starting at the next 64B cache line boundary or until + * a NULL doorbell is found in the application page or + * the end of the 4K page is reached. + */ + #define DBC_DRK_STRIDE_SZ64 (UINT32_C(0x1) << 8) + /* + * When stride is 2, the DBR will read the 'size' doorbells, + * starting at the next 128B cache line boundary or until + * a NULL doorbell is found in the application page or + * the end of the 4K page is reached. + */ + #define DBC_DRK_STRIDE_SZ128 (UINT32_C(0x2) << 8) + #define DBC_DRK_STRIDE_LAST DBC_DRK_STRIDE_SZ128 + /* + * This value controls how many doorbells are read at each stride + * when stride mode is in use. + */ + #define DBC_DRK_SIZE_MASK UINT32_C(0xc00) + #define DBC_DRK_SIZE_SFT 10 + /* 4*8B is read at the start of each stride. */ + #define DBC_DRK_SIZE_FOUR (UINT32_C(0x0) << 10) + /* 1*8B is read at the start of each stride. */ + #define DBC_DRK_SIZE_ONE (UINT32_C(0x1) << 10) + /* 2*8B is read at the start of each stride. */ + #define DBC_DRK_SIZE_TWO (UINT32_C(0x2) << 10) + /* 3*8B is read at the start of each stride. */ + #define DBC_DRK_SIZE_THREE (UINT32_C(0x3) << 10) + #define DBC_DRK_SIZE_LAST DBC_DRK_SIZE_THREE uint32_t pi; /* * Page Index portion of DPI{VF_VALID,VFID,PI}. The pi needs to match - * the value from the context DPI for the operation to be valid or the - * pi must be zero, indicating a write from the privileged driver. + * the value from the context DPI for the operation to be valid or + * the pi must be zero, indicating a write from the privileged + * driver. * * pi in the kernel memory table is there for DBR to generate the DPI * message to the client. @@ -75811,6 +87679,322 @@ typedef struct dbc_drk { uint64_t memptr; } dbc_drk_t, *pdbc_drk_t; +/* + * This is the 64b doorbell format. The host writes this message + * format directly to byte offset 0 of the appropriate doorbell page. + */ +/* dbc_dbc_v3 (size:64b/8B) */ + +typedef struct dbc_dbc_v3 { + uint32_t index; + /* + * This value is the index being written. + * + * For SQ/RQ/SRQ, this is the producer index. It should be set to + * the queue index of the last WQE/BD written plus the number of + * index units in the WQE/BD. For example, if the number of index + * units in an SQ WQE is 8 and the WQE was written to the first + * location in the queue (zero), this index should be written to 8. + * The index should point to the start of the first location that + * has not been filled in with WQE/BD data. For SQ (both RoCE and + * L2), the index unit is 16B. For RQ/SRQ, the index unit is 1 WQE + * (RoCE) or 1 BD (L2). + * + * For CQ, this is the consumer index and should be the starting + * queue index of the last CQE processed plus the size of the last + * processed CQE in index units. The index should point to the + * start of the first CQE in the queue that has not been processed. + * The index unit is 16B. + * + * For NQ, this is the consumer index and should be the starting + * queue index of the last NQE processed plus the size of the last + * processed NQE in index units. The index should point to the + * start of the first NQE in the queue that has not been processed. + * The index unit is 16B. + */ + #define DBC_DBC_V3_INDEX_MASK UINT32_C(0xffffff) + #define DBC_DBC_V3_INDEX_SFT 0 + /* + * The epoch bit provides a frame of reference for the queue index. + * S/W will toggle this bit in the doorbell each time index range is + * wrapped. This allows the receiving HW block to more efficiently + * detect out-of-order doorbells and to ignore the older doorbells. + * Out-of-order doorbells occur normally during dropped doorbell + * recovery. + */ + #define DBC_DBC_V3_EPOCH UINT32_C(0x1000000) + /* + * The toggle value is used in CQ_ARMENA, CQ_ARMSE, CQ_ARMALL, + * SRQ_ARMENA, SRQ_ARM, and CQ_CUTOFF_ACK doorbells to qualify the + * doorbell as valid. This value should be taken from the latest + * NQE or cutoff completion. + * + * Doorbells of the above types with the wrong toggle value will + * be ignored. This is how old values in of backup doorbells + * are ignored. + */ + #define DBC_DBC_V3_TOGGLE_MASK UINT32_C(0x6000000) + #define DBC_DBC_V3_TOGGLE_SFT 25 + uint32_t type_path_xid; + /* + * This value identifies the resource that the doorbell is intended + * to notify. + * + * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For + * CQ, this is the CID. For NQ, this is the NID. + * + * Unused bits (for example bits [11:7] of the SID value) must be + * zero. + */ + #define DBC_DBC_V3_XID_MASK UINT32_C(0xfff) + #define DBC_DBC_V3_XID_SFT 0 + /* + * This value defines the intended doorbell path between RoCE and + * L2. + */ + #define DBC_DBC_V3_PATH_MASK UINT32_C(0x3000000) + #define DBC_DBC_V3_PATH_SFT 24 + /* This is a RoCE doorbell message. */ + #define DBC_DBC_V3_PATH_ROCE (UINT32_C(0x0) << 24) + /* This is a L2 doorbell message. */ + #define DBC_DBC_V3_PATH_L2 (UINT32_C(0x1) << 24) + #define DBC_DBC_V3_PATH_LAST DBC_DBC_V3_PATH_L2 + /* + * This indicates it is valid doorbell update. It should be set for + * each doorbell written to the chip and set when doorbell message is + * written to the backup doorbell location. The bit should be cleared + * in the backup doorbell location at time zero to indicate that the + * backup doorbell has not yet been written. + */ + #define DBC_DBC_V3_VALID UINT32_C(0x4000000) + /* + * When this bit is set to one, the chip will capture debug + * information for the doorbell ring. This is intended to only be + * used on SQ doorbell rings. + */ + #define DBC_DBC_V3_DEBUG_TRACE UINT32_C(0x8000000) + /* This value identifies the type of doorbell being written. */ + #define DBC_DBC_V3_TYPE_MASK UINT32_C(0xf0000000) + #define DBC_DBC_V3_TYPE_SFT 28 + /* + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID indicated + * on the xID field. This type is valid for L2 and RoCE path. + */ + #define DBC_DBC_V3_TYPE_SQ (UINT32_C(0x0) << 28) + /* + * This is a RQ producer index update. It indicates one or more + * new entries have been written to the RQ for the QPID indicated + * on the xID field. This type is valid for RoCE path. + */ + #define DBC_DBC_V3_TYPE_RQ (UINT32_C(0x1) << 28) + /* + * This is a SRQ producer index update. It indicates one or more + * new entries have been written to the SRQ for the SID indicated + * on the xID field. This type is valid for L2 and RoCE path. + */ + #define DBC_DBC_V3_TYPE_SRQ (UINT32_C(0x2) << 28) + /* + * This doorbell command arms the SRQ async event. The xID field + * must identify the SID that is begin armed. The index field is + * will set the arm threshold such that a notification will be + * generated if less than that number or SRQ entries are posted. + * + * This type is valid for RoCE path. + */ + #define DBC_DBC_V3_TYPE_SRQ_ARM (UINT32_C(0x3) << 28) + /* + * CQ doorbell is used to update the consumer index for the CQ + * for overflow detection. It should only be sent if overflow + * detection is enabled for the CQ. Keep in mind that if + * doorbells are being dropped due to PCIE ordering rules, you + * may get a false overflow detection if you are checking for CQ + * overflow. + * + * This type is valid for L2 and RoCE path. + */ + #define DBC_DBC_V3_TYPE_CQ (UINT32_C(0x4) << 28) + /* + * This is a CQ consumer index update that also arms the CQ for + * solicited events. This is for roce only not for l2. + * + * The index is used as the location of the last CQE that was + * processed by the driver. The new interrupt will be generated + * based on this location. + * + * This type is valid for RoCE path. + */ + #define DBC_DBC_V3_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28) + /* + * This is a CQ consumer index update that also arms the CQ for + * any new CQE. + * + * The index is used as the location of the last CQE that was + * processed by the driver. The new interrupt will be generated + * based on this location. + * + * This type is valid for L2 and RoCE path. + */ + #define DBC_DBC_V3_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28) + /* + * This is a CQ arm enable message. This message must be sent + * from the privileged driver before a new CQ_ARMSE or CQ_ARMALL + * message will be accepted from user space (non-privileged + * doorbell page). The index and epoch for this doorbell type are + * unused. + * + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. + */ + #define DBC_DBC_V3_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28) + /* + * This doorbell command enables the SRQ async event to be armed. + * This message must be sent from the privileged driver before + * a new SRQ_ARM message will be accepted from user space. The + * xID field must identify the SID that is being enabled for arm. + * The index and epoch for this doorbell type are unused. + * + * This doorbell can only be sent from the privileged (first) + * doorbell page of a function. + */ + #define DBC_DBC_V3_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28) + /* + * This doorbell type is used to acknowledge a cutoff completion + * in the CQ. The index and epoch for this doorbell type are + * unused. This doorbell is sent when the cutoff completion has + * been processed and the old CQ in a CQ resize operation is no + * longer needed. + * + * The index and epoch must be valid for this doorbell if + * overflow checking is enabled for the CQ. + */ + #define DBC_DBC_V3_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28) + /* + * This is a NQ consumer index update. It indicates one or more + * entries have been processed off the NQ indicated on the xID + * field. It will also mask the NQ for any new NQE. This type is + * valid for L2 and RoCE path. + * + * Thor is broken in that it doesn't mask a legacy INTA interrupt + * when used at the start of an ISR, as it is supposed to be. + * + * type=NQ masks the current interrupt. When the iSR starts, it + * writes a type=NQ with the current consumer index. For legacy + * PCI interrupts, this needs to mask the interrupt so the legacy + * interrupt is deasserted. Then the driver does some work and + * writes some more type=NQ. Finally the driver stops the ISR and + * does a type=NQ_ARM to get another interrupt (when needed). The + * only reason to use type=NQ_MASK is to back out of the armed + * state. In that request, the index update is not required. + */ + #define DBC_DBC_V3_TYPE_NQ (UINT32_C(0xa) << 28) + /* + * This is a NQ consumer index update that also arms the NQ for + * any new NQE. + * + * This type is valid for L2 and RoCE path. + */ + #define DBC_DBC_V3_TYPE_NQ_ARM (UINT32_C(0xb) << 28) + /* + * This doorbell will assign a new NQ to a CQ. This is handy if + * the user wants to change which interrupt handler is going to + * process a particular CQ. This doorbell must be sent from the + * privileged driver. + * + * The xID must be the CID for the CQ that needs to be changed. + * The index value is the NQID of the new NQ that will be used + * for future notifications. epoch and toggle are ignored for + * this doorbell type. + * + * The CQ will disarm notifications and generate a NQE to the old + * NQ with the nq_reassign type value. The chip will guarantee + * that no notification will be sent to the old NQ after the + * nq_reassign NQE has been sent. + * + * This type is valid for L2 and RoCE CQs. + */ + #define DBC_DBC_V3_TYPE_CQ_REASSIGN (UINT32_C(0xc) << 28) + /* + * This masks the NQ for any new NQE. This will NOT update the NQ + * consumer index. + * + * This type is valid for L2 and RoCE path. + */ + #define DBC_DBC_V3_TYPE_NQ_MASK (UINT32_C(0xe) << 28) + /* + * All other fields should be zero for NULL doorbell. + * + * For doorbell recovery, NULL doorbell type in the Application + * table indicates that it is the last QP entry for the function. + * This type is valid for L2 and RoCE path. + */ + #define DBC_DBC_V3_TYPE_NULL (UINT32_C(0xf) << 28) + #define DBC_DBC_V3_TYPE_LAST DBC_DBC_V3_TYPE_NULL +} dbc_dbc_v3_t, *pdbc_dbc_v3_t; + +/* + * This is the RoCE Express Doorbell format. The host writes this + * message format directly to offset 0x40 of the appropriate doorbell + * page. Express doorbells are used when the chip will be owning the + * SQ, RQ, and SRQ as well as the producer indexes for each queue. This + * provides a simple fastpath programming model. + * + * Express doorbell must be received by the chip as a single TLP + * message. + */ +/* dbc_xp (size:512b/64B) */ + +typedef struct dbc_xp { + uint32_t reserved; + uint32_t type_xid; + /* + * This value identifies the resource that the doorbell is intended + * to notify. + * + * For SQ and RQ, this is the QPID. For SRQ, this is the SID. For + * CQ, this is the CID. For NQ, this is the NID. + * + * Unused bits (for example bits [11:7] of the SID value) must be + * zero. + */ + #define DBC_XP_XID_MASK UINT32_C(0xfff) + #define DBC_XP_XID_SFT 0 + /* + * When this bit is set to one, the chip will capture debug + * information for the doorbell ring. This is intended to only be + * used on SQ doorbell rings. + */ + #define DBC_XP_DEBUG_TRACE UINT32_C(0x1000000) + /* This value identifies the type of doorbell being written. */ + #define DBC_XP_TYPE_MASK UINT32_C(0xf0000000) + #define DBC_XP_TYPE_SFT 28 + /* + * This is a SQ producer index update. It indicates one or more + * new entries have been written to the SQ for the QPID indicated + * on the xID field. This type is valid for L2, RoCE and Engine + * path. + */ + #define DBC_XP_TYPE_SQ (UINT32_C(0x0) << 28) + /* + * This is a RQ producer index update. It indicates one or more + * new entries have been written to the RQ for the QPID indicated + * on the xID field. This type is valid for RoCE path. + */ + #define DBC_XP_TYPE_RQ (UINT32_C(0x1) << 28) + /* + * This is a SRQ producer index update. It indicates one or more + * new entries have been written to the SRQ for the SID indicated + * on the xID field. This type is valid for L2 and RoCE path. + */ + #define DBC_XP_TYPE_SRQ (UINT32_C(0x2) << 28) + #define DBC_XP_TYPE_LAST DBC_XP_TYPE_SRQ + /* + * This field hold one express WQE. The WQE must be appropriate for + * the queue selected by the type field. + */ + uint32_t wqe[14]; +} dbc_xp_t, *pdbc_xp_t; + /* * This is a firmware status register that indicates the software status * exposed by the firmware to the host. @@ -75825,9 +88009,10 @@ typedef struct fw_status_reg { * These bits indicate the status as being reported by the firmware. * * The value should be interpreted as follows: - * A value below 0x8000 is an indication that the firmware is still in the - * process of starting up and is not ready. The host driver should - * continue waiting with a timeout for firmware status to be ready. + * A value below 0x8000 is an indication that the firmware is still + * in the process of starting up and is not ready. The host driver + * should continue waiting with a timeout for firmware status to be + * ready. * > 0x0000 to 0x00FF : SBL state information * > 0x0200 to 0x02FF : SBI state information * > 0x0400 to 0x04FF : SRT state information @@ -75835,14 +88020,15 @@ typedef struct fw_status_reg { * > 0x0800 to 0x08FF : External Firmware state information * > 0x0A00 to 0x0FFF : Reserved for future fw functionality * - * A value of 0x8000 indicates firmware is ready and healthy. The host - * driver can start initiating HWRM commands to the firmware. + * A value of 0x8000 indicates firmware is ready and healthy. The + * host driver can start initiating HWRM commands to the firmware. * - * A value over 0x8000 is an indication that the firmware has detected - * a fatal error, this error could be in one of the hardware block or - * in a software module. The lower 8 bits indicate a block/module - * specific error and the upper 8 bits identify the hardware block - * or firmware module that was the source of the error. + * A value over 0x8000 is an indication that the firmware has + * detected a fatal error, this error could be in one of the hardware + * block or in a software module. The lower 8 bits indicate a + * block/module specific error and the upper 8 bits identify the + * hardware block or firmware module that was the source of the + * error. * > 0x81XX - 0xBFXX : 63 ASIC blocks * > 0xC0XX to 0xFDXX : 62 Firmware modules * > 0xFE00 to 0xFEFF : External firmware module @@ -75868,10 +88054,10 @@ typedef struct fw_status_reg { * recoverable with a full reset. * * This bit should be used by host software and deployment models - * that support error recovery by resetting the controller. A recovery - * should be attempted from a fatal error condition only if this bit - * is set. This bit is meaningful only when the code field is greater - * than 0x8000 (32768 decimal). + * that support error recovery by resetting the controller. A + * recovery should be attempted from a fatal error condition only if + * this bit is set. This bit is meaningful only when the code field + * is greater than 0x8000 (32768 decimal). */ #define FW_STATUS_REG_RECOVERABLE UINT32_C(0x20000) /* @@ -75879,51 +88065,52 @@ typedef struct fw_status_reg { * currently recording a crash dump. * * This bit provides a hint to the host driver if the firmware is - * currently recording a crash dump. Host driers should avoid resetting - * the controller when a crash dump is in progress if possible. This - * bit is meaningful only when the code field is greater than - * 0x8000 (32768 decimal). + * currently recording a crash dump. Host driers should avoid + * resetting the controller when a crash dump is in progress if + * possible. This bit is meaningful only when the code field is + * greater than 0x8000 (32768 decimal). */ #define FW_STATUS_REG_CRASHDUMP_ONGOING UINT32_C(0x40000) /* - * Crash dump is available. If set indicates that a firmware crash dump - * was recorded before and is now available. + * Crash dump is available. If set indicates that a firmware crash + * dump was recorded before and is now available. * - * This bit provides indication to the host driver that the firmware has - * completed a crash dump. This bit is meaningful only when the code - * field is greater than 0x8000 (32768 decimal). + * This bit provides indication to the host driver that the firmware + * has completed a crash dump. This bit is meaningful only when the + * code field is greater than 0x8000 (32768 decimal). */ #define FW_STATUS_REG_CRASHDUMP_COMPLETE UINT32_C(0x80000) /* - * This bit is used to indicate device state when it enters the shutdown mode - * and stopped the communication with the host. The host should initiate the - * reload of firmware image or initiate the reset to bring the device to the - * normal operational state and re-establish the communication. + * This bit is used to indicate device state when it enters the + * shutdown mode and stopped the communication with the host. The + * host should initiate the reload of firmware image or initiate the + * reset to bring the device to the normal operational state and + * re-establish the communication. * - * This bit is meaningful only when the code field is greater than 0x8000 - * (32768 decimal). + * This bit is meaningful only when the code field is greater than + * 0x8000 (32768 decimal). */ #define FW_STATUS_REG_SHUTDOWN UINT32_C(0x100000) /* * This bit will be set to 1 by the FW when FW crashed without master * function. * - * This bit is controller specific, not all products will support this bit. - * This bit is valid only when the code field is greater than 0x8000 - * (32768 decimal). + * This bit is controller specific, not all products will support + * this bit. This bit is valid only when the code field is greater + * than 0x8000 (32768 decimal). */ #define FW_STATUS_REG_CRASHED_NO_MASTER UINT32_C(0x200000) /* - * The firmware sets this bit to 1 when the firmware has taken an exception - * and expects to initiate error recovery. + * The firmware sets this bit to 1 when the firmware has taken an + * exception and expects to initiate error recovery. * * This bit is valid only when the code field is greater than 0x8000 * (32768 decimal). */ #define FW_STATUS_REG_RECOVERING UINT32_C(0x400000) /* - * The SBL sets this bit to indicate whether manu_debug pin is detected high - * or low. + * The SBL sets this bit to indicate whether manu_debug pin is + * detected high or low. */ #define FW_STATUS_REG_MANU_DEBUG_STATUS UINT32_C(0x800000) } fw_status_reg_t, *pfw_status_reg_t; @@ -76067,48 +88254,14 @@ typedef struct hwrm_selftest_qlist_output { uint16_t test_timeout; uint8_t unused_1[2]; /* - * This field represents the name of the NVM test (ASCII chars + * This field represents array of 8 test name strings (ASCII chars * with NULL at the end). */ - char test0_name[32]; - /* - * This field represents the name of the link test (ASCII chars - * with NULL at the end). - */ - char test1_name[32]; - /* - * This field represents the name of the register test (ASCII chars - * with NULL at the end). - */ - char test2_name[32]; - /* - * This field represents the name of the memory test (ASCII chars - * with NULL at the end). - */ - char test3_name[32]; - /* - * This field represents the name of the PCIe serdes test (ASCII chars - * with NULL at the end). - */ - char test4_name[32]; - /* - * This field represents the name of the Ethernet serdes test (ASCII chars - * with NULL at the end). - */ - char test5_name[32]; - /* - * This field represents the name of some future test (ASCII chars - * with NULL at the end). - */ - char test6_name[32]; - /* - * This field represents the name of some future test (ASCII chars - * with NULL at the end). - */ - char test7_name[32]; + char test_name[8][32]; /* * The lowest available target BER that is supported by FW eyescope. - * A Value of 3 indicates that FW supports 1e-8, 1e-9, 1e-10, and 1e-11. + * A Value of 3 indicates that FW supports 1e-8, 1e-9, 1e-10, and + * 1e-11. */ uint8_t eyescope_target_BER_support; /* Eyescope supports a target BER of 1e-8 */ @@ -76125,9 +88278,9 @@ typedef struct hwrm_selftest_qlist_output { uint8_t unused_2[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76212,28 +88365,47 @@ typedef struct hwrm_selftest_exec_output { /* A request was made to run the Ethernet serdes test. */ #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20) /* - * If a test was requested to be run as seen in the requested_tests field, - * this bit indicates whether the test was successful(1) or failed(0). + * If a test was requested to be run as seen in the requested_tests + * field, this bit indicates whether the test was successful(1) or + * failed(0). */ uint8_t test_success; - /* If requested, a value of 1 indicates the NVM test completed successfully. */ + /* + * If requested, a value of 1 indicates the NVM test completed + * successfully. + */ #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_NVM_TEST UINT32_C(0x1) - /* If requested, a value of 1 indicates the link test completed successfully. */ + /* + * If requested, a value of 1 indicates the link test completed + * successfully. + */ #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_LINK_TEST UINT32_C(0x2) - /* If requested, a value of 1 indicates the register test completed successfully. */ + /* + * If requested, a value of 1 indicates the register test completed + * successfully. + */ #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_REGISTER_TEST UINT32_C(0x4) - /* If requested, a value of 1 indicates the memory test completed successfully. */ + /* + * If requested, a value of 1 indicates the memory test completed + * successfully. + */ #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_MEMORY_TEST UINT32_C(0x8) - /* If requested, a value of 1 indicates the PCIe serdes test completed successfully. */ + /* + * If requested, a value of 1 indicates the PCIe serdes test + * completed successfully. + */ #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PCIE_SERDES_TEST UINT32_C(0x10) - /* If requested, a value of 1 indicates the Ethernet serdes test completed successfully. */ + /* + * If requested, a value of 1 indicates the Ethernet serdes test + * completed successfully. + */ #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_ETHERNET_SERDES_TEST UINT32_C(0x20) uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76291,9 +88463,9 @@ typedef struct hwrm_selftest_irq_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76345,12 +88517,13 @@ typedef struct hwrm_selftest_retrieve_serdes_data_input { uint32_t resp_data_offset; /* * Size of the buffer pointed to by resp_data_addr. The firmware may - * use this entire buffer or less than the entire buffer, but never more. + * use this entire buffer or less than the entire buffer, but never + * more. */ uint16_t data_len; /* - * This field allows this command to request the individual serdes tests - * to be run using this command. + * This field allows this command to request the individual serdes + * tests to be run using this command. */ uint8_t flags; /* Unused. */ @@ -76365,7 +88538,8 @@ typedef struct hwrm_selftest_retrieve_serdes_data_input { uint8_t options; /* * This field represents the PCIE lane number on which tools wants to - * retrieve eye plot. This field is valid only when ‘pcie_serdes_test’ flag is set. + * retrieve eye plot. This field is valid only when 'pcie_serdes_test' + * flag is set. * Valid values from 0 to 16. */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_MASK UINT32_C(0xf) @@ -76385,8 +88559,9 @@ typedef struct hwrm_selftest_retrieve_serdes_data_input { */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LEFT_TOP (UINT32_C(0x0) << 5) /* - * Value 1 indicates right/bottom projection in horizontal/vertical - * This value is valid only when eye_projection flag was set. + * Value 1 indicates right/bottom projection in + * horizontal/vertical. This value is valid only when + * eye_projection flag was set. */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM (UINT32_C(0x1) << 5) #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM @@ -76416,20 +88591,24 @@ typedef struct hwrm_selftest_retrieve_serdes_data_input { uint8_t action; /* * Value 0 indicates that collection of the eyescope should be - * returned synchronously in the output. This only applies to + * returned synchronously in the output. This only applies to * a targetBER of 1e-8. */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_SYNCHRONOUS UINT32_C(0x0) - /* Value 1 indicates to the firmware to start the collection of the eyescope. */ + /* + * Value 1 indicates to the firmware to start the collection of the + * eyescope. + */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_START UINT32_C(0x1) /* - * Value 2 indicates to the firmware to respond with a progress percentage - * of the current eyescope collection from 0.0 to 100.0. + * Value 2 indicates to the firmware to respond with a progress + * percentage of the current eyescope collection from 0.0 to 100.0. */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_PROGRESS UINT32_C(0x2) /* - * Value 3 indicates to stop the eyescope. if the progress percentage - * is 100.0, the data will be DMAed back to resp_data_addr. + * Value 3 indicates to stop the eyescope. if the progress + * percentage is 100.0, the data will be DMAed back to + * resp_data_addr. */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP UINT32_C(0x3) #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_LAST HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP @@ -76458,16 +88637,17 @@ typedef struct hwrm_selftest_retrieve_serdes_data_output { */ uint16_t copied_data_len; /* - * Percentage of completion of collection of BER values from the current - * eyescope operation in tenths of a percentage. 0 (0.0) to 1000 (100.0) + * Percentage of completion of collection of BER values from the + * current eyescope operation in tenths of a percentage. 0 (0.0) to + * 1000 (100.0). */ uint16_t progress_percent; /* Timeout in seconds for timeout of an individual BER point. */ uint16_t timeout; uint8_t flags; /* - * This value indicates the structure of data returned by the firmware - * when DMA'ed to resp_data_addr + * This value indicates the structure of data returned by the + * firmware when DMA'ed to resp_data_addr. */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE UINT32_C(0x1) /* @@ -76477,7 +88657,7 @@ typedef struct hwrm_selftest_retrieve_serdes_data_output { #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_TOTAL UINT32_C(0x0) /* * Value 1 indicates that bit count is a power of - * 2 that bit_count is normalized to. A Value of 42 indicates + * 2 that bit_count is normalized to. A Value of 42 indicates * that BER = error_count / 2^42 */ #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2 UINT32_C(0x1) @@ -76488,15 +88668,16 @@ typedef struct hwrm_selftest_retrieve_serdes_data_output { uint8_t unused_0; /* * Size of header prepended to the bit_count and error_count array. - * Use this value to skip forward to the bit_count and error_count array. + * Use this value to skip forward to the bit_count and error_count + * array. */ uint16_t hdr_size; uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76560,9 +88741,9 @@ typedef struct hwrm_mfg_fru_write_control_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76639,9 +88820,9 @@ typedef struct hwrm_mfg_timers_query_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76729,9 +88910,9 @@ typedef struct hwrm_mfg_otp_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76824,9 +89005,9 @@ typedef struct hwrm_mfg_otp_qcfg_output { uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76908,9 +89089,9 @@ typedef struct hwrm_mfg_hdma_test_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -76984,9 +89165,9 @@ typedef struct hwrm_mfg_fru_eeprom_write_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -77064,9 +89245,9 @@ typedef struct hwrm_mfg_fru_eeprom_read_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -77189,7 +89370,7 @@ typedef struct hwrm_mfg_soc_image_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -77285,7 +89466,7 @@ typedef struct hwrm_mfg_soc_qstatus_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -77294,14 +89475,14 @@ typedef struct hwrm_mfg_soc_qstatus_output { uint8_t valid; } hwrm_mfg_soc_qstatus_output_t, *phwrm_mfg_soc_qstatus_output_t; -/******************************* - * hwrm_mfg_param_seeprom_sync * - *******************************/ +/***************************************** + * hwrm_mfg_param_critical_data_finalize * + *****************************************/ -/* hwrm_mfg_param_seeprom_sync_input (size:640b/80B) */ +/* hwrm_mfg_param_critical_data_finalize_input (size:192b/24B) */ -typedef struct hwrm_mfg_param_seeprom_sync_input { +typedef struct hwrm_mfg_param_critical_data_finalize_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77330,34 +89511,19 @@ typedef struct hwrm_mfg_param_seeprom_sync_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint16_t flags; /* - * The host (DMA) buffer physical addr for the firmware to read from. - * This buffer is populated with the parameter binary bits which is - * going to be programmed into the seeprom memory. + * Set to 1 if you wish to unlock and erase the region + * before finalizing the data. */ - uint64_t data_addr; - /* Size of the buffer pointed to by data_addr. */ - uint16_t data_len; - /* The offset within the SEEPROM to start programming. */ - uint16_t offset; - uint32_t flags; - /* - * This bit must be '1' to sync the parameters available in factory - * config to seeprom binary before writing to seeprom - */ - #define HWRM_MFG_PARAM_SEEPROM_SYNC_INPUT_FLAGS_FAC_CFG_SYNC UINT32_C(0x1) - /* - * This bit must be '1' for the seeprom data to be written to - * a specified address with out any change in the binary - */ - #define HWRM_MFG_PARAM_SEEPROM_SYNC_INPUT_FLAGS_WRITE_BINARY_ONLY UINT32_C(0x80000000) - /* Reserved for future use. */ - uint8_t reserved[48]; -} hwrm_mfg_param_seeprom_sync_input_t, *phwrm_mfg_param_seeprom_sync_input_t; + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_INPUT_FLAGS_FORCE UINT32_C(0x1) + uint16_t unused_0; + uint32_t unused_1; +} hwrm_mfg_param_critical_data_finalize_input_t, *phwrm_mfg_param_critical_data_finalize_input_t; -/* hwrm_mfg_param_seeprom_sync_output (size:128b/16B) */ +/* hwrm_mfg_param_critical_data_finalize_output (size:128b/16B) */ -typedef struct hwrm_mfg_param_seeprom_sync_output { +typedef struct hwrm_mfg_param_critical_data_finalize_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77366,28 +89532,36 @@ typedef struct hwrm_mfg_param_seeprom_sync_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Total length of data written to the seeprom memory. */ - uint16_t total_data_len; - uint16_t unused_0; - uint8_t unused_1[3]; + /* Total length of data finalized. */ + uint32_t total_data_len; + uint16_t error_status; + /* Critical data region was already locked */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_ALREADY_LOCKED UINT32_C(0x1) + /* Flash region was not entirely empty */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_NOT_EMPTY UINT32_C(0x2) + /* FACT_CFG was missing for write to critical cfg */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_FACT_CFG UINT32_C(0x4) + /* VPD was missing for write to critical cfg */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_VPD UINT32_C(0x8) + uint8_t unused_1; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} hwrm_mfg_param_seeprom_sync_output_t, *phwrm_mfg_param_seeprom_sync_output_t; +} hwrm_mfg_param_critical_data_finalize_output_t, *phwrm_mfg_param_critical_data_finalize_output_t; -/******************************* - * hwrm_mfg_param_seeprom_read * - *******************************/ +/************************************* + * hwrm_mfg_param_critical_data_read * + *************************************/ -/* hwrm_mfg_param_seeprom_read_input (size:256b/32B) */ +/* hwrm_mfg_param_critical_data_read_input (size:256b/32B) */ -typedef struct hwrm_mfg_param_seeprom_read_input { +typedef struct hwrm_mfg_param_critical_data_read_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77418,8 +89592,8 @@ typedef struct hwrm_mfg_param_seeprom_read_input { uint64_t resp_addr; /* * The host (DMA) buffer physical addr for the firmware to write to. - * This buffer is populated with the parameter binary bits which is - * going to be read from the seeprom memory. + * This buffer is populated with data read from the + * critical data storage location. */ uint64_t data_addr; /* @@ -77427,15 +89601,14 @@ typedef struct hwrm_mfg_param_seeprom_read_input { * use this entire buffer or less than the entire buffer, but never * more. */ - uint16_t data_len; - /* The offset within the SEEPROM to start reading. */ - uint16_t offset; - uint8_t unused[4]; -} hwrm_mfg_param_seeprom_read_input_t, *phwrm_mfg_param_seeprom_read_input_t; + uint32_t data_len; + /* The offset within the critical data to start reading. */ + uint32_t offset; +} hwrm_mfg_param_critical_data_read_input_t, *phwrm_mfg_param_critical_data_read_input_t; -/* hwrm_mfg_param_seeprom_read_output (size:128b/16B) */ +/* hwrm_mfg_param_critical_data_read_output (size:128b/16B) */ -typedef struct hwrm_mfg_param_seeprom_read_output { +typedef struct hwrm_mfg_param_critical_data_read_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77445,27 +89618,27 @@ typedef struct hwrm_mfg_param_seeprom_read_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* Total length of data written to the host memory. */ - uint16_t total_data_len; - uint16_t unused_0[2]; + uint32_t total_data_len; + uint16_t unused_0; + uint8_t unused_1; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; - uint8_t unused_1; -} hwrm_mfg_param_seeprom_read_output_t, *phwrm_mfg_param_seeprom_read_output_t; +} hwrm_mfg_param_critical_data_read_output_t, *phwrm_mfg_param_critical_data_read_output_t; -/********************************* - * hwrm_mfg_param_seeprom_health * - *********************************/ +/*************************************** + * hwrm_mfg_param_critical_data_health * + ***************************************/ -/* hwrm_mfg_param_seeprom_health_input (size:192b/24B) */ +/* hwrm_mfg_param_critical_data_health_input (size:192b/24B) */ -typedef struct hwrm_mfg_param_seeprom_health_input { +typedef struct hwrm_mfg_param_critical_data_health_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -77495,11 +89668,11 @@ typedef struct hwrm_mfg_param_seeprom_health_input { */ uint64_t resp_addr; uint64_t unused_0; -} hwrm_mfg_param_seeprom_health_input_t, *phwrm_mfg_param_seeprom_health_input_t; +} hwrm_mfg_param_critical_data_health_input_t, *phwrm_mfg_param_critical_data_health_input_t; -/* hwrm_mfg_param_seeprom_health_output (size:128b/16B) */ +/* hwrm_mfg_param_critical_data_health_output (size:128b/16B) */ -typedef struct hwrm_mfg_param_seeprom_health_output { +typedef struct hwrm_mfg_param_critical_data_health_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -77509,37 +89682,25 @@ typedef struct hwrm_mfg_param_seeprom_health_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; uint32_t health_status; - /* No response from the device */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_RESPONSE UINT32_C(0x1) + /* region entirely empty */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_IS_EMPTY UINT32_C(0x1) /* Data checksum fail */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_CHECKSUM_FAIL UINT32_C(0x2) - /* Mac address not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_MAC_ADDRESS UINT32_C(0x4) - /* Part number not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_PART_NUMBER UINT32_C(0x8) - /* Serial number not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_SR_NUMBER UINT32_C(0x10) - /* Package description not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_STATUS_NO_PKG_DESCRIPTION UINT32_C(0x20) - uint16_t health_code; - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_SUCCESS UINT32_C(0x0) - /* No response from the device */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_NO_RESPONSE UINT32_C(0x1) - /* Data checksum fail */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_CHECKSUM_FAIL UINT32_C(0x2) - /* Mac address not populated */ - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_NO_MAC_ADDRESS UINT32_C(0x3) - #define HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_LAST HWRM_MFG_PARAM_SEEPROM_HEALTH_OUTPUT_HEALTH_CODE_NO_MAC_ADDRESS + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_CHECKSUM_FAIL UINT32_C(0x2) + /* Malformed data (header/footer) */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_MALFORMED_DATA UINT32_C(0x4) + /* Critical data not locked */ + #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_NOT_LOCKED UINT32_C(0x8) + uint16_t unused_1; + uint8_t unused_2; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; - uint8_t unused_1; -} hwrm_mfg_param_seeprom_health_output_t, *phwrm_mfg_param_seeprom_health_output_t; +} hwrm_mfg_param_critical_data_health_output_t, *phwrm_mfg_param_critical_data_health_output_t; /***************************** * hwrm_mfg_prvsn_export_csr * @@ -77578,16 +89739,24 @@ typedef struct hwrm_mfg_prvsn_export_csr_input { */ uint64_t resp_addr; /* - * 64-bit Host destination address. This is the host address where + * 64-bit Host destination address. This is the host address where * data will be written. */ uint64_t host_dest_addr; - /* Provisioning slot number. 0-indexed. */ + /* Provisioning slot number. 0-indexed. */ uint8_t slot; uint8_t unused_0; /* Size in bytes of the available host buffer. */ uint16_t host_buf_len; - uint32_t unused_1; + uint8_t flags; + /* + * This bit is only used when external secure SoC is used for + * secure boot. If this bit is set, export a certificate signing + * request (CSR) from the security SoC non-volatile storage on + * the device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CSR_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1) + uint8_t unused_1[3]; } hwrm_mfg_prvsn_export_csr_input_t, *phwrm_mfg_prvsn_export_csr_input_t; /* hwrm_mfg_prvsn_export_csr_output (size:128b/16B) */ @@ -77601,7 +89770,7 @@ typedef struct hwrm_mfg_prvsn_export_csr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Provisioning slot number. 0-indexed. */ + /* Provisioning slot number. 0-indexed. */ uint8_t slot; uint8_t unused_0; /* Size in bytes of the exported CSR. */ @@ -77609,7 +89778,7 @@ typedef struct hwrm_mfg_prvsn_export_csr_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -77673,16 +89842,24 @@ typedef struct hwrm_mfg_prvsn_import_cert_input { */ uint64_t resp_addr; /* - * 64-bit Host source address. This is the host address where + * 64-bit Host source address. This is the host address where * source data is located. */ uint64_t host_src_addr; - /* Provisioning slot number. 0-indexed. */ + /* Provisioning slot number. 0-indexed. */ uint8_t slot; uint8_t unused_0; /* Size in bytes of the certificate chain. */ uint16_t cert_len; - uint32_t unused_1; + uint8_t flags; + /* + * This bit is only used when external secure SoC is used for + * secure boot. If this bit is set, then import a HSM-signed + * certificate chain to security SoC non-volatile storage on + * the device. + */ + #define HWRM_MFG_PRVSN_IMPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1) + uint8_t unused_1[3]; } hwrm_mfg_prvsn_import_cert_input_t, *phwrm_mfg_prvsn_import_cert_input_t; /* hwrm_mfg_prvsn_import_cert_output (size:128b/16B) */ @@ -77696,7 +89873,7 @@ typedef struct hwrm_mfg_prvsn_import_cert_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Provisioning slot number. 0-indexed. */ + /* Provisioning slot number. 0-indexed. */ uint8_t slot; /* Provisioned state */ uint8_t state; @@ -77708,7 +89885,7 @@ typedef struct hwrm_mfg_prvsn_import_cert_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -77793,7 +89970,7 @@ typedef struct hwrm_mfg_prvsn_get_state_output { /* Flag indicating if provision get state is valid. */ uint8_t get_state_valid; /* - * Provision get state is invalid. The attestation agent has not + * Provision get state is invalid. The attestation agent has not * yet initialized and not completed verification of the * provisioned certificate chain. * The slot_status field is undetermined. @@ -77803,7 +89980,7 @@ typedef struct hwrm_mfg_prvsn_get_state_output { #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_SPDM UINT32_C(0x1) /* Provision get state is valid for Cerberus. */ #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_CERBERUS UINT32_C(0x2) - /* Provision get state is valid. There is no attestation agent. */ + /* Provision get state is valid. There is no attestation agent. */ #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE UINT32_C(0xff) #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_LAST HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE /* @@ -77827,7 +90004,7 @@ typedef struct hwrm_mfg_prvsn_get_state_output { uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -77836,6 +90013,118 @@ typedef struct hwrm_mfg_prvsn_get_state_output { uint8_t valid; } hwrm_mfg_prvsn_get_state_output_t, *phwrm_mfg_prvsn_get_state_output_t; +/****************************** + * hwrm_mfg_prvsn_export_cert * + ******************************/ + + +/* hwrm_mfg_prvsn_export_cert_input (size:256b/32B) */ + +typedef struct hwrm_mfg_prvsn_export_cert_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * 64-bit Host destination address. This is the host address where + * data will be written. + */ + uint64_t host_dest_addr; + /* Provisioning slot number. 0-indexed. */ + uint8_t slot; + uint8_t unused_0; + /* Size in bytes of the available host buffer. */ + uint16_t host_buf_len; + uint8_t flags; + /* + * This bit is only used when external secure SoC is used + * for secure boot. If this bit is set, then export the + * provisioned certificate from the security SoC non-volatile + * storage device. + */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1) + uint8_t unused_1[3]; +} hwrm_mfg_prvsn_export_cert_input_t, *phwrm_mfg_prvsn_export_cert_input_t; + +/* hwrm_mfg_prvsn_export_cert_output (size:128b/16B) */ + +typedef struct hwrm_mfg_prvsn_export_cert_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Provisioning slot number. 0-indexed. */ + uint8_t slot; + uint8_t unused_0; + /* + * Size in bytes of the exported certificate chain. If there are no + * certificates provisioned for the specified slot, the device will + * return a successful response with cert_len equal to 0. + */ + uint16_t cert_len; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} hwrm_mfg_prvsn_export_cert_output_t, *phwrm_mfg_prvsn_export_cert_output_t; + +/* hwrm_mfg_prvsn_export_cert_cmd_err (size:64b/8B) */ + +typedef struct hwrm_mfg_prvsn_export_cert_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error. */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* Slot invalid */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1) + /* + * The provisioned certificates are invalid due to device ID change, + * NVRAM corruption or another reason. + */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_CERT_INVALID UINT32_C(0x2) + /* Host provided buffer is too small */ + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x3) + #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_LAST HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_BUFFER_LENGTH + uint8_t unused_0[7]; +} hwrm_mfg_prvsn_export_cert_cmd_err_t, *phwrm_mfg_prvsn_export_cert_cmd_err_t; + /******************************** * hwrm_mfg_get_nvm_measurement * ********************************/ @@ -77888,7 +90177,7 @@ typedef struct hwrm_mfg_get_nvm_measurement_output { /* Flag indicating if the hash returned is valid. */ uint8_t hash_state; /* - * Measurement hash is invalid. There was an error + * Measurement hash is invalid. There was an error * calculating the hash or firmware does not support NVM * measurement. */ @@ -77912,7 +90201,7 @@ typedef struct hwrm_mfg_get_nvm_measurement_output { uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -78003,7 +90292,7 @@ typedef struct hwrm_mfg_psoc_qstatus_output { uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal * processor, the order of writes has to be such that this field is @@ -78102,9 +90391,9 @@ typedef struct hwrm_mfg_selftest_qlist_output { uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -78254,9 +90543,9 @@ typedef struct hwrm_mfg_selftest_exec_output { uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -78298,8 +90587,29 @@ typedef struct hwrm_oem_cmd_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t IANA; - uint32_t unused_0; + /* + * The organization owning the message format. Set this field + * to 0x14e4 when used for Broadcom internal use when + * the naming authority is set to PCI_SIG. + */ + uint32_t oem_id; + /* The naming authority used for setting the oem_id. */ + uint8_t naming_authority; + /* Invalid naming authority */ + #define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_INVALID UINT32_C(0x0) + /* PCI_SIG naming authority numbering is used */ + #define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG UINT32_C(0x1) + #define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_LAST HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG + /* The message family within the organization. */ + uint8_t message_family; + /* Invalid message family */ + #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_INVALID UINT32_C(0x0) + /* This message is targeted for Truflow */ + #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW UINT32_C(0x1) + /* This message is targeted for RoCE */ + #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_ROCE UINT32_C(0x2) + #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_LAST HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_ROCE + uint16_t unused; /* This field contains the vendor specific command data. */ uint32_t oem_data[26]; } hwrm_oem_cmd_input_t, *phwrm_oem_cmd_input_t; @@ -78315,16 +90625,21 @@ typedef struct hwrm_oem_cmd_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t IANA; - uint32_t unused_0; + /* The organization owning the message format. */ + uint32_t oem_id; + /* The naming authority used for setting the oem_id. */ + uint8_t naming_authority; + /* The message family within the organization. */ + uint8_t message_family; + uint16_t unused; /* This field contains the vendor specific response data. */ uint32_t oem_data[18]; uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; @@ -78383,4 +90698,818 @@ typedef struct hwrm_sv_output { uint32_t opaque[32]; } hwrm_sv_output_t, *phwrm_sv_output_t; +/******************* + * hwrm_udcc_qcaps * + *******************/ + + +/* hwrm_udcc_qcaps_input (size:128b/16B) */ + +typedef struct hwrm_udcc_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_udcc_qcaps_input_t, *phwrm_udcc_qcaps_input_t; + +/* hwrm_udcc_qcaps_output (size:192b/24B) */ + +typedef struct hwrm_udcc_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This field represents guaranteed minimum number of UDCC sessions + * available to the function. + */ + uint16_t min_sessions; + /* + * This field represents unguaranteed maximum number of UDCC sessions + * available to the function. + */ + uint16_t max_sessions; + /* + * This value indicates the type of session being modified by the + * UDCC. + */ + uint8_t session_type; + /* sessions are allocated on a per destination basis. */ + #define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_DESTINATION UINT32_C(0x0) + /* sessions are allocated on a per QP basis. */ + #define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_QP UINT32_C(0x1) + #define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_LAST HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_QP + uint8_t unused_0[3]; + /* + * This field represents the maximum number of bytes of UDCC program + * configuration data that one hwrm_udcc_comp_cfg request or + * hwrm_udcc_comp_qcfg response can transfer. + * The value is determined by the UDCC firmware. + */ + uint16_t max_comp_cfg_xfer; + /* + * This field represents the maximum number of bytes of UDCC program + * status or statistics data that one hwrm_udcc_comp_query response + * can transfer. The value is determined by the UDCC firmware. + */ + uint16_t max_comp_data_xfer; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_qcaps_output_t, *phwrm_udcc_qcaps_output_t; + +/***************** + * hwrm_udcc_cfg * + *****************/ + + +/* hwrm_udcc_cfg_input (size:192b/24B) */ + +typedef struct hwrm_udcc_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the udcc_mode field to be + * configured. + */ + #define HWRM_UDCC_CFG_INPUT_ENABLES_UDCC_MODE UINT32_C(0x1) + /* UDCC mode for this function. */ + uint8_t udcc_mode; + /* UDCC is not enabled. */ + #define HWRM_UDCC_CFG_INPUT_UDCC_MODE_DISABLED UINT32_C(0x0) + /* UDCC is enabled. */ + #define HWRM_UDCC_CFG_INPUT_UDCC_MODE_ENABLED UINT32_C(0x1) + #define HWRM_UDCC_CFG_INPUT_UDCC_MODE_LAST HWRM_UDCC_CFG_INPUT_UDCC_MODE_ENABLED + uint8_t unused_1[3]; +} hwrm_udcc_cfg_input_t, *phwrm_udcc_cfg_input_t; + +/* hwrm_udcc_cfg_output (size:128b/16B) */ + +typedef struct hwrm_udcc_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_cfg_output_t, *phwrm_udcc_cfg_output_t; + +/****************** + * hwrm_udcc_qcfg * + ******************/ + + +/* hwrm_udcc_qcfg_input (size:128b/16B) */ + +typedef struct hwrm_udcc_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} hwrm_udcc_qcfg_input_t, *phwrm_udcc_qcfg_input_t; + +/* hwrm_udcc_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_udcc_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* UDCC mode for this function. */ + uint8_t udcc_mode; + uint8_t unused_1[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_qcfg_output_t, *phwrm_udcc_qcfg_output_t; + +/************************* + * hwrm_udcc_session_cfg * + *************************/ + + +/* hwrm_udcc_session_cfg_input (size:384b/48B) */ + +typedef struct hwrm_udcc_session_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* This bit must be '1' for the session_state to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SESSION_STATE UINT32_C(0x1) + /* This bit must be '1' for the dest_mac to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_DEST_MAC UINT32_C(0x2) + /* This bit must be '1' for the src_mac to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SRC_MAC UINT32_C(0x4) + /* This bit must be '1' for the tx_stats_record to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_TX_STATS_RECORD UINT32_C(0x8) + /* This bit must be '1' for the rx_stats_record to be configured. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_RX_STATS_RECORD UINT32_C(0x10) + /* State to configure for the session. */ + uint8_t session_state; + /* + * This bit is set if the session is to be enabled and have firmware + * querying it for events. The bit is cleared if the session is to + * be disabled in firmware. + */ + #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_ENABLED UINT32_C(0x1) + /* UDCC flow is not created in driver. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_NOT_CREATED UINT32_C(0x2) + /* UDCC flow is now deleted in driver. */ + #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED UINT32_C(0x4) + uint8_t unused_1; + /* A handle for the session to be configured, if previously allocated. */ + uint16_t session_id; + /* destination mac address used for the session. */ + uint8_t dest_mac[6]; + uint16_t unused_2; + /* source mac address used for the session. */ + uint8_t src_mac[6]; + uint16_t unused_3; + /* + * address for the tx flow statistics record to be sampled by the + * UDCC firmware. Session must be disabled to take effect. + */ + uint32_t tx_stats_record; + /* + * address for the rx flow statistics record to be sampled by the + * UDCC firmware. Session must be disabled to take effect. + */ + uint32_t rx_stats_record; +} hwrm_udcc_session_cfg_input_t, *phwrm_udcc_session_cfg_input_t; + +/* hwrm_udcc_session_cfg_output (size:128b/16B) */ + +typedef struct hwrm_udcc_session_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_session_cfg_output_t, *phwrm_udcc_session_cfg_output_t; + +/************************** + * hwrm_udcc_session_qcfg * + **************************/ + + +/* hwrm_udcc_session_qcfg_input (size:192b/24B) */ + +typedef struct hwrm_udcc_session_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* A handle for the session to be queried, if previously allocated. */ + uint16_t session_id; + uint8_t unused_0[6]; +} hwrm_udcc_session_qcfg_input_t, *phwrm_udcc_session_qcfg_input_t; + +/* hwrm_udcc_session_qcfg_output (size:512b/64B) */ + +typedef struct hwrm_udcc_session_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* session_state specifying configuration of the session. */ + uint8_t session_state; + /* + * This bit is set if the session is enabled and firmware is + * querying it for events. The bit is cleared if no querying + * should occur for this session. + */ + #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_ENABLED UINT32_C(0x1) + /* UDCC flow is not created in driver. */ + #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_NOT_CREATED UINT32_C(0x2) + /* UDCC flow is now deleted in driver. */ + #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED UINT32_C(0x4) + uint8_t unused_0; + /* destination mac address used for the session. */ + uint8_t dest_mac[6]; + /* + * a 4 byte or 16 byte IP address, depending on whether the ip_type + * specifies IPv4 or IPv6. For IPv4 addresses, the first 4 bytes of the + * 16 byte field are used; the remaining 12 bytes are not used. + */ + uint32_t dest_ip[4]; + uint8_t unused_1[2]; + /* source mac address used for the session. */ + uint8_t src_mac[6]; + /* source QP number used for the session. */ + uint32_t src_qp_num; + /* destination QP number used for the session. */ + uint32_t dest_qp_num; + /* + * address for the tx flow statistics record to be sampled by the + * UDCC firmware. + */ + uint32_t tx_stats_record; + /* + * address for the rx flow statistics record to be sampled by the + * UDCC firmware. + */ + uint32_t rx_stats_record; + uint8_t unused_2[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_session_qcfg_output_t, *phwrm_udcc_session_qcfg_output_t; + +/*************************** + * hwrm_udcc_session_query * + ***************************/ + + +/* hwrm_udcc_session_query_input (size:192b/24B) */ + +typedef struct hwrm_udcc_session_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* A handle for the session to be queried, if previously allocated. */ + uint16_t session_id; + uint8_t unused_0[6]; +} hwrm_udcc_session_query_input_t, *phwrm_udcc_session_query_input_t; + +/* hwrm_udcc_session_query_output (size:576b/72B) */ + +typedef struct hwrm_udcc_session_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* field for the minimum RTT value (in ns) for the session. */ + uint32_t min_rtt_ns; + /* field for the maximum RTT value (in ns) for the session. */ + uint32_t max_rtt_ns; + /* + * field for the current configured rate (in Mbps) for the + * session. + */ + uint32_t cur_rate_mbps; + /* + * count for the number of events sent from FW to the UDCC + * program. + */ + uint32_t tx_event_count; + /* + * count for the number of CNP events sent from FW to the UDCC + * program. + */ + uint32_t cnp_rx_event_count; + /* + * count for the number of RTT request events received by the FW from + * the UDCC program. + */ + uint32_t rtt_req_count; + /* + * count for the number of RTT response events sent by the FW to the + * UDCC program. + */ + uint32_t rtt_resp_count; + /* count for the number of bytes transmitted for the session. */ + uint32_t tx_bytes_count; + /* count for the number of packets transmitted for the session. */ + uint32_t tx_packets_count; + /* count of initiator probes transmitted for the session. */ + uint32_t init_probes_sent; + /* count of terminator probes received for the session. */ + uint32_t term_probes_recv; + /* count of CNP packets received for the session. */ + uint32_t cnp_packets_recv; + /* count of retransmission timeout events received for the session. */ + uint32_t rto_event_recv; + /* count of sequence error NAK events received for the session. */ + uint32_t seq_err_nak_recv; + /* the current number of qps associated with the session. */ + uint32_t qp_count; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_session_query_output_t, *phwrm_udcc_session_query_output_t; + +/********************** + * hwrm_udcc_comp_cfg * + **********************/ + + +/* hwrm_udcc_comp_cfg_input (size:576b/72B) */ + +typedef struct hwrm_udcc_comp_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This field holds the configuration arguments, which can be used + * to specify the context of the configuration data, e.g. type, + * session ID, etc. It is possible not all arg_buf are utilized. + * The format and meaning of the arguments are internal to + * the UDCC program. + */ + uint8_t arg_buf[40]; + /* + * This field specifies the number of bytes in arg_buf that are + * configuration arguments. It can be zero if there are no arguments. + */ + uint32_t arg_len; + /* + * This field specifies the length of the configuration data + * stored in the host memory. The host driver shall guarantee + * this number is not greater than the maximum configuration + * transfer size that is specified by the max_comp_cfg_xfer + * field of hwrm_udcc_qcaps_output. + */ + uint32_t cfg_len; + /* + * This field specifies the address of the host memory where + * the configuration data is stored. The format and meaning of + * the configuration data are internal to the UDCC program. + */ + uint64_t cfg_host_addr; +} hwrm_udcc_comp_cfg_input_t, *phwrm_udcc_comp_cfg_input_t; + +/* hwrm_udcc_comp_cfg_output (size:128b/16B) */ + +typedef struct hwrm_udcc_comp_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_comp_cfg_output_t, *phwrm_udcc_comp_cfg_output_t; + +/*********************** + * hwrm_udcc_comp_qcfg * + ***********************/ + + +/* hwrm_udcc_comp_qcfg_input (size:576b/72B) */ + +typedef struct hwrm_udcc_comp_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This field holds the query arguments, which can be used to + * specify the context of the query, e.g. type, session ID, etc. + * It is possible not all arg_buf are utilized. + * The format and meaning of the arguments are internal to + * the UDCC program. + */ + uint8_t arg_buf[40]; + /* + * This field specifies the number of bytes in arg_buf that are + * query arguments. It can be zero if there are no arguments. + */ + uint32_t arg_len; + /* + * This field specifies the size of the buffer in the host memory + * for receiving the configuration data. The host driver shall + * guarantee the size of the buffer is not smaller than + * the maximum configuration transfer size that is specified by + * the max_comp_cfg_xfer field of hwrm_udcc_qcaps_output. + */ + uint32_t cfg_host_buf_size; + /* + * This field specifies the address of the host memory where + * the queried configuration to be stored. + */ + uint64_t cfg_host_addr; +} hwrm_udcc_comp_qcfg_input_t, *phwrm_udcc_comp_qcfg_input_t; + +/* hwrm_udcc_comp_qcfg_output (size:128b/16B) */ + +typedef struct hwrm_udcc_comp_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This field specifies the length of configuration data transferred + * into the host memory. The amount of data transferred is up to + * the maximum configuration transfer size that is specified by + * the max_comp_cfg_xfer field of hwrm_udcc_qcaps_output. + */ + uint32_t cfg_len; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_comp_qcfg_output_t, *phwrm_udcc_comp_qcfg_output_t; + +/************************ + * hwrm_udcc_comp_query * + ************************/ + + +/* hwrm_udcc_comp_query_input (size:576b/72B) */ + +typedef struct hwrm_udcc_comp_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This field holds the query arguments, which can be used to + * specify the context of the query, e.g. type, session ID, etc. + * It is possible not all arg_buf are utilized. + * The format and meaning of the arguments are internal to + * the UDCC program. + */ + uint8_t arg_buf[40]; + /* + * This field specifies the number of bytes in arg_buf that are + * query arguments. It can be zero if there are no arguments. + */ + uint32_t arg_len; + /* + * This field specifies the size of the buffer in the host memory + * for receiving the status or statistics data. The host driver + * shall guarantee the size of the buffer is not smaller than + * the maximum data transfer size that is specified by + * the max_comp_data_xfer field of hwrm_udcc_qcaps_output. + */ + uint32_t data_host_buf_size; + /* + * This field specifies the address of the host memory where + * the queried data to be stored. + */ + uint64_t data_host_addr; +} hwrm_udcc_comp_query_input_t, *phwrm_udcc_comp_query_input_t; + +/* hwrm_udcc_comp_query_output (size:128b/16B) */ + +typedef struct hwrm_udcc_comp_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This field specifies the length of status or statistics data + * transferred into the host memory. The amount of data transferred + * is up to the maximum data transfer size that is specified by + * the max_comp_data_xfer field of hwrm_udcc_qcaps_output. + */ + uint32_t data_len; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} hwrm_udcc_comp_query_output_t, *phwrm_udcc_comp_query_output_t; + #endif /* _HSI_STRUCT_DEF_H_ */