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cxgbe(4): T7 related updates to shared code

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- Avoid some more registers with read side-effects during regdump.
- mps_tcam_size is 3x the size of T6/T5.
- Update rss_rd_row to work with T7.

Obtained from:	Chelsio Communications
MFC after:	1 week
Sponsored by:	Chelsio Communications
This commit is contained in:
Navdeep Parhar
2025-10-15 12:29:06 -07:00
parent 4b17bb0ede
commit 17b4a0acfa
5 changed files with 723 additions and 169 deletions
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usr.sbin/cxgbetool/reg_defs_t7.c
+69 -57
View File
@@ -1,6 +1,6 @@
/* This file is automatically generated --- changes will be lost */
/* Generation Date : Thu Sep 11 05:26:14 PM IST 2025 */
/* Directory name: t7_reg.txt, Changeset: 5945:1487219ecb20 */
/* Generation Date : Tue Oct 28 05:24:53 PM IST 2025 */
/* Directory name: t7_sw_reg.txt, Changeset: 5946:0b60ff298e7d */
struct reg_info t7_sge_regs[] = {
{ "SGE_PF_KDOORBELL", 0x1e000, 0 },
@@ -1546,17 +1546,6 @@ struct reg_info t7_pcie_regs[] = {
{ "PERstTimeout", 8, 1 },
{ "PERstTimer", 0, 4 },
{ "PCIE_CFG7", 0x302c, 0 },
{ "PCIE_CFG_SPACE_REQ", 0x3060, 0 },
{ "Enable", 31, 1 },
{ "AI", 30, 1 },
{ "CS2", 29, 1 },
{ "WrBE", 25, 4 },
{ "VFVld", 24, 1 },
{ "RVF", 16, 8 },
{ "PF", 12, 3 },
{ "ExtRegister", 8, 4 },
{ "Register", 0, 8 },
{ "PCIE_CFG_SPACE_DATA", 0x3064, 0 },
{ "PCIE_MAILBOX_BASE_WIN", 0x30a4, 0 },
{ "PCIEOfst", 6, 26 },
{ "BIR", 4, 2 },
@@ -1591,15 +1580,6 @@ struct reg_info t7_pcie_regs[] = {
{ "PCIE_STATIC_CFG2", 0x30e8, 0 },
{ "PL_CONTROL", 16, 16 },
{ "STATIC_SPARE3", 0, 15 },
{ "PCIE_DBG_INDIR_REQ", 0x30ec, 0 },
{ "Enable", 31, 1 },
{ "AI", 30, 1 },
{ "Pointer", 8, 16 },
{ "Select", 0, 4 },
{ "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 },
{ "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 },
{ "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 },
{ "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 },
{ "PCIE_PF_INT_CFG", 0x3140, 0 },
{ "PBAOfst", 28, 4 },
{ "TABOfst", 24, 4 },
@@ -3136,14 +3116,6 @@ struct reg_info t7_pcie_regs[] = {
{ "PCIE_X8_CORE_PIPE_CONTROL", 0x48b8, 0 },
{ "Loopback_Enable", 31, 1 },
{ "PCIE_X8_CORE_DBI_RO_WE", 0x48bc, 0 },
{ "PCIE_X8_CFG_SPACE_REQ", 0x48c0, 0 },
{ "Enable", 31, 1 },
{ "AI", 30, 1 },
{ "CS2", 29, 1 },
{ "WrBE", 25, 4 },
{ "ExtRegister", 8, 4 },
{ "Register", 0, 8 },
{ "PCIE_X8_CFG_SPACE_DATA", 0x48c4, 0 },
{ "PCIE_X8_CFG_MPS_MRS", 0x4900, 0 },
{ "MRS", 3, 3 },
{ "MPS", 0, 3 },
@@ -3513,10 +3485,6 @@ struct reg_info t7_pcie_regs[] = {
{ "PCIE_PHY_PRESET_COEFF", 0x5be4, 0 },
{ "PCIE_PHY_PRESET_COEFF", 0x5be8, 0 },
{ "PCIE_PHY_PRESET_COEFF", 0x5bec, 0 },
{ "PCIE_PHY_INDIR_REQ", 0x5bf0, 0 },
{ "Enable", 31, 1 },
{ "RegAddr", 0, 16 },
{ "PCIE_PHY_INDIR_DATA", 0x5bf4, 0 },
{ "PCIE_STATIC_SPARE1", 0x5bf8, 0 },
{ "PCIE_STATIC_SPARE2", 0x5bfc, 0 },
{ "x8_sw_en", 30, 1 },
@@ -3606,13 +3574,6 @@ struct reg_info t7_pcie_regs[] = {
{ "Phy_Reg_Select", 22, 2 },
{ "Phy_Reg_RegAddr", 0, 16 },
{ "PCIE_MULTI_PHY_INDIR_DATA", 0x5c40, 0 },
{ "PCIE_VF_INT_INDIR_REQ", 0x5c44, 0 },
{ "Enable", 24, 1 },
{ "AI", 23, 1 },
{ "VFID", 0, 10 },
{ "PCIE_VF_INT_INDIR_DATA", 0x5c48, 0 },
{ "VecNum", 12, 10 },
{ "VecBase", 0, 12 },
{ "PCIE_VF_256_INT_CFG2", 0x5c4c, 0 },
{ "SendFLRRsp", 31, 1 },
{ "ImmFLRRsp", 24, 1 },
@@ -4300,15 +4261,6 @@ struct reg_info t7_pcie_regs[] = {
{ "ByteEnable", 26, 4 },
{ "RegAddr", 0, 15 },
{ "PCIE_SWITCH_CFG_SPACE_DATA8", 0x5f78, 0 },
{ "PCIE_SNPS_G5_PHY_CR_REQ", 0x5f7c, 0 },
{ "RegSel", 31, 1 },
{ "RdEnable", 30, 1 },
{ "WrEnable", 29, 1 },
{ "AutoIncrVal", 21, 2 },
{ "AutoIncr", 20, 1 },
{ "PhySel", 16, 4 },
{ "RegAddr", 0, 16 },
{ "PCIE_SNPS_G5_PHY_CR_DATA", 0x5f80, 0 },
{ "PCIE_SNPS_G5_PHY_SRAM_CFG", 0x5f84, 0 },
{ "phy3_sram_bootload_bypass", 27, 1 },
{ "phy3_sram_bypass", 26, 1 },
@@ -8895,10 +8847,6 @@ struct reg_info t7_mps_regs[] = {
{ "MPS_FPGA_BIST_CFG_P3", 0x912c, 0 },
{ "AddrMask", 16, 16 },
{ "BaseAddr", 0, 16 },
{ "MPS_INIC_CTL", 0x9130, 0 },
{ "RD_WRN", 16, 1 },
{ "ADDR", 0, 16 },
{ "MPS_INIC_DATA", 0x9134, 0 },
{ "MPS_RED_CTL", 0x9140, 0 },
{ "LPBK_SHIFT_0", 28, 4 },
{ "LPBK_SHIFT_1", 24, 4 },
@@ -9279,7 +9227,19 @@ struct reg_info t7_mps_regs[] = {
{ "xgmac2mps_rx0_perr", 25, 1 },
{ "xgmac2mps_rx1_perr", 24, 1 },
{ "mps2crypto_rx_intf_fifo", 20, 4 },
{ "RX_PRE_PROC_PERR", 9, 11 },
{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
{ "mac_rx_pproc_lb_ch3", 18, 1 },
{ "mac_rx_pproc_lb_ch2", 17, 1 },
{ "mac_rx_pproc_lb_ch1", 16, 1 },
{ "mac_rx_pproc_lb_ch0", 15, 1 },
{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
{ "mac_rx_fifo_perr", 13, 1 },
{ "mac2mps_pt3_perr", 12, 1 },
{ "mac2mps_pt2_perr", 11, 1 },
{ "mac2mps_pt1_perr", 10, 1 },
{ "mac2mps_pt0_perr", 9, 1 },
{ "lpbk_fifo_perr", 8, 1 },
{ "tp2mps_tf_fifo_perr", 7, 1 },
{ "MPS_RX_PERR_INT_ENABLE2", 0x11090, 0 },
{ "crypt2mps_rx_intf_fifo", 28, 4 },
{ "inic2mps_tx0_perr", 27, 1 },
@@ -9287,7 +9247,19 @@ struct reg_info t7_mps_regs[] = {
{ "xgmac2mps_rx0_perr", 25, 1 },
{ "xgmac2mps_rx1_perr", 24, 1 },
{ "mps2crypto_rx_intf_fifo", 20, 4 },
{ "RX_PRE_PROC_PERR", 9, 11 },
{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
{ "mac_rx_pproc_lb_ch3", 18, 1 },
{ "mac_rx_pproc_lb_ch2", 17, 1 },
{ "mac_rx_pproc_lb_ch1", 16, 1 },
{ "mac_rx_pproc_lb_ch0", 15, 1 },
{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
{ "mac_rx_fifo_perr", 13, 1 },
{ "mac2mps_pt3_perr", 12, 1 },
{ "mac2mps_pt2_perr", 11, 1 },
{ "mac2mps_pt1_perr", 10, 1 },
{ "mac2mps_pt0_perr", 9, 1 },
{ "lpbk_fifo_perr", 8, 1 },
{ "tp2mps_tf_fifo_perr", 7, 1 },
{ "MPS_RX_PERR_ENABLE2", 0x11094, 0 },
{ "crypt2mps_rx_intf_fifo", 28, 4 },
{ "inic2mps_tx0_perr", 27, 1 },
@@ -9295,7 +9267,19 @@ struct reg_info t7_mps_regs[] = {
{ "xgmac2mps_rx0_perr", 25, 1 },
{ "xgmac2mps_rx1_perr", 24, 1 },
{ "mps2crypto_rx_intf_fifo", 20, 4 },
{ "RX_PRE_PROC_PERR", 9, 11 },
{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
{ "mac_rx_pproc_lb_ch3", 18, 1 },
{ "mac_rx_pproc_lb_ch2", 17, 1 },
{ "mac_rx_pproc_lb_ch1", 16, 1 },
{ "mac_rx_pproc_lb_ch0", 15, 1 },
{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
{ "mac_rx_fifo_perr", 13, 1 },
{ "mac2mps_pt3_perr", 12, 1 },
{ "mac2mps_pt2_perr", 11, 1 },
{ "mac2mps_pt1_perr", 10, 1 },
{ "mac2mps_pt0_perr", 9, 1 },
{ "lpbk_fifo_perr", 8, 1 },
{ "tp2mps_tf_fifo_perr", 7, 1 },
{ "MPS_RX_PERR_INT_CAUSE3", 0x11310, 0 },
{ "MPS_RX_PERR_INT_ENABLE3", 0x11314, 0 },
{ "MPS_RX_PERR_ENABLE3", 0x11318, 0 },
@@ -22654,6 +22638,14 @@ struct reg_info t7_mac_t7_regs[] = {
{ "TX_CDR_LANE_SEL", 3, 3 },
{ "RX_CDR_LANE_SEL", 0, 3 },
{ "MAC_DEBUG_PL_IF_1", 0x381c4, 0 },
{ "MAC_HSS0_ANALOG_TEST_CTRL", 0x381d0, 0 },
{ "MAC_HSS1_ANALOG_TEST_CTRL", 0x381d4, 0 },
{ "MAC_HSS2_ANALOG_TEST_CTRL", 0x381d8, 0 },
{ "MAC_HSS3_ANALOG_TEST_CTRL", 0x381dc, 0 },
{ "MAC_HSS0_ANALOG_TEST_STATUS", 0x381e0, 0 },
{ "MAC_HSS1_ANALOG_TEST_STATUS", 0x381e4, 0 },
{ "MAC_HSS2_ANALOG_TEST_STATUS", 0x381e8, 0 },
{ "MAC_HSS3_ANALOG_TEST_STATUS", 0x381ec, 0 },
{ "MAC_SIGNAL_DETECT_CTRL", 0x381f0, 0 },
{ "Signal_Det_ln7", 15, 1 },
{ "Signal_Det_ln6", 14, 1 },
@@ -24583,6 +24575,26 @@ struct reg_info t7_mac_t7_regs[] = {
{ "Q1_LOS_2_assert", 2, 1 },
{ "Q1_LOS_1_assert", 1, 1 },
{ "Q1_LOS_0_assert", 0, 1 },
{ "MAC_HSS0_PMD_RECEIVE_SIGNAL_DETECT", 0x3a93c, 0 },
{ "pmd_receive_signal_detect_1n3", 4, 1 },
{ "pmd_receive_signal_detect_1n2", 3, 1 },
{ "pmd_receive_signal_detect_ln1", 2, 1 },
{ "pmd_receive_signal_detect_1n0", 1, 1 },
{ "MAC_HSS1_PMD_RECEIVE_SIGNAL_DETECT", 0x3b93c, 0 },
{ "pmd_receive_signal_detect_1n3", 4, 1 },
{ "pmd_receive_signal_detect_1n2", 3, 1 },
{ "pmd_receive_signal_detect_ln1", 2, 1 },
{ "pmd_receive_signal_detect_1n0", 1, 1 },
{ "MAC_HSS2_PMD_RECEIVE_SIGNAL_DETECT", 0x3c93c, 0 },
{ "pmd_receive_signal_detect_1n3", 4, 1 },
{ "pmd_receive_signal_detect_1n2", 3, 1 },
{ "pmd_receive_signal_detect_ln1", 2, 1 },
{ "pmd_receive_signal_detect_1n0", 1, 1 },
{ "MAC_HSS3_PMD_RECEIVE_SIGNAL_DETECT", 0x3d93c, 0 },
{ "pmd_receive_signal_detect_1n3", 4, 1 },
{ "pmd_receive_signal_detect_1n2", 3, 1 },
{ "pmd_receive_signal_detect_ln1", 2, 1 },
{ "pmd_receive_signal_detect_1n0", 1, 1 },
{ "MAC_MTIP_PCS_1G_0_CONTROL", 0x3e000, 0 },
{ "Reset", 15, 1 },
{ "Loopback", 14, 1 },